JP2005236602A

JP2005236602A - Semiconductor device

Info

Publication number: JP2005236602A
Application number: JP2004042429A
Authority: JP
Inventors: Kosuke Ota; 浩介太田
Original assignee: Matsushita Electric Industrial Co Ltd
Current assignee: Panasonic Holdings Corp
Priority date: 2004-02-19
Filing date: 2004-02-19
Publication date: 2005-09-02

Abstract

<P>PROBLEM TO BE SOLVED: To reduce spurious caused by interference, when one chip has a plurality of differential-configuration oscillators. <P>SOLUTION: The output signal of the first oscillator and the output signal of the second oscillator cancel diffracted signals, each being an interference component through making attenuated the output signal of the first oscillator which is the negative phase component of the interference component to the second oscillator and diffracted from the first oscillator, by means of a signal attenuator to inject the output signal of the first oscillator into the input of the second oscillator; and attenuating the output signal of the second oscillator which is the negative phase component of the interference component to the first oscillator and diffracted from the second oscillator, by means of a signal attenuator to inject the output signal of the second oscillator into the input of the first oscillator. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、同一チップ内に複数の差動構成の発振器を有する半導体装置に関するものである。 The present invention relates to a semiconductor device having a plurality of differentially configured oscillators in the same chip.

近年、半導体集積回路の高集積化、送受信機用半導体回路の高付加価値化と、セットの小型化による部品数削減のために、複数の差動構成の発振器の同一チップ内への内蔵が行われている。 In recent years, multiple differential oscillators have been built in the same chip in order to increase the integration of semiconductor integrated circuits, increase the added value of semiconductor circuits for transceivers, and reduce the number of parts by reducing the size of sets. It has been broken.

図４では簡素化のために２つの差動構成の発振器の例について説明する。従来は、図４のように同一チップ内に複数の差動構成の発振器を有し、互いに異なった周波数の信号を発生させている。これらの異なった周波数を発生させる発振器は、ノイズの悪化や、様々な規格等を考慮した場合、相互に干渉しないことが望まれる。しかしながら、上記のように、半導体回路の高集積化が進んでいると同時に、セットの小型化やコスト削減によりチップの小型化が行われているために、複数の差動構成の発振器を近傍に配置せざるを得ない。このため、複数の差動構成の発振器が相互に干渉しスプリアスを発生する場合がある。 FIG. 4 illustrates an example of two differential oscillators for the sake of simplicity. Conventionally, as shown in FIG. 4, a plurality of differentially configured oscillators are provided in the same chip, and signals having different frequencies are generated. It is desirable that the oscillators that generate these different frequencies do not interfere with each other in consideration of noise deterioration and various standards. However, as described above, the integration of semiconductor circuits is progressing, and at the same time, the size of the chip is reduced by reducing the size of the set and reducing the cost. It must be placed. For this reason, a plurality of differentially configured oscillators may interfere with each other to generate spurious.

干渉を低減する対策として例えば特許文献１があげられる。
特開平８−３３１００５号公報 For example, Patent Document 1 is cited as a measure for reducing the interference.
JP-A-8-332005

本来、発振器の出力信号が差動出力であれば、他方の発振器からの回り込みは同相信号のため相殺しあい、干渉によるスプリアスは発生しないが、発振器の配置が近い場合や、基盤パターン、ボンディングワイヤなど様々な要因で回り込む信号の差動のバランスが崩れてしまい、他の発振器に差動出力信号のどちらかが回り込み、相互に干渉する場合が発生する。その干渉により数１で表される周波数のスプリアスが図５の３１−１、３１−２のように発生する問題がある。 Originally, if the output signal of the oscillator is a differential output, the sneak from the other oscillator cancels out because it is an in-phase signal, and spurious due to interference does not occur. For example, the differential balance of the sneaking signal may be lost due to various factors, and one of the differential output signals may sneak into another oscillator and interfere with each other. Due to the interference, there is a problem that spurious frequencies having the frequency expressed by Equation 1 are generated as indicated by 31-1 and 31-2 in FIG.

本発明は、このような従来の問題点を鑑みてなされたものであり、発振器どうしの干渉により発生するスプリアスの低減をすることで、複数の発振器の1チップ化を可能にすることを目的とする。 The present invention has been made in view of such conventional problems, and has an object of enabling a plurality of oscillators to be made into one chip by reducing spurious generated by interference between the oscillators. To do.

前記の目的を達成するために、本発明は第１の発振器から回り込む第２の発振器への干渉成分の逆相成分にあたる第１の発振器の出力信号を信号減衰器で減衰させて第２の発振器の入力へ注入し、第２の発振器から回り込む第１の発振器への干渉成分の逆相成分にあたる第２の発振器の出力信号を信号減衰器で減衰させて第１の発振器の入力へ注入し、干渉成分である回り込んだ信号と相殺させたものである。 In order to achieve the above-mentioned object, the present invention attenuates the output signal of the first oscillator corresponding to the anti-phase component of the interference component to the second oscillator that wraps around from the first oscillator by the signal attenuator. The output signal of the second oscillator corresponding to the anti-phase component of the interference component to the first oscillator that circulates from the second oscillator is attenuated by the signal attenuator and injected to the input of the first oscillator. This is offset with the sneak signal that is the interference component.

干渉しあっている第１の発振器の出力と、第２の発振器の入力とを減衰器を通して接続し、第２の発振器の出力と、第１の発振器の入力とを減衰器を通して接続する。 The interfering output of the first oscillator and the input of the second oscillator are connected through an attenuator, and the output of the second oscillator and the input of the first oscillator are connected through an attenuator.

また、減衰器による減衰量は、その出力信号が干渉成分を打ち消すように調整する。 Further, the amount of attenuation by the attenuator is adjusted so that the output signal cancels the interference component.

本発明に係る半導体装置は上記構成を有し、複数の発振器どうしの干渉により発生するスプリアスを低減することができる。 The semiconductor device according to the present invention has the above-described configuration, and can reduce spurious generated by interference between a plurality of oscillators.

（第１の実施形態）
以下、本発明の第１の実施形態に係る構造について、図面を参照しながら説明する。本発明は複数の差動構成の発振器を同一チップ内に有するものだが説明の簡素化のため２つの差動構成の発振器の実施例で説明する。 (First embodiment)
Hereinafter, a structure according to a first embodiment of the present invention will be described with reference to the drawings. Although the present invention has a plurality of differentially configured oscillators in the same chip, for the sake of simplicity of explanation, an example of two differentially configured oscillators will be described.

まず、図１に示すように同一のチップ１内に第１の差動構成の発振器２と第２の差動構成の発振器３を有し、発振器２の出力バッファ７の出力を第１の減衰器６−１を通して発振器３の入力に接続し、発振器３の出力バッファ８の出力を第２の減衰器６−２を通して発振器２の入力に接続している。１１、１２はそれぞれ発振器２と発振器３の出力信号である。１５は減衰器６−１の通過後の発振器２の出力成分、１６は減衰器６−２の通過後の発振器３の出力成分である。 First, as shown in FIG. 1, an oscillator 2 having a first differential configuration and an oscillator 3 having a second differential configuration are included in the same chip 1, and the output of an output buffer 7 of the oscillator 2 is subjected to a first attenuation. The output of the output buffer 8 of the oscillator 3 is connected to the input of the oscillator 2 through the second attenuator 6-2. Reference numerals 11 and 12 denote output signals of the oscillator 2 and the oscillator 3, respectively. 15 is an output component of the oscillator 2 after passing through the attenuator 6-1, and 16 is an output component of the oscillator 3 after passing through the attenuator 6-2.

発振器２、発振器３は同一チップ上に構成されるため様々な要因による寄生成分１０が存在するために、相互に他の発振器から回り込み、干渉信号１３、干渉信号１４が発生する。干渉信号１３、干渉信号１４はチップのレイアウト等の寄生成分１０を考慮したシミュレーションにより評価可能である。 Since the oscillator 2 and the oscillator 3 are configured on the same chip, the parasitic component 10 due to various factors exists, and therefore, the interference signal 13 and the interference signal 14 are generated from each other. The interference signal 13 and the interference signal 14 can be evaluated by simulation in consideration of the parasitic component 10 such as chip layout.

１７、１８は発振器２の入力トランジスタのコレクタ、１９、２０は発振器３の入力トランジスタのコレクタである。 Reference numerals 17 and 18 denote collectors of the input transistors of the oscillator 2, and reference numerals 19 and 20 denote collectors of the input transistors of the oscillator 3.

図１では、減衰器６−１の出力をコレクタ２０に、減衰器６−２の出力をコレクタ１７に接続しているが、寄生成分１０を考慮したシミュレーションによる干渉信号１３、１４の振幅、位相に対して逆位相となる信号を選択的に接続する。 In FIG. 1, the output of the attenuator 6-1 is connected to the collector 20, and the output of the attenuator 6-2 is connected to the collector 17. However, the amplitude and phase of the interference signals 13 and 14 by simulation taking the parasitic component 10 into consideration. Are selectively connected to signals having opposite phases.

また、振幅は干渉信号１３、１４と等しくなるように、減衰器６−１と減衰器６−２の減衰量で決める。 Further, the amplitude is determined by the attenuation amounts of the attenuator 6-1 and the attenuator 6-2 so as to be equal to the interference signals 13 and 14.

減衰器出力を干渉成分と等振幅、逆位相となるようにすることで、発振器どうしの相互干渉によって発生するスプリアスは低減する。 By setting the attenuator output to have the same amplitude and opposite phase as the interference component, spurious generated by mutual interference between the oscillators is reduced.

（第２の実施形態）
まず、図２に示すように同一のチップ１内に第１の差動構成の発振器２と第２の差動構成の発振器３を有し、発振器２の共振器４と発振器３の共振器５の間を減衰器６−３が接続している。１５は減衰器６−３通過後の発振器２の出力成分、１６は減衰器６−３通過後の発振器３の出力成分である。 (Second Embodiment)
First, as shown in FIG. 2, the same chip 1 has a first differential oscillator 2 and a second differential oscillator 3, and the resonator 4 of the oscillator 2 and the resonator 5 of the oscillator 3. Attenuator 6-3 is connected between the two. 15 is an output component of the oscillator 2 after passing through the attenuator 6-3, and 16 is an output component of the oscillator 3 after passing through the attenuator 6-3.

１０〜１４は第１の実施形態で説明済みのため省略する。 Since 10 to 14 are already described in the first embodiment, they are omitted.

図２では、減衰器６−３の出力をコレクタ２０とコレクタ１７に接続しているが、寄生成分１０を考慮したシミュレーションによる干渉信号１３、１４の振幅、位相に対して逆位相となる側に選択的に接続する。 In FIG. 2, the output of the attenuator 6-3 is connected to the collector 20 and the collector 17, but on the side that is opposite in phase to the amplitude and phase of the interference signals 13 and 14 by simulation considering the parasitic component 10. Selectively connect.

また、振幅は干渉信号１３、１４と等しくなるように、減衰器６−３の減衰量で決める。 Further, the amplitude is determined by the attenuation amount of the attenuator 6-3 so as to be equal to the interference signals 13 and 14.

減衰器出力を干渉成分と等振幅、逆位相となるようにすることで、発振器どうしの相互干渉によって発生するスプリアスはひとつの減衰器の使用で低減する。 By setting the attenuator output to have the same amplitude and opposite phase as the interference component, spurious generated by mutual interference between the oscillators can be reduced by using one attenuator.

（第３の実施形態）
この第３の実施形態は、第２の実施形態の具体例である。 (Third embodiment)
The third embodiment is a specific example of the second embodiment.

まず、図３に示すように第２の実施形態では減衰器であったものを以下のように構成する。第１の差動構成の発振器２の共振器４と第２の差動構成の発振器３の共振器５の間を第１の抵抗９−１と第２の抵抗９−２が接続している。抵抗９−１と抵抗９−２の接続点と発振周波数において接地となる端子の間を第３の抵抗９−３が接続している。 First, as shown in FIG. 3, in the second embodiment, an attenuator is configured as follows. A first resistor 9-1 and a second resistor 9-2 are connected between the resonator 4 of the oscillator 2 having the first differential configuration and the resonator 5 of the oscillator 3 having the second differential configuration. . A third resistor 9-3 is connected between a connection point between the resistor 9-1 and the resistor 9-2 and a terminal that is grounded at the oscillation frequency.

抵抗９−１と可変することで減衰器出力１５の、抵抗９−２と可変することで減衰器出力１６の減衰量を調整する。 The attenuation of the attenuator output 15 is adjusted by changing the resistance 9-1, and the attenuation of the attenuator output 16 is adjusted by changing the resistance 9-2.

第３の実施形態によると、図６に示すように９〜１２ｄＢ程度改善することができる。 According to the third embodiment, it can be improved by about 9 to 12 dB as shown in FIG.

本発明に係る半導体装置は、複数の発振器同士の干渉により発生するスプリアスを低減することができる。 The semiconductor device according to the present invention can reduce spurious generated by interference between a plurality of oscillators.

本発明の第１の実施形態における半導体装置を示す図The figure which shows the semiconductor device in the 1st Embodiment of this invention 本発明の第２の実施形態における半導体装置を示す図The figure which shows the semiconductor device in the 2nd Embodiment of this invention. 本発明の第３の実施形態における半導体装置を示す図The figure which shows the semiconductor device in the 3rd Embodiment of this invention. 従来の実施形態における半導体装置を示す図The figure which shows the semiconductor device in conventional embodiment 従来の実施形態におけるスペクトラムを示す図The figure which shows the spectrum in conventional embodiment 本発明の第1の実施形態における半導体装置の実測による結果を示す図The figure which shows the result by the measurement of the semiconductor device in the 1st Embodiment of this invention

Explanation of symbols

１半導体チップ
２第１の差動構成の発振器
３第２の差動構成の発振器
４第１の差動構成の発振器の共振器
５第２の差動構成の発振器の共振器
６減衰器
７第１の差動構成の発振器の出力バッファ
８第２の差動構成の発振器の出力バッファ
９抵抗
10 寄生成分
11 第１の差動構成の発振器の出力信号
12 第２の差動構成の発振器の出力信号
13 第１の差動構成の発振器から、第２の差動構成の発振器へ回り込む干渉成分
14 第２の差動構成の発振器から、第１の差動構成の発振器へ回り込む干渉成分
15 減衰器通過後の第１の差動構成の発振器の出力成分
16 減衰器通過後の第２の差動構成の発振器の出力成分
17 第１の差動構成の発振器の第１の入力トランジスタのコレクタ
18 第１の差動構成の発振器の第２の入力トランジスタのコレクタ
19 第２の差動構成の発振器の第１の入力トランジスタのコレクタ
20 第２の差動構成の発振器の第２の入力トランジスタのコレクタ
30 第１の差動構成の発振器の出力信号のスペクトラム
31 干渉によるスプリアスのスペクトラム
32 第２の差動構成の発振器の出力信号のスペクトラム DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2 Oscillator of 1st differential structure 3 Oscillator of 2nd differential structure 4 Resonator of oscillator of 1st differential structure 5 Resonator of oscillator of 2nd differential structure 6 Attenuator 7 1st 1 differential configuration oscillator output buffer 8 second differential configuration output buffer 9 resistance
10 Parasitic components
11 Output signal of the first differential oscillator
12 Output signal of the second differential oscillator
13 Interference component that wraps around from the first differential oscillator to the second differential oscillator
14 Interference components that sneak into the first differential oscillator from the second differential oscillator
15 Output component of the first differential oscillator after passing through the attenuator
16 Output component of the second differential oscillator after passing through the attenuator
17 Collector of the first input transistor of the oscillator of the first differential configuration
18 Collector of second input transistor of oscillator of first differential configuration
19 Collector of the first input transistor of the oscillator of the second differential configuration
20 Collector of the second input transistor of the oscillator of the second differential configuration
30 Spectrum of the output signal of the first differential oscillator
31 Spurious spectrum due to interference
32 Spectrum of the output signal of the second differential oscillator

Claims

In a semiconductor device having a plurality of differentially configured oscillators in the same chip,
Connecting the output of the first oscillator to the input of the second oscillator via a first attenuator and connecting the output of the second oscillator to the input of the first oscillator via a second attenuator. A semiconductor device characterized by the above.

In a semiconductor device having a plurality of differentially configured oscillators in the same chip,
A semiconductor device comprising an attenuator for attenuating a signal between resonators of each oscillator.

In a semiconductor device having a plurality of differentially configured oscillators in the same chip,
A first resistor and a second resistor connected in series between the resonator of the first differential configuration oscillator and the resonator of the second differential configuration oscillator, the first resistance and the second resistance A semiconductor device having a third resistor between a connection point of the resistor and a terminal that is grounded at an oscillation frequency.