JP2005236350A - Ofdm demodulator - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an OFDM demodulator, applied to a digital radio communications system employing the OFDM modulation system such as terrestrial digital broadcast and a wireless LAN, capable of applying excellent weighting to a data signal by determining a proper threshold, even when a signal for estimating a transmission path is subjected to the effects of analog disturbance and noise or the like. <P>SOLUTION: A received power arithmetic circuit 9 calculates the received power of an SP signal by each prescribed number of symbols (e.g., one symbol, 4 symbols, or 12 symbols) from the SP signal stored in a RAM 8. An upper-limit generating circuit 10 generates upper limit for extracting a maximum value by each prescribed number of symbols. A maximum-value extracting circuit 19 receives the output value of the received power arithmetic circuit 9 via a delay circuit 18 for extracting the maximum value of the received power of the SP signal within a range of the upper limit received, form the upper-limit generating circuit 10 or smaller. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an OFDM demodulator suitable for use in a digital radio communication system using an OFDM (Orthogonal Frequency Division Multiplexing) modulation method such as terrestrial digital broadcasting or a wireless local area network (LAN).

  In an OFDM demodulator, weighting processing is usually performed on a data signal before Viterbi decoding, for example, a data signal output from a demapping circuit, in order to improve error correction processing capability (see, for example, Patent Document 1). ). A threshold is required for the weighting process, but in order to determine the threshold, the received power of the transmission path estimation signal (a signal for estimating the fluctuation of the subcarrier amplitude and phase generated by the transmission path) is calculated. It is necessary to extract the maximum value.

  FIG. 5 is a circuit diagram showing a main part of an example of a conventional OFDM demodulator that performs weighting processing on a data signal output from the demapping circuit. The OFDM demodulator shown in FIG. 5 is used for a terrestrial digital broadcast receiver. 1 is a RAM (Random Access Memory) for storing an SP (Scattered Pilot) signal, which is a transmission path estimation signal, and 2 is a predetermined one. This is a received power calculation circuit that calculates the received power of the SP signal for each number of symbols (for example, 1 symbol, 4 symbols, or 12 symbols).

  Reference numeral 3 denotes a maximum value extraction circuit that extracts a maximum value from the output value of the received power calculation circuit 2 for each predetermined number of symbols. Reference numeral 4 denotes a comparison circuit, and reference numeral 5 denotes a maximum value storage circuit. The comparison circuit 4 compares the output value of the received power calculation circuit 2 with the maximum value stored in the maximum value storage circuit 5, and if the output value of the received power calculation circuit 2 is larger, the comparison circuit 4 The output value is given to the maximum value storage circuit 5. The maximum value storage circuit 5 sets the initial value to 0 and updates the already stored value to a value given from the comparison circuit 4.

6, when the maximum value extraction circuit 3 extracts the maximum value of the received power of the SP signal for each predetermined number of symbols, a threshold value (for example, maximum value> threshold value 1> threshold value 2 is determined based on the maximum value). > Threshold value determining circuit for determining threshold value 1, threshold value 2 and threshold value 3) to be threshold value 3, and 7 is a weighting for the data signal output from the demapping circuit using the threshold value determined by the threshold value determining circuit 6. It is a weighting circuit that performs processing.
JP 2003-258762 A

  6 and 7 are graphs showing the reception power calculation results of the SP signals for four symbols in the reception power calculation circuit 2 in an analog manner, with the reception power in the vertical axis direction and the carrier number in the horizontal axis direction. FIG. 6 shows an example in which the SP signal is not affected by analog interference or noise. In such a case, there is no problem in extracting the maximum value of received power in the maximum value extraction circuit 3. .

  On the other hand, FIG. 7 shows an example in which the SP signal is affected by analog interference or noise, and peaks P1 and P2 are affected by analog interference or noise. In such a case, the maximum value extraction circuit 3 will extract the value of the peak P1 as the maximum value, and an appropriate threshold value cannot be determined, and the data signal output from the demapping circuit will not be determined. However, there arises a problem that good weighting cannot be performed.

  In view of the above, the present invention determines an appropriate threshold value and performs good weighting on a data signal even when the transmission path estimation signal is affected by analog interference or noise. An object of the present invention is to provide an OFDM demodulator capable of performing the above.

  An OFDM demodulator according to the present invention includes a received power calculation means for calculating received power of a transmission path estimation signal, a maximum value extraction means for extracting a maximum value from an output value of the received power calculation means, and an output of the received power calculation means It has an upper limit value generating means for generating an upper limit value of maximum value extraction in the maximum value extracting means from the value, and the maximum value extracting means extracts the maximum value within a range equal to or lower than the upper limit value.

  According to the present invention, the maximum value extraction means extracts the maximum value in the range below the upper limit value generated by the upper limit value generation means, so except for the received power of the SP signal affected by analog interference, noise, etc. The maximum value can be extracted. Therefore, even when the transmission path estimation signal is affected by analog interference, noise, or the like, an appropriate threshold value can be determined and good weighting processing can be performed on the data signal.

  The first and second embodiments of the present invention will be described below with reference to FIGS. 1 to 3 by taking as an example the case where the present invention is applied to an OFDM demodulator used in a terrestrial digital broadcast receiver. To do.

(First embodiment. FIG. 1 and FIG. 2)
FIG. 1 is a circuit diagram showing the main part of the first embodiment of the present invention. In FIG. 1, 8 is a RAM for storing an SP signal which is a transmission path estimation signal, and 9 is a received power calculation for calculating the received power of the SP signal for each predetermined number of symbols (for example, 1 symbol, 4 symbols or 12 symbols). Circuits 10 and 10 are upper limit value generation circuits for generating an upper limit value for maximum value extraction used in a maximum value extraction circuit described later from the output value of the received power calculation circuit 9.

  In the upper limit value generation circuit 10, 11 is an average value calculation circuit that calculates an average value in units of a predetermined number of symbols of the output value of the received power calculation circuit 9, and 12 is a minimum value from the output value of the reception power calculation circuit 9 for each predetermined number of symbols. It is a minimum value extraction circuit for extracting values.

  In the minimum value extraction circuit 12, 13 is a comparison circuit, and 14 is a minimum value storage circuit. The comparison circuit 13 compares the output value of the reception power calculation circuit 9 with the minimum value stored in the minimum value storage circuit 14. If the output value of the reception power calculation circuit 9 is smaller, the comparison circuit 13 The output value is given to the minimum value storage circuit 14. The minimum value storage circuit 14 sets the initial value as the maximum storable value, and updates the already stored value to a value given from the comparison circuit 13.

  Reference numeral 15 denotes an upper limit calculation circuit for calculating an upper limit value for each predetermined number of symbols from the average value output by the average value calculation circuit 11 and the minimum value stored by the minimum value storage circuit 14, and 16 indicates the output from the average value calculation circuit 11. A subtracter for subtracting the minimum value stored in the minimum value storage circuit 14 from the average value to be performed, 17 is a value output from the subtractor 16, that is, an average output by the average value calculation circuit 11 to (average value−minimum value). An adder that adds values. That is, in the upper limit calculation circuit 15, the upper limit is calculated by an arithmetic expression [(average value−minimum value) + average value].

  Reference numeral 18 denotes a delay circuit that delays the output value of the received power arithmetic circuit 9 by one symbol, 19 denotes a maximum value extraction circuit that extracts a maximum value for each symbol from the output value of the delay circuit 18, 20 denotes a comparison circuit, 21 Is a maximum value storage circuit.

  The comparison circuit 20 compares the output value of the delay circuit 18 with the maximum value stored in the maximum value storage circuit 21. If the output value of the delay circuit 18 is larger, the output value of the delay circuit 18 is stored in the maximum value. This is given to the circuit 21. The maximum value storage circuit 21 sets the initial value to 0 and updates the already stored value to a value given from the comparison circuit 20.

  22 is a threshold value determination circuit that determines a threshold value based on the maximum value when the maximum value extraction circuit 19 extracts the maximum value of the received power of the SP signal for each predetermined number of symbols, and 23 is determined by the threshold value determination circuit 22. This is a weighting circuit that performs weighting processing on the data signal output from the demapping circuit using a threshold value.

  In the first embodiment of the present invention, the received power calculation circuit 9 calculates the received power of the SP signal for each predetermined number of symbols from the SP signal stored in the RAM 8, and the upper limit generation circuit 10 calculates the received power for each predetermined number of symbols. An upper limit is generated. In the maximum value extraction circuit 19, the output value of the reception power calculation circuit 9 is input via the delay circuit 18, and the maximum value of the reception power of the SP signal is within a range below the upper limit value given from the upper limit value generation circuit 10. Extracted.

  FIG. 2 is a diagram showing the reception power calculation result of the SP signal for four symbols in the reception power calculation circuit 9 in an analog manner, which is the same as that shown in FIG. According to the first embodiment of the present invention, even if there are peaks P1 and P2 of the SP signal affected by analog interference or noise, the maximum value is affected by analog interference or noise. It is possible to obtain a maximum value or a value close to the maximum value of the received power of a non-SP signal.

  As described above, according to the first embodiment of the present invention, the maximum value extraction circuit 19 is equal to or less than the upper limit value generated by the upper limit value generation circuit 10 using the arithmetic expression [(average value−minimum value) + average value]. Since the maximum value is extracted in the range, the maximum value can be extracted excluding the reception power of the SP signal affected by analog interference or noise. Therefore, even when the SP signal is affected by analog interference or noise, an appropriate threshold value can be determined and a good weighting process can be performed on the data signal output from the demapping circuit. .

(Second embodiment: FIGS. 3 and 4)
FIG. 3 is a circuit diagram showing the main part of the second embodiment of the present invention. The second embodiment of the present invention is provided with an upper limit value generation circuit 24 having a circuit configuration different from that of the upper limit value generation circuit 10 provided in the first embodiment of the present invention, and the others are the same as in the first embodiment of the present invention. It is composed.

  The upper limit value generation circuit 24 includes an upper limit value calculation circuit 25 having a circuit configuration different from that of the upper limit value calculation circuit 15 included in the upper limit value generation circuit 10 shown in FIG. It is constituted similarly.

  In the upper limit calculation circuit 25, 26 is a subtracter that subtracts the minimum value stored in the minimum value storage circuit 14 from the average value output from the average value calculation circuit 11, and 27 is output from the subtractor 26 (average value−minimum value). ) Is multiplied by an arbitrary value α within a predetermined range, 28 is a multiplier that multiplies the average value output from the average value calculation circuit 11 by an arbitrary value β within the predetermined range, and 29 is an output value of the multiplier 27. This is an adder that adds the output value of the multiplier 28. That is, in the upper limit calculation circuit 25, the upper limit is calculated by an arithmetic expression [(average value−minimum value) × α + average value × β].

  FIG. 4 is a diagram for explaining an example of using α and β. (A) and (B) both show an example of the calculation result of the received power of the SP signal in the received power calculation circuit 9, and noise and multi The case where an ideal OFDM signal without a factor such as a path is received is taken as an example. Here, if the calculation result of the received power of the SP signal in the received power calculation circuit 9 is flat as shown in (A), there is no problem in calculating the average value or the minimum value.

  However, when the power at both ends is reduced as shown in (B) by the filter in the tuner or the OFDM demodulator, the average value and the minimum value are calculated in the same manner as in the first embodiment of the present invention. Then, the average value and the minimum value are calculated low. In order to adjust this, α and β are used in the second embodiment of the present invention. It should be noted that a value between 0 and 2 is considered sufficient for both α and β. Further, the upper limit value generation circuit may be configured to perform an operation of [(average value−minimum value) + average value + γ (any value within a predetermined range)].

  In the second embodiment of the present invention, the received power calculation circuit 9 calculates the received power of the SP signal for each predetermined number of symbols from the SP signal stored in the RAM 8, and the upper limit value generation circuit 24 for each predetermined number of symbols. An upper limit is generated. In the maximum value extraction circuit 19, the output value of the reception power calculation circuit 9 is input via the delay circuit 18, and the maximum value of the reception power of the SP signal is within a range below the upper limit value given from the upper limit value generation circuit 24. Extracted.

  According to the second embodiment of the present invention, an appropriate upper limit value can be generated by selecting appropriate values as α and β, and the maximum value extraction circuit 19 can generate an upper limit value generated by the upper limit value generation circuit 24. Since the maximum value is extracted in the following range, the maximum value can be extracted except for the received power of the SP signal affected by analog interference or noise. As a result, even when the SP signal is affected by analog interference or noise, an appropriate threshold value can be determined and a good weighting process can be performed on the data signal output from the demapping circuit. it can.

  Although the multipliers 27 and 28 are provided in the second embodiment of the present invention, any one of them may be provided. In the first and second embodiments of the present invention, the case where the weighting process is performed on the data signal output from the demapping circuit has been described as an example. However, the weighting process may be a data signal before Viterbi decoding. For example, it may not be a data signal output from the dematching circuit.

  Further, in the first and second embodiments of the present invention, the case where the present invention is applied to an OFDM demodulator for a terrestrial digital broadcast receiver has been described as an example. The present invention can be widely applied to an OFDM demodulator for an OFDM wireless communication system such as an OFDM demodulator.

It is a circuit diagram which shows the principal part of 1st Embodiment of this invention. It is a figure which shows the reception power calculation result of SP signal for 4 symbols in analog in the reception power calculation circuit with which 1st Embodiment of this invention is provided. It is a circuit diagram which shows the principal part of 2nd Embodiment of this invention. It is a figure for demonstrating the utilization example of arbitrary values (alpha) and (beta) used in 2nd Embodiment of this invention. It is a circuit diagram which shows the principal part of an example of the conventional OFDM demodulation apparatus. It is a figure which shows the reception power calculation result of the SP signal for 4 symbols in an analog manner in the reception power calculation circuit with which the conventional OFDM demodulator shown in FIG. 5 is provided. It is a figure which shows the reception power calculation result of the SP signal for 4 symbols in an analog manner in the reception power calculation circuit with which the conventional OFDM demodulator shown in FIG. 5 is provided.

Explanation of symbols

1 ... RAM
2 ... Received power calculation circuit 3 ... Maximum value extraction circuit 4 ... Comparison circuit 5 ... Maximum value storage circuit 6 ... Threshold determination circuit 7 ... Weighting circuit 8 ... RAM
DESCRIPTION OF SYMBOLS 9 ... Received power calculation circuit 10 ... Upper limit value generation circuit 11 ... Average value calculation circuit 12 ... Minimum value extraction circuit 13 ... Comparison circuit 14 ... Minimum value storage circuit 15 ... Upper limit value calculation circuit 16 ... Subtractor 17 ... Adder 18 ... Delay circuit 19 ... Maximum value extraction circuit 20 ... Comparison circuit 21 ... Maximum value storage circuit 22 ... Threshold determination circuit 23 ... Weighting circuit 24 ... Upper limit generation circuit 25 ... Upper limit calculation circuit 26 ... Subtractors 27, 28 ... Multiplier 29 ... Adder

Claims (3)

Received power calculation means for calculating the received power of the transmission path estimation signal;
Maximum value extracting means for extracting the maximum value from the output value of the received power calculating means;
An upper limit value generating means for generating an upper limit value of maximum value extraction in the maximum value extracting means from an output value of the received power calculating means;
The OFDM demodulator characterized in that the maximum value extraction means extracts a maximum value within a range equal to or less than the upper limit value. The upper limit generation means includes
Average value calculating means for calculating an average value from an output value of the received power calculating means;
Minimum value extracting means for extracting a minimum value from the output value of the received power calculating means;
It has an upper limit value calculating means for calculating the upper limit value by an arithmetic expression [(the average value−the minimum value) × α + the average value × β] (where α and β are arbitrary values within a predetermined range). The OFDM demodulator according to claim 1. The upper limit calculating means includes
When α is 1, multiplication of α with respect to (the average value−the minimum value) is not performed.
The OFDM demodulator according to claim 2, wherein when β is 1, the average value is not multiplied by β.

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