JP2005236105A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device in which the occurrence of pn junction leakage is suppressed, and a method for manufacturing the semiconductor device. <P>SOLUTION: After forming an oxide film 15 (silicide protection) and a sidewall 16 in the manufacturing process of the semiconductor device comprising a CMOS element and a resistor element, a p<SP>+</SP>source/drain area 14 is formed by injecting impurities into both sides of a gate electrode 7A in an n well 4. More preferably, impurity injection into an n<SP>+</SP>source/drain area 13 is also performed after forming the oxide film 15 and the sidewall 16. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a metal silicide film on a source / drain region of a MOS (Metal Oxide Semiconductor) transistor and a manufacturing method thereof.

  A semiconductor integrated circuit may include not only a transistor but also a passive element such as a resistance element.

  In this case, it is necessary to form the transistor and the passive element on the same substrate without increasing the number of processes as much as possible.

  As the above transistor, for example, a CMOS (Complementary MOS) device having a PMOS (P-Channel MOS) and an NMOS (N-Channel MOS) is often used.

  In a CMOS device, a gate electrode is provided on a P-type / N-type well provided on a substrate via a gate oxide film, and a source / drain is formed using the gate electrode and side walls provided on both sides thereof as a mask. An N-type impurity region and a P-type impurity region to be regions are implanted.

  As the resistance element, an oxide film (silicide protection) for preventing silicidation is provided on a part of a conductive layer such as polysilicon provided on a field oxide film, and the oxide film on the conductive layer is provided. A region other than the portion where the film is formed is formed by silicidation.

Japanese Laid-Open Patent Publication No. 10-275871 discloses a method for manufacturing a semiconductor device in which a MOS transistor, a bipolar transistor, a resistance element, and a capacitance element are mixedly mounted on the same substrate.
JP 10-275871 A JP 2003-17580 A

  However, the semiconductor device and the manufacturing method thereof as described above have the following problems.

  In some cases, an impurity region which becomes a source / drain region of a MOS transistor is silicided.

  In the etching for forming the oxide film used for the resistance element described above, the field oxide film is reduced. As a result, a PN junction leak may occur when the silicide film penetrates the boundary (PN junction surface) between the impurity region and the well. From the viewpoint of improving the reliability of the operation of the semiconductor integrated circuit, it is preferable to suppress this PN junction leakage as much as possible.

  By the way, in Japanese Patent Application Laid-Open No. 2003-17580, an N-type / P-type high concentration is formed after a silicidation preventing insulating film (resistance element insulating film) is formed on a part of a polysilicon layer provided on an element isolation oxide film. A method of manufacturing a semiconductor device is disclosed in which a diffusion layer is formed and then a silicide layer is formed.

  However, in Japanese Patent Application Laid-Open No. 2003-17580, in one aspect, the sidewall of the gate electrode and the resistive element insulating film are formed of the same oxide film, and therefore the thickness of the sidewall of the gate electrode is the resistance element. Restrained by the thickness of the insulating film. Further, from the viewpoint different from the above, since the sidewalls of the PMOS and NMOS are formed in the same process, the sidewall formation process and the source / drain region implantation process are performed by using different mask films. It is necessary to use it.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device in which the occurrence of PN junction leakage is suppressed and a method for manufacturing the same.

  A method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device having a complementary metal oxide semiconductor (CMOS) element portion and a resistance element portion, and includes a first active region of a first conductivity type on a substrate, Forming a second active region of a second conductivity type and an element isolation insulating film; and isolating and isolating the first and second gate electrodes on the first and second active regions via a gate insulating film, respectively. Forming a conductive film on the film; forming a first sidewall insulating film on the sidewalls of the first and second gate electrodes; and a first on both sides of the second gate electrode in the second active region. Forming a conductive type first source / drain region; forming an insulating layer on the first and second active regions from above the conductive film; etching the insulating layer; After forming the insulating film and forming the second sidewall insulating film on the first sidewall insulating film, and forming the insulating film and the second sidewall insulating film, the first active region in the first active region is formed. Forming a second source / drain region of the second conductivity type on both sides of the gate electrode, silicide on the first and second gate electrodes, on the first and second source / drain regions, and on the conductive film; Forming a film.

  A semiconductor device according to the present invention includes a substrate having a main surface, an element isolation insulating film selectively formed on the main surface of the substrate, an active region of a first conductivity type surrounded by the element isolation insulating film, A gate electrode formed on the active region via a gate insulating film; first and second dummy gates formed on the active region on both sides of the gate electrode via an insulating film; and a first dummy A source / drain region of the second conductivity type formed between the gate and the gate electrode and between the second dummy gate and the gate electrode, and between the first dummy gate and the element isolation insulating film, respectively. The first impurity region, the second impurity region formed between the second dummy gate and the element isolation insulating film, the surface of the source / drain region and the surface of the first and second impurity regions. With silicide film .

  According to the present invention, it is possible to suppress the occurrence of PN junction leakage in a semiconductor device having a metal silicide film on the source / drain regions of a MOS transistor.

  Embodiments of a semiconductor device and a manufacturing method thereof according to the present invention will be described below with reference to FIGS.

(Embodiment 1)
FIG. 9 is a cross-sectional view showing a CMOS element portion in the semiconductor device according to the first embodiment of the present invention.

  In the semiconductor device according to the present embodiment, as shown in FIG. 9, an N + type buried layer 2 and a P + type buried layer 3 are formed on a P type silicon substrate 1. An N-type well 4 (first active region) is formed on the buried layer 2, and a P-type well 5 (second active region) is formed on the buried layer 3. A field oxide film 6 (element isolation insulating film) is provided between the N-type well 4 and the P-type well 5 for element isolation.

A gate electrode 7A (first gate electrode) is provided on the N-type well 4 via a gate oxide film 7C. Gate electrode 7A is formed of, for example, an N + type polysilicon layer. P + -type source / drain regions 14 (second source / drain regions) are formed on both sides of the gate electrode 7A. A silicide film 19 including, for example, CoSi ₂ is formed on gate electrode 7A and P + type source / drain region 14. The PMOS section is configured as described above.

  A gate electrode 7B (second gate electrode) is provided on the P-type well 5 in the same manner as on the N-type well 4. N + type source / drain regions 13 (first source / drain regions) are formed on both sides of the gate electrode 7B. Silicide film 19 is formed on gate electrode 7B and N + type source / drain region 13. The NMOS unit is configured as described above.

  A polysilicon film 8 (conductive film) is formed on field oxide film 6. An oxide film 15 (insulating film) is provided on a part of the polysilicon film 8, and a silicide film 19 is formed in a region on the polysilicon film 8 where the oxide film 15 is not formed. The resistance element is configured as described above.

  A sidewall 12 (first sidewall insulating film) is formed on the wall surfaces of the gate electrodes 7A and 7B and the polysilicon film 8, and a sidewall insulating film 16 (second sidewall insulating film) is formed on the sidewall insulating film 12. ) Is formed.

  A method for manufacturing the semiconductor device having the above-described configuration will be described below.

  1 to 6 and 8 are cross-sectional views showing respective steps in the manufacturing process of the CMOS element portion shown in FIG.

  As shown in FIG. 1, a field oxide film 6, a buried layer 2 (N + type), and a buried layer 3 (P + type) are provided on a P-type silicon substrate 1. Then, an N-type well 4 is formed on the buried layer 2 and a P-type well 5 is formed on the buried layer 3. Further, gate electrodes 7A and 7B are provided on the N-type well 4 and the P-type well 5 through gate oxide films 7C, respectively, and a polysilicon film 8 is formed on the field oxide film 6. The polysilicon film 8 can be formed simultaneously with the patterning of the gate electrodes 7A and 7B.

From the state of FIG. 1, a resist film is formed so as to cover N-type well 4, P-type well 5 and field oxide film 6. As shown in FIG. 2, the resist film is patterned so as to have an opening in a region where the NMOS transistor is provided, thereby forming a resist mask 9A. A relatively low concentration N-type impurity is implanted into this opening (for example, phosphorus implantation, 70 KeV, 1.8 × 10 ¹³ cm ⁻² , 45 ° rotation implantation, etc.), and N-source / drain region 10 is formed. The

From the state of FIG. 2, the resist mask 9A is removed, and a resist film is formed again. As shown in FIG. 3, the resist film is patterned so as to have an opening in a region where the PMOS transistor is provided, thereby forming a resist mask 9B. A relatively low concentration P-type impurity is implanted into this opening (for example, boron implantation, 10 KeV, 1.0 × 10 ¹³ cm ⁻² , 7-degree rotational implantation, etc.), and a P-source / drain region 11 is formed. The

  3, the resist mask 9B is removed, and an oxide film (CVD oxide film) is formed so as to cover the N-type well 4, the P-type well 5, and the field oxide film 6 by a CVD (Chemical Vapor Deposition) method or the like. Is done. Then, by performing dry etching on the oxide film, sidewalls 12 (sidewall oxide films) are formed on the gate electrodes 7A and 7B and the polysilicon film 8, as shown in FIG. Here, the dry etching is performed so that the CVD oxide film on the field oxide film 6 is sufficiently removed (for example, 125% or more with respect to the film thickness of the CVD oxide film). Therefore, the field oxide film 6 is reduced by this dry etching process, and the upper surface of the edge portion of the field oxide film 6 is lowered below the upper surfaces of the N-source / drain region 10 and the P-source / drain region 11. It becomes a state.

From the state of FIG. 4, a resist film is formed again. As shown in FIG. 5, the resist film is patterned so as to have an opening in a region where the NMOS transistor is provided, thereby forming a resist mask 9A. An N-type impurity having a concentration higher than that described above is implanted into the opening (for example, phosphorus implantation, 100 KeV, 2.0 × 10 ¹⁴ cm ⁻² , 60 ° rotation implantation, arsenic implantation, 50 KeV, 4.0 × 10 ¹⁵ etc. cm ^-2), N + source / drain regions 13 are formed.

  From the state of FIG. 5, the resist mask 9A is removed, and an oxide film (CVD oxide film) is formed so as to cover the N-type well 4, the P-type well 5 and the field oxide film 6 by CVD or the like. Then, by performing dry etching on the oxide film while protecting the region where the oxide film for the resistive element is formed with a resist film, as shown in FIG. An oxide film 15 is formed on part of the silicon film 8. A silicide film to be described later is not formed in the portion where the oxide film 15 is formed. That is, the oxide film 15 functions as silicide protection. Thereby, a region having a resistance value different from that of the region where the silicide film is formed is formed, and a resistance element is formed. Here, the dry etching is performed so that the CVD oxide film on the field oxide film 6 is sufficiently removed (for example, 125% or more with respect to the film thickness of the CVD oxide film). Accordingly, the field oxide film 6 is further reduced by this dry etching process.

  Incidentally, on the silicon substrate 1, in addition to the N-type well 4 and the P-type well 5 described above, an N-type well 4A and a P-type well 5A shown in FIG. 7 are provided. A P-type diffusion region 18 is provided on the N-type well 4A, and an N-type diffusion region 17 is provided on the P-type well 5A. An oxide film 15 </ b> A is formed on a part on the N-type diffusion region 17 and a part on the P-type diffusion region 18. A silicide film to be described later is not formed in the portion where the oxide film 15A is formed. Thereby, a region having a resistance value different from that of the region where the silicide film is formed is provided, and a resistance element is formed. The oxide film 15A can be formed in the same process as the oxide film 15.

  Thus, as the resistance element, a configuration formed on the polysilicon film 8 may be used, or a configuration formed on the N-type diffusion region 17 and the P-type diffusion region 18 may be used.

From the state of FIG. 6, a resist film is formed again. As shown in FIG. 8, the resist film is patterned so as to have an opening in a region where the PMOS transistor is provided, and a resist mask 9B is formed. A P-type impurity having a higher concentration than the above is implanted into the opening (for example, BF ₂ implantation, 40 KeV, 4.0 × 10 ¹⁵ cm ^−2, etc.), and a P + source / drain region 14 is formed.

  From the state of FIG. 8, silicide film 19 is formed on gate electrode 7, polysilicon film 8, N + source / drain region 13 and P + source / drain region 14. Thereby, the structure shown in FIG. 9 is obtained.

  From the state of FIG. 9, as shown in FIG. 10, an interlayer insulating film 23 is deposited so as to cover the resistance element, the PMOS transistor and the NMOS transistor. A contact hole 20 reaching the silicide film 19 is provided in the interlayer insulating film 23. In the contact hole 20, a barrier metal 21A is formed on the inner peripheral surface thereof, and a metal wiring 21 (for example, in a region surrounded by the barrier metal 21A). Including tungsten). Metal interconnection 21 is connected to metal interconnection 22 (including, for example, aluminum) on interlayer insulating film 23.

  From the state of FIG. 7, an interlayer insulating film 23 is deposited so as to cover the N type diffusion region 17 and the P type diffusion region 18 as shown in FIG. In the interlayer insulating film 23 and on the interlayer insulating film 23, a contact hole 20, a barrier metal 21A, and metal wirings 21 and 22 are provided in the same manner as described above.

  In general, impurities constituting the source / drain regions of a MOS transistor are implanted in consideration of the short channel characteristics of the transistor. Therefore, the depth of the PN junction surface between the source / drain region and the well region cannot be increased indefinitely when viewed from the upper surface of the field oxide film 6.

  If the field oxide film 6 is excessively reduced after the impurity constituting the source / drain region is implanted, the depth of the PN junction surface between the source / drain region and the well region (the field oxide film 6 (Depth viewed from the upper surface of the edge portion) is reduced.

  In the present embodiment, after the oxide film 15 constituting the resistance element is formed by dry etching, impurities are implanted to form the P + source / drain region 14. Therefore, in the a part in FIG. 9, the depth of the PN junction surface is not reduced by the reduction of the field oxide film 6, and the silicide film 19 is formed between the P + source / drain region 14 and the N-type well 4. It is possible to suppress the penetration into the N-type well 4 through the joint surface. As a result, the occurrence of PN junction leakage can be suppressed, and the operation reliability of the semiconductor integrated circuit is improved.

  Here, PN junction leakage means that a conductive film (silicide film) is inserted between PN junctions (here, the junction between the P + source / drain region 14 and the N-type well 4), and the characteristics of the PN junction are impaired. That means.

  In the present embodiment, the N + source / drain region 13 is implanted before the oxide film 15 constituting the resistance element is formed by etching. However, by implanting the N + source / drain region 13 sufficiently deep without impairing the short channel characteristics of the transistor, the silicide film 19 penetrates the junction surface between the N + source / drain region 13 and the P-type well 5. As a result, it is possible to suppress reaching the P-type well 5. As a result, it is possible to suppress the occurrence of PN junction leakage in the NMOS portion.

  Furthermore, in the present embodiment, the sidewalls of the gate electrodes 7A and 7B in the PMOS transistor and the NMOS transistor are the sidewall 16 made of the same oxide film as the oxide film constituting the oxide film 15 constituting the resistance element, and the oxide film. 15 has a laminated structure including a sidewall 12 made of another oxide film. Therefore, the thickness of the sidewall of the gate electrode 7 (total thickness of the sidewalls 12 and 16) can be determined regardless of the thickness of the oxide film 15 for the resistance element.

  The method for manufacturing the semiconductor device according to the present embodiment is summarized as follows.

  The method for manufacturing a semiconductor device according to the present embodiment is a method for manufacturing a semiconductor device having a CMOS element portion and a resistance element portion, and N in which N-type (first conductivity type) impurities are implanted on a substrate 1. A type well 4 (first active region), a P type well 5 (second active region) implanted with a P type (second conductivity type) impurity, and a field oxide film 6 (element isolation insulating film) are formed. On the N-type well 4 and the P-type well 5 on the gate electrodes 7A and 7B (first and second gate electrodes) and the field oxide film 6 via the gate oxide film 7C (gate insulating film), respectively. A step of forming the polysilicon film 8 (conductive film) (FIG. 1), and a step of forming the sidewall 12 (first sidewall insulating film) on the side walls of the gate electrodes 7A and 7B (FIG. 4). The gate electrode 7B in the P-type well 5 A step of forming N + source / drain regions 13 (first source / drain regions) on both sides (FIG. 5), and a CVD oxide film (insulating layer) on the polysilicon film 8 and on the N-type well 4 and P-type well 5 ) And the oxide film is etched to form an oxide film 15 (insulating film) as silicide protection on a part of the polysilicon film 8 and a sidewall 16 (second side) on the sidewall 12. After forming the oxide film 15 and the side wall 16, the P + source / drain regions 14 (second source / drain regions) are formed on both sides of the gate electrode 7A in the N-type well 4 (FIG. 6). A drain region) (FIG. 8), silicide on the gate electrodes 7A and 7B, the source / drain regions 13 and 14 and the polysilicon film 8. And a step (FIG. 9) to form a 19.

  In the semiconductor device described above, even if the NMOS portion (P-type well 5 and N + source / drain region 13) is omitted, the same effect (an effect of suppressing PN junction leakage) is obtained in the PMOS portion.

  In this case, the semiconductor device manufacturing method forms an N-type well 4 (active region) and a field oxide film 6 (element isolation insulating film) into which an N-type (first conductivity type) impurity is implanted on a substrate 1. A step of forming a gate electrode 7A on the N-type well 4 via a gate oxide film 7C (gate insulating film) and a polysilicon film 8 (conductive film) on the field oxide film 6 (see FIG. 1). ), A step of forming a sidewall 12 (first sidewall insulating film) on the side wall of the gate electrode 7A (FIG. 4), and a CVD oxide film (insulating layer) from the polysilicon film 8 to the N-type well 4 The oxide film is etched to form an oxide film 15 (insulating film) as silicide protection on a part of the polysilicon film 8, and a sidewall 16 (second sidewall) is formed on the sidewall 12. A step of forming an insulating film) (FIG. 6), and a step of forming P + source / drain regions 14 on both sides of the gate electrode 7A in the N-type well 4 after forming the oxide film 15 and the sidewalls 16 (FIG. 6). 8), a step of forming a silicide film 19 on the gate electrode 7A, the source / drain region 14, and the polysilicon film 8 (FIG. 9).

(Embodiment 2)
FIG. 14 is a cross-sectional view showing a CMOS element portion in the semiconductor device according to the second embodiment of the present invention.

  The semiconductor device according to the present embodiment is a modification of the semiconductor device according to the first embodiment. As shown in FIG. 14, the sidewall of the gate electrode 7 has a single-layer structure (only the sidewall 12). This is different from the first embodiment in the point that is performed.

  12 and 13 are cross-sectional views showing respective steps in the manufacturing process of the CMOS element portion shown in FIG.

  Note that the steps shown in FIGS. 1 to 3 described above are performed in the present embodiment in the same manner as in the first embodiment.

  From the state of FIG. 3, the resist mask 9B is removed, and as shown in FIG. 12, an oxide film 16C (insulating layer) and a resist film are formed on the oxide film 16C. The oxide film 16C and the resist film are patterned so as to have an opening in a region where the NMOS transistor is provided, thereby forming a resist mask 9A (first mask film).

  Next, by performing dry etching on the oxide film 12A, sidewalls 16A (sidewall insulating films) are formed on both sides of the gate electrode 7 of the NMOS transistor.

  Then, an N-type impurity having a concentration higher than that of the N− source / drain region 10 is implanted into the opening to form an N + source / drain region 13 (first source / drain region).

  From the state of FIG. 12, the resist mask 9A is removed, and a resist film is formed again. As shown in FIG. 13, the resist film is patterned so as to have an opening in a region where the PMOS transistor and the resistance element are provided, and a resist mask 9C (second mask film) is formed. In the region where the resistance element is provided, the resist film is left in the portion where the oxide film 15 is formed on the polysilicon film 8.

  Next, by performing dry etching on the oxide film 16C, a resistance is applied to the side wall 16B (another side wall insulating film) on both sides of the gate electrode 7A of the PMOS transistor and a part on the polysilicon film 8 (conductive film). An oxide film 15 (insulating film) for the element is formed.

  Then, a P-type impurity having a concentration higher than that of the P− source / drain region 11 is implanted into the opening in the PMOS transistor forming portion, thereby forming a P + source / drain region 14 (second source / drain region).

  In the steps shown in FIGS. 12 and 13, dry etching for oxide film 16C is performed so that the CVD oxide film on field oxide film 6 is sufficiently removed. Therefore, the field oxide film 6 is reduced by this dry etching process.

  From the state of FIG. 13, silicide film 19 is formed on gate electrodes 7A and 7B, polysilicon film 8, N + source / drain region 13 and P + source / drain region 14. Thereby, the structure shown in FIG. 14 is obtained.

  Thereafter, an interlayer insulating film covering the transistor and the resistance element and a metal wiring reaching the silicide film from the interlayer insulating film are provided in the same manner as in the first embodiment.

  Also in the present embodiment, after the oxide film 15 constituting the resistance element is formed by dry etching, impurities are implanted to form the P + source / drain region 14. Therefore, the depth of the junction surface between the P + source / drain region 14 and the N-type well 4 is not reduced by the reduction of the field oxide film 6. Accordingly, it is possible to prevent the silicide film 19 from penetrating through the junction surface between the P + source / drain region 14 and the N-type well 4 and reaching the N-type well 4 in the portion b1 in FIG. As a result, the occurrence of PN junction leakage can be suppressed, and the operation reliability of the semiconductor integrated circuit is improved.

  On the other hand, in this embodiment, the N + source / drain region 13 is implanted before dry etching for forming the resistance element oxide film 15. However, when dry etching for forming oxide film 15 is performed, an edge portion (b2 portion in FIG. 14) on the N + source / drain region 13 side of field oxide film 6 is covered with resist mask 9C. Therefore, the field oxide film 6 is not further reduced in the portion b2 after the impurity implantation of the N + source / drain region 13 is implanted. Therefore, the silicide film 19 can be prevented from penetrating through the junction surface between the N + source / drain region 13 and the P-type well 5 and reaching the P-type well 5. As a result, the occurrence of PN junction leakage can be suppressed.

  Further, in the present embodiment, the sidewall 16A and the N + source / drain region 13 are formed using the same resist mask 9A, and the sidewall 16B, the P + source / drain region 14 and the oxide film 15 (for the resistance element) are formed. ) Is formed using the same resist mask 9C, the number of steps required for forming the transistor and the resistance element can be reduced.

  The method for manufacturing the semiconductor device according to the present embodiment is summarized as follows.

  The method for manufacturing a semiconductor device according to the present embodiment is a method for manufacturing a semiconductor device having a CMOS element portion and a resistance element portion, and an N-type well 4 (N-type (first conductivity type) impurity implanted therein. Forming a first active region), a P-type well 5 (second active region) implanted with P-type (second conductivity type) impurities, and a field oxide film 6 (element isolation insulating film); Gate electrode 7A, 7B (first and second gate electrodes) via gate oxide film 7C (gate insulating film) on type well 4 and P type well 5, respectively, and polysilicon film 8 on field oxide film 6 (Conductive film) forming step (above, FIG. 1), forming an oxide film 16C (insulating layer) on the N-type well 4 and the P-type well 5 from the polysilicon film 8, and P-type Resist mask 9A having an opening on well 5 (first A mask film), a step of etching the oxide film 16C using the resist mask 9A as a mask to form a sidewall 16A (sidewall insulating film) on the sidewall of the gate electrode 7B, a resist mask 9A and the sidewall Step of forming N + source / drain regions 13 (first source / drain regions) by introducing N-type impurities into both sides of the gate electrode 7B in the P-type well 5 using 16A as a mask (refer to FIG. 12). A step of forming a resist mask 9C (second mask film) having an opening on a part of the N-type well 4 and the polysilicon film 8, and etching the oxide film 16C using the resist mask 9C as a mask to form a gate electrode A sidewall 16B (another sidewall insulating film) is formed on the side wall of 7A and A step of forming an oxide film 15 (insulating film) as silicide protection on a part of the con film 8 and a P-type on both sides of the gate electrode 7A in the N-type well 4 using the resist mask 9B and the sidewall 16B as a mask. The step of forming the P + source / drain region 14 (second source / drain region) by introducing the impurity (see FIG. 13), the gate electrodes 7A and 7B, the source / drain regions 13 and 14, And a step of forming a silicide film 19 on the polysilicon film 8 (FIG. 14).

  In the present embodiment, detailed description of the same matters as in the first embodiment will not be repeated.

(Embodiment 3)
FIG. 18 is a cross-sectional view showing a CMOS element portion in the semiconductor device according to the third embodiment of the present invention.

  The semiconductor device according to the present embodiment is a modification of the semiconductor device according to the first embodiment. In the manufacturing process, the oxide film 15 for the resistance element is formed and then the N + type source / drain region 13 is formed. This is different from the first embodiment in that impurities are implanted.

  15 to 17 are cross-sectional views showing respective steps in the manufacturing process of the CMOS element portion shown in FIG.

  The above-described steps shown in FIGS. 1 to 4 are performed in the present embodiment in the same manner as in the first embodiment.

  From the state of FIG. 4, an oxide film (CVD oxide film) is formed so as to cover N-type well 4, P-type well 5 and field oxide film 6 by the CVD method or the like. Then, by performing dry etching on the CVD oxide film while protecting the region where the oxide film for the resistance element is formed with a resist, as shown in FIG. 15, the sidewall 12 (first sidewall insulating film) is formed. A sidewall 16 (second sidewall insulating film) is formed on the outside, and an oxide film 15 (insulating film) is formed on a portion of the polysilicon film 8 (conductive film). Here, the dry etching is performed so that the CVD oxide film on the polysilicon film 8 is sufficiently removed. Accordingly, the field oxide film 6 is further reduced by this dry etching process.

  From the state of FIG. 15, a resist film is formed again. As shown in FIG. 16, the resist film is patterned so as to have an opening in a region where the NMOS transistor is provided, and a resist mask 9A is formed. An N-type impurity having a concentration higher than that of the N− source / drain region 10 is implanted into the opening to form an N + source / drain region 13 (first source / drain region).

  From the state of FIG. 16, the resist mask 9A is removed, and a resist film is formed again. As shown in FIG. 17, the resist film is patterned so as to have an opening in a region where the PMOS transistor is provided, thereby forming a resist mask 9B. A P-type impurity having a concentration higher than that of the P− source / drain region 11 is implanted into the opening to form a P + source / drain region 14 (second source / drain region).

  From the state of FIG. 17, a silicide film 19 is formed on the gate electrodes 7A and 7B, the polysilicon film 8, the N + source / drain region 13 and the P + source / drain region 14. Thereby, the structure shown in FIG. 18 is obtained.

  Thereafter, an interlayer insulating film covering the transistor and the resistance element and a metal wiring reaching the silicide film from the interlayer insulating film are provided in the same manner as in the first embodiment.

  In the present embodiment, after oxide film 15 constituting the resistance element is formed by dry etching, impurities for forming N + source / drain region 13 and P + source / drain region 14 are implanted. Therefore, in the C1 portion and the C2 portion in FIG. 18, the silicide film 19 includes the source / drain regions (P + source / drain regions 14 and N + source / drain regions 13) and wells (N type well 4 and P type well 5). Can be prevented from penetrating through the joint surface and reaching the well. As a result, the occurrence of PN junction leakage can be suppressed, and the operation reliability of the semiconductor integrated circuit is improved.

  Furthermore, in the present embodiment, the sidewalls of the gate electrodes 7A and 7B in the PMOS transistor and the NMOS transistor are the sidewall 16 made of the same oxide film as the oxide film constituting the oxide film 15 constituting the resistance element, and the oxide film. 15 has a laminated structure including a sidewall 12 made of another oxide film. Therefore, the thickness of the sidewalls of the gate electrodes 7A and 7B (the total thickness of the sidewalls 12 and 16) can be determined regardless of the thickness of the oxide film 15 for the resistance element.

  The method for manufacturing the semiconductor device according to the present embodiment is summarized as follows.

  The method for manufacturing a semiconductor device according to the present embodiment is a method for manufacturing a semiconductor device having a CMOS element portion and a resistance element portion, and N in which N-type (first conductivity type) impurities are implanted on a substrate 1. A type well 4 (first active region), a P type well 5 (second active region) implanted with a P type (second conductivity type) impurity, and a field oxide film 6 (element isolation insulating film) are formed. On the N-type well 4 and the P-type well 5 on the gate electrodes 7A and 7B (first and second gate electrodes) and the field oxide film 6 via the gate oxide film 7C (gate insulating film), respectively. A step of forming the polysilicon film 8 (conductive film) (FIG. 1), and a step of forming the sidewall 12 (first sidewall insulating film) on the side walls of the gate electrodes 7A and 7B (FIG. 4). On the N-type well 4 from the polysilicon film 8 A CVD oxide film (insulating layer) is formed on the P-type well 5 and the oxide film is etched to form an oxide film 15 (insulating film) as silicide protection on a part of the polysilicon film 8. After forming the sidewall 16 (second sidewall insulating film) on the sidewall 12 (FIG. 15), and forming the oxide film 15 and the sidewall 16, the gate electrode 7B in the P-type well 5 is formed. A step of forming N + source / drain regions 13 (first source / drain regions) on both sides (FIG. 16), and further, P + source / drain regions 14 (first) on both sides of the gate electrode 7A in the N-type well 4 2 source / drain regions) (FIG. 17), gate electrodes 7A and 7B, source / drain regions 13 and 14, and polysilicon. And a step (FIG. 18) to form a silicide film 19 and the upper membrane 8.

  In the present embodiment, detailed description of the same matters as in the first embodiment will not be repeated.

(Embodiment 4)
FIG. 19 is a top view showing a semiconductor device according to the fourth embodiment of the present invention. 20 is a view showing a cross section XX-XX in FIG. 19, and FIG. 21 is a view showing a cross section XXI-XXI in FIG.

  On the other hand, FIG. 22 is a top view showing a conventional semiconductor device compared with the semiconductor device shown in FIG. FIG. 23 is a diagram showing a section XXIII-XXIII in FIG. 22, and FIG. 24 is a diagram showing a section XXIV-XXIV in FIG.

  In the present embodiment, the PMOS portion formed on the N-type well 4 will be described, but the same structure can be adopted for the NMOS portion formed on the P-type well 5. .

  Referring to FIGS. 19 to 24, gate electrode 7A and P + source / drain region 14 are provided in N type well 4 which is a region surrounded by field oxide film 6. This constitutes a PMOS transistor.

  A contact hole 20 reaching the silicide film 19 on the P + source / drain region 14 is provided in the interlayer insulating film 23 on the PMOS transistor, and the barrier metal 21A and the metal wiring 21 are filled in the contact hole 20. Thereby, in the contact portion 25, the P + source / drain region 14 and the upper metal wiring 22 are electrically connected.

  19 and 20 are compared with FIGS. 22 and 23, in the conventional semiconductor device (FIGS. 22 and 23), the P + source extends between the gate electrode 7A and the field oxide film 6. / Drain region 14 is provided, whereas in the semiconductor device according to the present embodiment (FIGS. 19 and 20), both sides of gate electrode 7A connected to the upper layer wiring contribute to the electrical characteristics of the semiconductor device. Dummy gates 70A and 70B are provided.

  Therefore, the P + source / drain regions 14 located on both sides of the gate electrode 7A do not reach the edge portion of the field oxide film 6, and the PN in the source / drain regions of the MOS transistor is the same as in the above embodiments. Junction leakage can be suppressed. Therefore, the reliability of the operation of the semiconductor device can be improved.

  In addition, since the gate electrode 7A and the field oxide film 6 are separated from each other, the gate electrode 7A is less susceptible to halation caused by a step in the edge portion of the field oxide film 6 when the gate electrode 7A is patterned. Therefore, the gate electrode 7A is formed in a stable shape.

  The oxide film 70C is formed in the same process as the gate oxide film 7C, and the dummy gates 70A and 70B are formed in the same process as the gate electrode 7A. Therefore, the manufacturing process of the semiconductor device is not complicated by adopting the above configuration.

  21 and 24, in the conventional semiconductor device (FIG. 24), the silicide film provided on the P + source / drain region 14 in the direction in which the P + source / drain region 14 extends. Whereas 19 reaches the edge portion of field oxide film 6, in the semiconductor device according to the present embodiment (FIG. 21), oxide film 26 is provided between silicide film 19 and field oxide film 6. .

  As a result, the silicide film 19 can be prevented from penetrating the junction surface between the P + source / drain region 14 and the N-type well 4 and reaching the N-type well 4. As a result, the occurrence of PN junction leakage can be suppressed, and the operation reliability of the semiconductor integrated circuit is improved.

  The oxide film 26 is formed by forming a P + source / drain region 14 and then forming an oxide film layer on the N-type well 4 by a CVD method or the like. A resist mask is formed on the region shown in FIG. And is formed by etching.

  The semiconductor device according to the present embodiment is summarized as follows.

  In one aspect (FIG. 20), the semiconductor device according to the present embodiment is surrounded by field oxide film 6 (element isolation insulating film) selectively formed on the main surface of the substrate and field oxide film 6. The N-type well 4 (active region), a gate electrode 7A formed on the N-type well 4 via a gate oxide film 7C (gate insulating film), and both sides of the gate electrode 7A on the N-type well 4 In addition, dummy gates 70A and 70B (first and second dummy gates) formed through an oxide film 70C (insulating film), between the dummy gate 70A and the gate electrode 7A, and between the dummy gate 70B and the gate electrode 7A, respectively. P + source / drain regions 14 respectively formed between the dummy gate 70A and the field oxide film 6, an impurity region 14A (first impurity region) formed between Impurity region 14B (second impurity region) formed between gate 70B and field oxide film 6, and a silicide film formed on the surface of P + source / drain region 14 and on the surfaces of impurity regions 14A and 14B. 19.

  In another aspect (FIG. 21), the semiconductor device according to the present embodiment includes a field oxide film 6 (element isolation insulating film) selectively formed on the main surface of the substrate and a field oxide film 6. An N-type well 4 (active region) surrounded, a P + source / drain region 14 formed in the N-type well 4 so as to reach the field oxide film 6 located on both sides of the N-type well 4, and a P + source / drain At both ends of the drain region 14, an oxide film 26 (insulating film) extending from the end of the field oxide film 6 to the end of the P + source / drain region 14 and a P + source located between the oxide films 26. / A silicide film 19 formed on the drain region 14 and a gate electrode 7A formed on the N-type well 4 via a gate oxide film 7C (gate insulating film).

  In addition, the above-described oxide film 26 can be provided in the semiconductor device according to the first to third embodiments.

  In the present embodiment, detailed description of the same matters as those of the above-described embodiments will not be repeated.

(Embodiment 5)
FIG. 38 is a sectional view showing a semiconductor device according to the fifth embodiment of the present invention.

  The semiconductor device according to the present embodiment is a modification of the semiconductor device according to the first embodiment, in which the semiconductor device according to the first embodiment is applied to a BiCMOS type semiconductor device.

  In the semiconductor device according to the present embodiment, as shown in FIG. 38, an NPN bipolar transistor is formed adjacent to the PMOS transistor and the NMOS transistor.

  The configuration of the NPN bipolar transistor will be described.

  Referring to FIG. 38, a buried layer 2 (N + type) is provided on a P type silicon substrate 1. An N type epitaxial layer 27 is formed on the buried layer 2. As the collector electrode 37, the same diffusion region as the N + source / drain region 13 is formed. The base electrode 36 is made of a P-type polysilicon film. Intrinsic base region 33 </ b> B is formed in N type epitaxial layer 27. The intrinsic base region 33B is formed by implantation. An emitter region 34 and an emitter electrode 35 are formed on the intrinsic base region 33B. The emitter region 34 is formed by diffusing impurities from the N-type polysilicon film. A silicide film 19 is formed on the emitter electrode 35, the base electrode 36 and the collector electrode 37.

  A method for manufacturing the semiconductor device having the above-described configuration will be described below.

  25 to 37 are cross-sectional views showing respective steps in the manufacturing process of the semiconductor device shown in FIG.

  In FIGS. 25 to 39, (a) shows the BiCMOS element portion of the semiconductor device, and (b) shows the resistance element portion.

  As shown in FIG. 25, a field oxide film 6, a buried layer 2 (N + type), a buried layer 3 (P + type), and an N type epitaxial layer 27 are provided on a P type silicon substrate 1. Then, an N-type well 4 is formed on the buried layer 2 and a P-type well 5 is formed on the buried layer 3. Further, an N-type polysilicon film 29 and a CVD oxide film 28A are provided on the N-type well 4, the P-type well 5, and the N-type epitaxial layer 27 via a gate oxide film 7C, respectively. N-type polysilicon film 29 and CVD oxide film 28A are also formed on field oxide film 6 in the resistance element portion (FIG. 25B). Thereafter, an N-type polysilicon film is formed so that a stacked structure of the N-type polysilicon film 29 and the CVD oxide film 28A is formed on the active region of the CMOS transistor, the collector region of the bipolar transistor, and the resistance element forming region. 29 and the oxide film 28A are patterned.

25, sidewalls 31A (sidewall oxide films) are formed on the sidewalls of the stacked film of the N-type polysilicon film 29 and the oxide film 28A. As shown in FIG. 26, as shown in FIG. P-type polysilicon film 30 is formed so as to cover the whole (hereinafter sometimes referred to as the entire surface). The P-type polysilicon film 30 is formed by depositing a polysilicon film not doped with impurities on the entire surface, and then implanting a P-type impurity (for example, BF ₂ implantation, 50 KeV, 1.0 × 10 ¹⁴ cm ^−2, etc.). ).

From the state of FIG. 26, a CVD oxide film 28B and a resist film are formed on the P-type polysilicon film 30 and the oxide film 28B over the entire surface. After patterning the resist film, the P-type polysilicon film 30 and the oxide film 28B are etched to form openings 32 in the vicinity of the emitter region and base region forming portions as shown in FIG. . Further, a P-type impurity is implanted from the opening 32 (BF ₂ implantation, 20 KeV, 3.0 × 10 ¹³ cm ^−2, etc.) to form a base region 33A.

From the state of FIG. 27, sidewalls 31B (sidewall oxide films) are formed on the sidewalls of the opening 32, P-type impurities are implanted (BF ₂ implantation, 20 KeV, 6.0 × 10 ¹³ cm ⁻² etc.), and By performing heat treatment at about 800 ° C., intrinsic base region 33B is formed as shown in FIG.

From the state of FIG. 28, an N-type polysilicon film is formed over the entire surface. As for the N-type polysilicon film, a polysilicon film not doped with impurities is deposited on the entire surface, and then N-type impurities are implanted (for example, As implantation, 50 KeV, 1.0 × 10 ¹⁶ cm ^−2, etc.). It is formed by. Further, by performing a heat treatment at about 800 ° C., an emitter region 34 is formed as shown in FIG. Thereafter, a resist mask 9D is formed, and the emitter electrode 35 is formed by etching the N-type polysilicon film.

  From the state of FIG. 29, the CVD oxide film 28B is removed using the resist mask 9D as it is. As a result, the P-type polysilicon film 30 is exposed as shown in FIG.

  From the state of FIG. 30, the P-type polysilicon film 30 is patterned to form a base electrode 36 as shown in FIG. Thereafter, CVD oxide film 28A and sidewall 31A are removed, and N-type polysilicon film 29 is exposed.

  From the state of FIG. 31, a resist film is formed over the entire surface. The resist film is patterned to form a resist mask 9E as shown in FIG. The resist mask 9E is provided so as to mask the emitter and base regions of the bipolar transistor, the gate electrode forming portion of the MOS transistor, and the polysilicon film forming portion for the resistance element. Further, the N-type polysilicon film 29 is etched using the resist mask 9E as a mask. As a result, the gate electrode 7 and the polysilicon film 8 for the resistance element are formed.

From the state of FIG. 32, the resist mask 9E is removed, and a resist film is formed again. As shown in FIG. 33, the resist film is patterned so as to have openings in the region where the NMOS transistor is provided and in the vicinity of the collector region of the bipolar transistor, thereby forming a resist mask 9A. A relatively low concentration of N-type impurity is implanted into this opening (for example, phosphorus implantation, 70 KeV, 1.8 × 10 ¹³ cm ⁻² , 45 ° rotation implantation, etc.), and the N− source / drain regions 10 and N− Impurity region 10A is formed.

From the state of FIG. 33, the resist mask 9A is removed, and a resist film is formed again. As shown in FIG. 34, the resist film is patterned so as to have an opening in a region where the PMOS transistor is provided, and a resist mask 9B is formed. A relatively low concentration P-type impurity is implanted into this opening (for example, boron implantation, 10 KeV, 1.0 × 10 ¹³ cm ⁻² , 7-degree rotational implantation, etc.), and a P-source / drain region 11 is formed. The

  From the state of FIG. 34, the resist mask 9B is removed, and an oxide film (CVD oxide film) is formed over the entire surface by CVD or the like. Then, by performing dry etching on the oxide film, sidewalls 12 (sidewall oxide films) are formed on the gate electrode 7 and the polysilicon film 8 as shown in FIG. Sidewall 12 is also formed on the side wall of the laminated structure of oxide film 28 </ b> A and emitter electrode 35 and on the side wall of base electrode 36. Here, the dry etching is performed so that the CVD oxide film on the field oxide film 6 is sufficiently removed (for example, 125% or more with respect to the film thickness of the CVD oxide film). Therefore, the field oxide film 6 is reduced by this dry etching process.

From this state, a resist film is formed again. The resist film is patterned so as to have an opening in a region where the NMOS transistor is provided, and a resist mask 9A is formed. An N-type impurity having a concentration higher than that described above is implanted into the opening (for example, phosphorus implantation, 100 KeV, 2.0 × 10 ¹⁴ cm ⁻² , 60 ° rotation implantation, arsenic implantation, 50 KeV, 4.0 × 10 ¹⁵ etc. cm ^-2), N + source / drain regions 13 and collector electrode 37 are formed.

  35, the resist mask 9A is removed, and an oxide film (CVD oxide film) is formed so as to cover the N-type well 4, the P-type well 5, and the field oxide film 6 by a CVD method or the like. Then, by performing dry etching on the oxide film while protecting the region where the oxide film for the resistance element is formed with a resist, as shown in FIG. 36, the sidewall 16 and the polysilicon are formed outside the sidewall 12. An oxide film 15 is formed on a part of the film 8. A silicide film 19 to be described later is not formed in the region where the oxide film 15 is formed. Here, the dry etching is performed so that the CVD oxide film on the polysilicon film 8 is sufficiently removed (for example, 125% or more with respect to the film thickness of the CVD oxide film). Accordingly, the field oxide film 6 is further reduced by this dry etching process.

From the state of FIG. 36, a resist film is formed again. As shown in FIG. 37, the resist film is patterned so as to have an opening in a region where the PMOS transistor is provided, and a resist mask 9B is formed. A P-type impurity having a higher concentration than the above is implanted into the opening (for example, BF ₂ implantation, 40 KeV, 4.0 × 10 ¹⁵ cm ^−2, etc.), and a P + source / drain region 14 is formed.

  37, the silicide film 19 is formed on the gate electrode 7, the polysilicon film 8, the N + source / drain region 13, the P + source / drain region 14, the emitter electrode 35, the base electrode 36, and the collector electrode 37. The Thereby, the structure shown in FIG. 38 is obtained.

  As shown in FIG. 39, the interlayer insulating film 23 is deposited over the entire surface from the state of FIG. A contact hole 20 reaching the silicide film 19 is provided in the interlayer insulating film 23. In the contact hole 20, a barrier metal 21A is formed on the inner peripheral surface thereof, and a metal wiring 21 (for example, in a region surrounded by the barrier metal 21A). Including tungsten). Metal interconnection 21 is connected to metal interconnection 22 (including, for example, aluminum) on interlayer insulating film 23.

  In the present embodiment, the structure of the semiconductor device according to the first embodiment is applied to a BiCMOS type semiconductor device through the above-described steps. As a result, in the BiCMOS type semiconductor device, the silicide film 19 penetrates the junction surface between the P + source / drain region 14 and the N type well 4 and reaches the N type well 4 as in the first embodiment. Can be suppressed. As a result, the occurrence of PN junction leakage can be suppressed, and the operation reliability of the semiconductor integrated circuit is improved. The other effects are also the same as in the first embodiment.

  It is also possible to combine the process of forming the bipolar transistor described above with the manufacturing process of the semiconductor device according to the second and third embodiments.

  In the present embodiment, detailed description of the same matters as those of the above-described embodiments will not be repeated.

  As mentioned above, although embodiment of this invention was described, combining the characteristic part of each embodiment mentioned above suitably is planned from the beginning. Moreover, it should be thought that embodiment disclosed this time is an illustration and restrictive at no points. The scope of the present invention is defined by the terms of the claims, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

It is sectional drawing which showed the 1st process in the manufacturing process of the CMOS element part in the semiconductor device which concerns on Embodiment 1 of this invention. It is sectional drawing which showed the 2nd process in the manufacturing process of the CMOS element part in the semiconductor device which concerns on Embodiment 1 of this invention. It is sectional drawing which showed the 3rd process in the manufacturing process of the CMOS element part in the semiconductor device which concerns on Embodiment 1 of this invention. It is sectional drawing which showed the 4th process in the manufacturing process of the CMOS element part in the semiconductor device which concerns on Embodiment 1 of this invention. It is sectional drawing which showed the 5th process in the manufacturing process of the CMOS element part in the semiconductor device which concerns on Embodiment 1 of this invention. It is sectional drawing which showed the 6th process in the manufacturing process of the CMOS element part in the semiconductor device which concerns on Embodiment 1 of this invention. It is sectional drawing which showed the intermediate process in the manufacturing process of the N type / P type diffused region part in the semiconductor device which concerns on Embodiment 1 of this invention. It is sectional drawing which showed the 7th process in the manufacturing process of the CMOS element part in the semiconductor device which concerns on Embodiment 1 of this invention. It is sectional drawing which showed the CMOS element part in the semiconductor device which concerns on Embodiment 1 of this invention. It is sectional drawing which showed the state which provided the upper wiring layer in the CMOS element part in the semiconductor device which concerns on Embodiment 1 of this invention. 5 is a cross-sectional view showing a state in which an upper wiring layer is provided in an N-type / P-type diffusion region portion in the semiconductor device according to the first embodiment of the present invention. It is sectional drawing which showed the 1st process in the manufacturing process of the CMOS element part in the semiconductor device which concerns on Embodiment 2 of this invention. It is sectional drawing which showed the 2nd process in the manufacturing process of the CMOS element part in the semiconductor device which concerns on Embodiment 2 of this invention. It is sectional drawing which showed the CMOS element part in the semiconductor device which concerns on Embodiment 2 of this invention. It is sectional drawing which showed the 1st process in the manufacturing process of the CMOS element part in the semiconductor device which concerns on Embodiment 3 of this invention. It is sectional drawing which showed the 2nd process in the manufacturing process of the CMOS element part in the semiconductor device which concerns on Embodiment 3 of this invention. It is sectional drawing which showed the 3rd process in the manufacturing process of the CMOS element part in the semiconductor device which concerns on Embodiment 3 of this invention. It is sectional drawing which showed the CMOS element part in the semiconductor device which concerns on Embodiment 3 of this invention. It is a top view which shows the semiconductor device which concerns on Embodiment 4 of this invention. It is a figure which shows the XX-XX cross section in FIG. It is a figure which shows the XXI-XXI cross section in FIG. FIG. 20 is a top view showing a conventional semiconductor device compared with the semiconductor device shown in FIG. 19. It is a figure which shows the XXIII-XXIII cross section in FIG. It is a figure which shows the XXIV-XXIV cross section in FIG. It is sectional drawing which showed the 1st process in the manufacturing process of the semiconductor device which concerns on Embodiment 5 of this invention, (a) shows a BiCMOS element part, (b) shows a resistance element part. It is sectional drawing which showed the 2nd process in the manufacturing process of the semiconductor device which concerns on Embodiment 5 of this invention, (a) shows a BiCMOS element part, (b) shows a resistance element part. It is sectional drawing which showed the 3rd process in the manufacturing process of the semiconductor device which concerns on Embodiment 5 of this invention, (a) shows a BiCMOS element part, (b) shows a resistance element part. It is sectional drawing which showed the 4th process in the manufacturing process of the semiconductor device which concerns on Embodiment 5 of this invention, (a) shows a BiCMOS element part, (b) shows a resistance element part. It is sectional drawing which showed the 5th process in the manufacturing process of the semiconductor device which concerns on Embodiment 5 of this invention, (a) shows a BiCMOS element part, (b) shows a resistance element part. It is sectional drawing which showed the 6th process in the manufacturing process of the semiconductor device which concerns on Embodiment 5 of this invention, (a) shows a BiCMOS element part, (b) shows a resistance element part. It is sectional drawing which showed the 7th process in the manufacturing process of the semiconductor device which concerns on Embodiment 5 of this invention, (a) shows a BiCMOS element part, (b) shows a resistance element part. It is sectional drawing which showed the 8th process in the manufacturing process of the semiconductor device which concerns on Embodiment 5 of this invention, (a) shows a BiCMOS element part, (b) shows a resistance element part. It is sectional drawing which showed the 9th process in the manufacturing process of the semiconductor device which concerns on Embodiment 5 of this invention, (a) shows a BiCMOS element part, (b) shows a resistance element part. It is sectional drawing which showed the 10th process in the manufacturing process of the semiconductor device which concerns on Embodiment 5 of this invention, (a) shows a BiCMOS element part, (b) shows a resistance element part. It is sectional drawing which showed the 11th process in the manufacturing process of the semiconductor device which concerns on Embodiment 5 of this invention, (a) shows a BiCMOS element part, (b) shows a resistance element part. It is sectional drawing which showed the 12th process in the manufacturing process of the semiconductor device which concerns on Embodiment 5 of this invention, (a) shows a BiCMOS element part, (b) shows a resistance element part. It is sectional drawing which showed the 13th process in the manufacturing process of the semiconductor device which concerns on Embodiment 5 of this invention, (a) shows a BiCMOS element part, (b) shows a resistance element part. It is sectional drawing which showed the semiconductor device which concerns on Embodiment 5 of this invention, (a) shows a BiCMOS element part, (b) shows a resistive element part. It is sectional drawing which showed the state which provided the upper wiring layer in the semiconductor device which concerns on Embodiment 5 of this invention, (a) shows a BiCMOS element part, (b) shows a resistance element part.

Explanation of symbols

  1 silicon substrate, 2 buried layer (N + type), 3 buried layer (P + type), 4,4A N type well, 5,5A P type well, 6 field oxide film, 7A, 7B gate electrode, 7C gate oxide film, 8 Polysilicon film, 9A, 9B, 9C, 9D, 9E Resist mask, 10 N-source / drain region, 10A N-impurity region, 11 P-source / drain region, 12, 16, 16A, 16B, 31A, 31B Side wall (side wall oxide film), 15, 15A, 16C, 26, 28A, 28B oxide film, 13 N + source / drain region, 14 P + source / drain region, 14A, 14B impurity region, 17 N type diffusion region, 18 P Type diffusion region, 19 silicide film, 20 contact hole, 21, 22 metal wiring, 21A barrier metal, 2 Interlayer insulating film, 25 contact portion, 27 N-type epitaxial layer, 29 N-type polysilicon layer, 30 P-type polysilicon layer, 32 opening, 33A base region, 33B intrinsic base region, 34 emitter region, 35 emitter electrode, 36 Base electrode, 37 collector electrode, 70A, 70B dummy gate, 70C oxide film.

Claims (6)

A manufacturing method of a semiconductor device having a CMOS (Complementary Metal Oxide Semiconductor) element portion and a resistance element portion,
Forming a first conductive type first active region, a second conductive type second active region, and an element isolation insulating film on a substrate;
Forming first and second gate electrodes on the first and second active regions via a gate insulating film, respectively, and a conductive film on the element isolation insulating film;
Forming a first sidewall insulating film on sidewalls of the first and second gate electrodes;
Forming first source / drain regions of a first conductivity type on both sides of the second gate electrode in the second active region;
An insulating layer is formed on the first and second active regions from above the conductive film, and the insulating layer is etched to form an insulating film on a part of the conductive film, and the first sidewall insulation Forming a second sidewall insulating film on the film;
Forming a second source / drain region of a second conductivity type on both sides of the first gate electrode in the first active region after forming the insulating film and the second sidewall insulating film;
A method of manufacturing a semiconductor device, comprising: forming a silicide film on the first and second gate electrodes, on the first and second source / drain regions, and on the conductive film.   The method of manufacturing a semiconductor device according to claim 1, wherein the first source / drain region is formed after the formation of the insulating film and the second sidewall insulating film. A manufacturing method of a semiconductor device having a CMOS (Complementary Metal Oxide Semiconductor) element portion and a resistance element portion,
Forming a first conductive type first active region, a second conductive type second active region, and an element isolation insulating film on a substrate;
Forming first and second gate electrodes on the first and second active regions via a gate insulating film, respectively, and a conductive film on the element isolation insulating film;
Forming an insulating layer on the first and second active regions from above the conductive film;
Forming a first mask film having an opening on the second active region;
Etching the insulating layer using the first mask film as a mask to form a sidewall insulating film on a sidewall of the second gate electrode;
A first source / drain region is formed by introducing a first conductivity type impurity on both sides of the second gate electrode in the second active region using the first mask film and the sidewall insulating film as a mask. Process,
Forming a second mask film having an opening on a part of the first active region and the conductive film;
Etching the insulating layer using the second mask film as a mask to form another sidewall insulating film on the side wall of the first gate electrode, and forming an insulating film on a part of the conductive film; ,
A second source / drain region is formed by introducing a second conductivity type impurity on both sides of the first gate electrode in the first active region using the second mask film and the other sidewall insulating film as a mask. Forming, and
A method of manufacturing a semiconductor device, comprising: forming a silicide film on the first and second gate electrodes, on the first and second source / drain regions, and on the conductive film. A method of manufacturing a semiconductor device having a MOS (Metal Oxide Semiconductor) transistor and a resistance element portion,
Forming a first conductivity type active region and an element isolation insulating film on a substrate;
Forming a gate electrode on the active region via a gate insulating film and a conductive film on the element isolation insulating film;
Forming a first sidewall insulating film on a sidewall of the gate electrode;
An insulating layer is formed on the conductive region from the conductive film, and the insulating layer is etched to form an insulating film on a part of the conductive film, and a second layer is formed on the first sidewall insulating film. Forming a sidewall insulating film;
Forming a second conductivity type source / drain region on both sides of the gate electrode in the active region after forming the insulating film and the second sidewall insulating film;
A method of manufacturing a semiconductor device, comprising: forming a silicide film on the gate electrode, the source / drain region, and the conductive film. A substrate having a main surface;
An element isolation insulating film selectively formed on the main surface of the substrate;
An active region of a first conductivity type surrounded by the element isolation insulating film;
A gate electrode formed on the active region via a gate insulating film;
First and second dummy gates formed on the active region and on both sides of the gate electrode through insulating films, respectively;
A source / drain region of a second conductivity type formed between the first dummy gate and the gate electrode and between the second dummy gate and the gate electrode;
A first impurity region formed between the first dummy gate and the element isolation insulating film;
A second impurity region formed between the second dummy gate and the element isolation insulating film;
A semiconductor device comprising a silicide film formed on the surface of the source / drain region and on the surfaces of the first and second impurity regions. A substrate having a main surface;
An element isolation insulating film selectively formed on the main surface of the substrate;
An active region of a first conductivity type surrounded by the element isolation insulating film;
A source / drain region of a second conductivity type formed in the active region so as to reach the element isolation insulating film located on both sides of the active region;
An insulating film extending from an end of the element isolation insulating film to an end of the source / drain region at both ends of the source / drain region;
A silicide film formed on the source / drain regions located between the insulating films;
A semiconductor device comprising: a gate electrode formed on the active region via a gate insulating film.

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