JP2005229553A - Image processing apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a novel image processing apparatus which is capable of reproducing a plurality of pictures of still picture data at an arbitrary speed. <P>SOLUTION: Each of a plurality of banks formed in an SDRAM 24 is selected in a circulating manner once 1/29.97 sec by a CPU 30. An MPEG-4 CODEC 38 writes image data of one frame obtained at the interval of 1/29.97 sec in thus selected bank. Furthermore, the CPU 30 specifies a bank preceding to the selected bank at the interval of 1/25 sec. Image data written in a specified bank are read out by a video encoder 26. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an image processing apparatus, and more particularly to an image processing apparatus that is applied to, for example, a digital video camera and converts a frame rate of moving image data.

An example of a conventional image processing apparatus of this type is disclosed in Patent Document 1. In this prior art, when reproducing moving image data composed of compressed still image data, the time required for reproduction processing of one frame of compressed still image data (1 frame reading → 1 frame expansion → 1 frame display) and the moving image data The frame decimation number is calculated based on the frame rate, and the decimation process according to the calculated frame decimation number is performed on the moving image data. As a result, even when the playback process takes longer than expected, a moving image that moves in real time can be played back.
JP 2002-320189 A [H04N 5/91, 5/225, G03B 15/00, 17/48, 19/02]

    However, in the conventional technique, the time required for the reproduction process is measured only for one frame. For this reason, when the size of compressed still image data varies greatly between frames and the size of the frame to be measured is small, the frame decimation number deviates from the optimum value, and the moving image is played back in real time. Can not do it.

    Therefore, a main object of the present invention is to provide a novel image processing apparatus that can reproduce still image data of a plurality of screens at an arbitrary speed.

  The image processing apparatus according to the first aspect of the present invention provides a selection means for cyclically selecting each of a plurality of memory areas for each first period, and a memory area in which still image data obtained for each first period is selected by the selection means. A writing means for writing to the memory, a specifying means for specifying a memory area that is a predetermined number of areas away from a memory area selected by the selecting means among a plurality of memory areas, each time the second period elapses, and a memory area specified by the specifying means Readout means for reading out still image data stored in the

  Each of the plurality of memory areas is cyclically selected by the selection unit every first period. The writing means writes the still image data obtained every first period into the memory area thus selected. The specifying unit specifies a memory area that is a predetermined number of areas away from the selected memory area every time the second period elapses. The still image data stored in the specified memory area is read by the reading means.

  That is, still image data obtained every first period is output every second period via a plurality of memory areas. Thereby, still image data of a plurality of screens can be reproduced at an arbitrary speed.

  An image processing apparatus according to a second aspect of the invention is dependent on the first aspect, further comprising decompression means for decompressing the compressed still image data for each first period, and the writing means writes to the still image data decompressed by the decompression means. Apply processing.

  The image processing apparatus according to the invention of claim 3 is dependent on claim 2, and the compressed still image data is image data compressed in accordance with the MPEG system.

  An image processing apparatus according to a fourth aspect of the invention is dependent on any one of the first to third aspects, wherein the reading means reads still image data in an interlaced scanning mode, and the first period is one frame period corresponding to the first format. And the second period is a one-field period corresponding to the second format. As a result, the specifying unit cyclically specifies a plurality of memory areas, and the motion of the reproduced image becomes smooth.

  An image processing apparatus according to a fifth aspect of the invention is dependent on the fourth aspect, wherein one frame period corresponding to the first format is shorter than one frame period corresponding to the second format, and 1 corresponding to the second format. Longer than the field period.

  An image processing apparatus according to a sixth aspect of the present invention is dependent on any one of the first to fifth aspects, and the still image data obtained for each first period forms a moving image.

  An image processing apparatus according to a seventh aspect of the invention is dependent on any one of the first to sixth aspects, wherein one of the first period and the second period corresponds to the NTSC system, and the other of the first period and the second period is PAL. Corresponds to the method. Thereby, still image data of a plurality of screens created according to one of the NTSC system and the PAL system can be reproduced in a mode according to the other of the NTSC system and the PAL system.

  An image processing apparatus according to an invention of claim 8 is dependent on any one of claims 1 to 7, and further comprises a determining means for determining the number of memory areas selected by the selecting means based on the first period and the second period. Prepare. As a result, the size required for mapping the memory area can be flexibly changed, and the efficiency of the memory capacity can be improved.

  A digital video camera according to a ninth aspect of the invention includes the image processing apparatus according to any one of the first to eighth aspects.

  According to the present invention, still image data obtained every first period is output every second period via a plurality of memory areas, so that still image data of a plurality of screens can be reproduced at an arbitrary speed. .

  The above object, other objects, features and advantages of the present invention will become more apparent from the following detailed description of embodiments with reference to the drawings.

  Referring to FIG. 1, a digital video camera 10 of this embodiment includes an optical lens 12. The optical image of the object scene is irradiated on the imaging surface of the image sensor 14 through the optical lens 12. On the imaging surface, a charge corresponding to the optical image of the object scene, that is, a raw image signal is generated by photoelectric conversion.

  When the camera mode is selected by the mode key 36m provided on the key input device 36, a through image process, that is, a process for displaying a real-time moving image of the object scene on the LCD monitor 28 is executed. The CPU 30 instructs a TG / SG (Timing Generator / Signal Generator) 18 to repeat pre-exposure and charge reading. The TG / SG 18 periodically generates a vertical synchronizing signal and a horizontal synchronizing signal, and supplies a plurality of timing signals synchronized therewith to the image sensor 14 and the CDS / AGC / AD circuit 16. As a result, the pre-exposure of the image sensor 14 and the reading of the raw image signal generated thereby are repeatedly executed. The output raw image signal of each frame is subjected to a series of processes of noise removal, level adjustment and A / D conversion by the CDS / AGC / AD circuit 16, thereby obtaining raw image data which is a digital signal.

  The vertical synchronization signal generated by the TG / SG 18 is generated once every 1 / 29.97 seconds so as to satisfy the NTSC system. Therefore, the raw image data output from the CDS / AGC / AD circuit 16 has a frame rate of 29.97 fps.

  The CPU 30 gives a processing command to the signal processing circuit 20 in response to the vertical synchronization signal output from the TG / SG 18. The signal processing circuit 20 performs processing such as white balance adjustment, color separation, and YUV conversion on the raw image data of each frame output from the CDS / AGC / AD circuit 16 to generate image data in YUV format. The generated image data is written into the SDRAM 24 by the memory control circuit 22.

  When the camera mode is selected, a clock corresponding to the NTSC system is supplied to the video encoder 26 and the frequency divider 40. The frequency divider 40 divides a given clock and outputs a 29.97 Hz vertical synchronizing signal according to the NTSC system. In response to this vertical synchronization signal, the CPU 30 instructs the video encoder 26 to perform one-frame encoding processing.

  The video encoder 26 reads out one frame of image data from the SDRAM 24 through the memory control circuit 22 in an interlaced scan mode every time an encoding process is commanded. The read image data is converted into a composite video signal according to the NTSC system, and the converted composite video signal is applied to the LCD monitor 28. As a result, a through image of the scene is displayed on the monitor screen. In the following description, although the description is omitted as appropriate, access to the SDRAM 24 is always performed through the memory control circuit 22.

  The clock corresponding to the NTSC system is also supplied to the MPEG4 codec 38 and the frequency divider 42. The frequency divider 42 divides a given clock and outputs a 29.97 Hz vertical synchronizing signal according to the NTSC system.

  When the moving image recording key 36r is operated, the CPU 30 instructs the MPEG4 codec 38 to perform compression processing for one frame in response to the vertical synchronization signal output from the frequency divider 42. The MPEG4 codec 38 reads out one frame of image data from the SDRAM 24 every time compression processing is commanded. The read image data is subjected to compression processing according to the MPEG4 simple profile. The image data is subjected to intra coding at a rate of about once every several tens to several hundred frames, and inter coding is performed on the remaining frames. As a result, compressed image data composed of a plurality of GOPs (Group Of Pictures) is generated.

  The generated compressed image data is once written in the SDRAM 24 and then recorded on the recording medium 34 in a file format by the CPU 30. When the moving image recording key 36r is operated again, the CPU 30 stops issuing the compression processing command, and closes the moving image file when recording of the compressed image data remaining in the SDRAM 24 is completed. Note that the recording medium 34 is a detachable medium, and can be accessed through the I / F circuit 32 when mounted in a slot (not shown).

  When the external output terminal T1 is connected to a television monitor (not shown) compatible with the PAL system and the playback mode is selected by the mode key 36m, playback processing of an arbitrary moving image file is executed. At this time, as shown in FIG. 2, a bank 24a (bank 0), a bank 24b (bank 1), a bank 24c (bank 2), and an MPEG data area 24d are formed on the SDRAM 24.

  The CPU 30 transfers the compressed image data stored in the moving image file to the MPEG data area 24d by 1 GOP. The frequency divider 42 outputs a vertical synchronization signal of 29.97 Hz even in the reproduction mode, and the CPU 30 instructs the MPEG4 codec 38 to perform decompression processing every time the vertical synchronization signal is output. The MPEG4 codec 38 reads one frame of compressed image data from the SDRAM 24, expands the read compressed image data, and writes the expanded image data to any one of the banks 24a to 24c.

  In the reproduction mode, the clock supplied to the video encoder 26 and the frequency divider 40 has a frequency corresponding to the PAL system. The frequency divider 40 divides the clock and outputs a 25 Hz vertical synchronizing signal. In response to the vertical synchronization signal, the CPU 30 instructs the video encoder 26 to encode one frame of image data. The video encoder 26 reads out one frame of image data from any one of the banks 24a to 24c in an interlaced scan mode, and converts the read image data into a composite video signal in accordance with the PAL system. The converted composite video signal is output from the external output terminal T1 to the television monitor. As a result, the playback moving image is displayed on the monitor screen. Note that when the reproduction process directed to the television monitor is executed, the LCD monitor 28 is turned off.

  A bank for writing image data, that is, a destination bank, is designated in response to a vertical synchronization signal corresponding to the NTSC system, and a bank for reading image data, that is, a destination bank, is designated in response to a vertical synchronization signal corresponding to the PAL system. Is done. The write destination bank is cyclically designated in the order of bank 24a → bank 24b → bank 24c → bank 24a →. The read destination bank is the bank immediately before the write destination bank. Therefore, writing / reading of image data is performed as shown in FIG.

  The NTSC vertical synchronizing signal has a frequency of 29.97 Hz, while the PAL vertical synchronizing signal has a frequency of 25 Hz. In order to prevent overtaking of the address on the SDRAM 24 due to such a frequency difference, the CPU 30 performs the write bank control task shown in FIG. 3 and the read bank control task shown in FIG. 4 when the reproduction mode is selected. Run in parallel. Note that control programs corresponding to these tasks are stored in the flash memory 44.

  Referring to FIG. 3, in step S1, variable i and MP4_DEC_BANK are set to “0”. A variable i is a variable indicating a frame number, and a variable MP4_DEC_BANK is a variable indicating a bank number into which image data output from the MPEG4 codec 38 is written.

  In step S3, it is determined whether or not a vertical synchronization signal corresponding to the NTSC system has been output from the frequency divider 42. If YES, the variable MP4_DEC_BANK is updated according to equation 1 in step S5.

  According to Equation 1, “1” is added to the current value of the variable MP4_DEC_BANK, and the obtained addition value is divided by “3”. The remainder obtained by the division becomes the value of the updated variable MP4_DEC_BANK. For example, if the calculated remainder is “2”, the bank 24c (bank 2) becomes the write destination bank.

  In step S7, the MPEG4 codec 38 is instructed to decompress one frame. This command includes a frame number (= i) and a bank number (= MP4_DEC_BANK). The MPEG4 codec 38 reads compressed image data of a designated frame from the MPEG data area 24d, decompresses the read compressed image data, and writes the decompressed image data to a designated bank.

  In step S9, the variable i is incremented, and in the subsequent step S11, it is determined whether or not the updated variable i exceeds the total number of frames of the compressed image data stored in the moving image file. If “NO” here, the process returns to the step S3, and if “YES”, the write bank control task is ended.

  Therefore, while it is determined NO in step S11, the write destination bank is cyclically updated in the manner of bank 0 → bank 1 → bank 2 → bank 0 → ... in response to the vertical synchronization signal of 29.97 fps. The The image data of each frame expanded in response to the vertical synchronizing signal is written in the write destination bank thus designated.

  Referring to FIG. 4, in step S21, it is determined whether or not a vertical synchronization signal corresponding to the PAL system is output from frequency divider 40. If YES, variable VID_ENC_BANK is obtained in accordance with equation 2 in step S23.

  According to Equation 2, “2” is added to the variable MP4_DEC_BANK, and the obtained addition value is divided by “3”. The remainder obtained by the division is set as a variable VID_ENC_BANK. The variable VID_ENC_BANK obtained in this way indicates the number of the bank from which image data for the video encoder 26 is read. For example, if the calculated remainder is “1”, the bank 24b (bank 1) becomes the read destination bank.

  In step S25, the video encoder 26 is instructed to encode one frame. This instruction includes a bank number (= VID_ENC_BANK). The video encoder 26 reads one frame of image data from the designated bank, and converts the read image data into a composite video signal according to the PAL system. The converted composite video signal is output from the external output terminal T1.

  In step S27, it is determined whether the reproduction of the moving image is completed. If NO, the process returns to step S21. As a result, each time a 25 fps vertical synchronization signal is generated, the bank immediately before the write destination bank is designated as the read destination bank.

  With reference to the reference timing shown in FIG. 6 (A), the processing directed to bank 0 is executed as shown in FIG. 6 (B), and the processing directed to bank 1 is executed as shown in FIG. 6 (C). And the process directed to the bank 2 is executed as shown in FIG.

  Here, block 1 indicates a period during which one frame of compressed image data is decompressed (decoded) by the MPEG4 codec 38, and block 2 stores the decompressed one frame of image data in a bank. Indicates the period. Block 3 indicates a free period in which no image data exists, and block 4 indicates a period in which one frame of image data is encoded by the video encoder 26.

  Further, block 5 indicates a period during which decompression processing is performed on image data of a frame in which encoding by the video encoder 26 is stopped, and block 6 indicates that image data of a frame in which encoding by the video encoder 26 is stopped is in a bank. Indicates the retention period.

  The bank designated as the read destination is the bank immediately before the bank designated as the write destination at the head timing of the block 4. Accordingly, the fifth frame of image data directed to the video encoder 26 is read from the bank 2 instead of the bank 1. The read image data is data output from the MPEG4 codec 38 in the sixth frame. Similarly, the 10th frame image data directed to the video encoder 26 is read from the bank 2 instead of the bank 1. The read image data is data output from the MPEG4 codec 38 in the 12th frame.

  By performing such bank switching control, address overtaking on the SDRAM 24 can be avoided, and noise extending in the horizontal direction on the monitor screen can be prevented from appearing.

  In the digital video camera 10 of another embodiment, when the reproduction mode is selected, the frequency divider 40 outputs a 50 Hz vertical synchronizing signal based on a clock corresponding to the PAL system, and the CPU 30 is shown in FIG. This embodiment is the same as the embodiment shown in FIG. 1 except that the read bank control task shown is executed. For this reason, the duplicate description regarding the same part is abbreviate | omitted.

  Referring to FIG. 7, in step S <b> 31, it is determined whether or not a vertical synchronization signal is output from frequency divider 42. If YES, the process proceeds to step S33, and the variable VID_ENC_BANK is calculated according to the above equation 2. In step S35, the video encoder 26 is instructed to encode one field. This instruction includes the bank number (= VID_ENC_BANK) of the read destination.

  The video encoder 26 reads one field of image data from the designated bank. The field of the image data to be read alternately changes in the order of odd field → even field → odd field →... Regardless of the bank designation change. The video encoder 26 converts the read image data into a composite video signal corresponding to the PAL system, and outputs the converted composite video signal from the external output terminal T1.

  In step S37, it is determined whether or not the reproduction of the moving image is completed. If NO, the process returns to step S31. As a result, every time a 50 fps vertical synchronizing signal is generated, one field of encoding processing is executed, and a playback moving image is output from the television monitor. If YES is determined in the step S37, the read bank control task is ended.

  Referring to the reference timing shown in FIG. 8 (A), the processing directed to bank 0 is executed as shown in FIG. 8 (B), and the processing directed to bank 1 is executed as shown in FIG. 8 (C). And the process directed to the bank 2 is executed as shown in FIG. Note that block 4 indicates a period during which one field of image data is encoded by the video encoder 26.

  As in the embodiment of FIG. 1, the bank designated as the read destination is the bank immediately before the bank designated as the write destination at the head timing of the block 4. However, the head timing of the block 4 occurs once every 1/50 seconds.

  As a result, the image data of the fourth field directed to the video encoder 26 is read from the bank 2 instead of the bank 1. The read image data is the image data of the first field forming the image data output in the fourth frame from the MPEG4 codec 38. Similarly, the image data of the ninth field directed to the video encoder 26 is read from the bank 2 instead of the bank 1. The read image data is the image data of the first field forming the image data output from the MPEG4 codec 38 at the seventh frame.

  By performing such bank switching control, it is possible to prevent the occurrence of noise extending in the horizontal direction on the monitor screen, as in the embodiment of FIG. Further, in this embodiment, the read destination bank is also designated cyclically in the order of bank 0 → bank 1 → bank 2 → bank 0 →.

  Referring to FIG. 9, the digital video camera 10 of the other embodiment is the same as the embodiment of FIG. 1 except for the points described below.

  The TG / SG 18 generates a 25 Hz vertical synchronizing signal according to the PAL system, and the raw image data output from the CDS / AGC / AD circuit 16 in the camera mode has a frame rate of 25 fps. The video encoder 26 operates in response to a clock corresponding to the PAL system in the camera mode, and operates in response to a clock corresponding to the NTSC system in the reproduction mode directed to the NTSC television monitor (not shown). To do. The MPEG4 codec 38 operates in response to a clock corresponding to the PAL system in both the camera mode and the playback mode.

  The frequency divider 40 outputs a 25 Hz vertical synchronizing signal in accordance with the PAL system in the camera mode, and outputs a 29.97 Hz vertical synchronizing signal in accordance with the NTSC system in the reproduction mode. The frequency divider 42 outputs a 25 Hz vertical synchronizing signal according to the PAL system in both the camera mode and the reproduction mode.

  Accordingly, in the camera mode, a through image having a frame rate of 25 fps is output from the LCD monitor 28, and compressed image data generated at a frame rate of 25 fps is recorded on the recording medium 34 in a file format. In the reproduction mode, the compressed image data recorded on the recording medium 34 is decompressed at a frame rate of 25 fps, and the decompressed image data is converted into an NTSC composite video signal at a frame rate of 29.97 fps.

  When the reproduction mode is selected, the CPU 30 executes the write bank control task shown in FIG. 10 and the read bank control task shown in FIG. 11 in parallel. However, these tasks are the same as the embodiment of FIG. 1 except that the frequency of the vertical synchronization signal noted in step S43 is 25 Hz and the frequency of the vertical synchronization signal noted in step S61 is 29.97 Hz. It is.

  However, since there is such a frequency difference, referring to the reference timing shown in FIG. 12 (A), the processing directed to bank 0 is executed in the manner shown in FIG. 12 (B) and directed to bank 1. The processing is executed as shown in FIG. 12C, and the processing directed to the bank 2 is executed as shown in FIG. As in the embodiment of FIG. 1, the bank designated as the read destination is the bank immediately before the bank designated as the write destination at the head timing of the block 4.

  As a result, the sixth frame image data directed to the video encoder 26 is read from the bank 1 instead of the bank 2. The read image data is image data output from the MPEG4 codec 38 in the fifth frame. Similarly, image data of the 12th frame directed to the video encoder 26 is read from the bank 0 instead of the bank 1. The read image data is the image data output from the MPEG4 codec 38 at the 10th frame.

  As can be seen from the above description, each of the plurality of banks 24a to 24c formed in the SDRAM 24 is cyclically selected by the CPU 30 at a rate of once every 1 / 29.97 seconds or 1/25 seconds ( S3 or S25). The MPEG4 codec 42 writes one frame of image data obtained every 1 / 29.97 seconds or every 1/25 seconds into the bank thus selected. The CPU 30 also specifies the bank immediately before the selected write destination bank every time 1/25 second, 1/50 second, or 1 / 29.97 second elapses (S23, S33 or S63). The image data written in the specified bank is read by the video encoder 26.

  Thereby, a moving image corresponding to one of the NTSC system and the PAL system can be reproduced in a mode according to the other of the NTSC system and the PAL system.

  Referring to FIG. 13, the digital video camera 10 of still another embodiment is the same as the embodiment of FIG. 1 except for the points described below.

  When the reproduction mode is selected, the CPU 30 executes the bank number determination task shown in FIG. First, in step S71, the frame rate information of the moving image data stored in the desired moving image file is acquired from the file header. That is, although omitted in the above description, a header is formed at the head of the moving image file, and frame rate information is written here. In step S71, such frame rate information is acquired. The numerical value indicated by the acquired frame rate information is set in the variable MOV_FPS.

  In step S73, the clock generator 46 is instructed to generate a clock corresponding to the variable MOV_FPS. In step S75, a variable VF_TIME (see FIG. 16) indicating one frame period of the composite video signal output from the video encoder 26 is used as a variable DEC_TIME (= 1 / MOV_FPS).

  Here, if the variable VF_TIME is equal to the variable DEC_TIME, the process proceeds from step S75 to step S79, and the variable BANK_N indicating the number of banks necessary for reproducing the moving image file is set to “2”. On the other hand, if the variable VF_TIME is not equal to the variable DEC_TIME, the process proceeds from step S75 to step S77, and the variable BANK_N is calculated according to Equation 3.

  As can be seen from FIG. 16, the variable ENC_TIME is a variable directed to the composite video signal of each field output from the video encoder 26. Specifically, the variable ENC_TIME indicates the video period belonging to this field from the beginning of the field of interest. This is the period until the end.

  According to Equation 3, the variable ENC_TIME is divided by the variable DEC_TIME, and “3” is added to the integer part of the division value obtained thereby.

  For example, if the frame rate of the moving image data stored in the moving image file is 25 fps and the frame rate of the composite video signal output from the video encoder 26 is 29.97 fps, the variable ENC_TIME is “1 / 59.94-α. "Seconds" and the variable DEC_TIME becomes "1/25" seconds. As a result, the variable BANK_N becomes "3". “Α” corresponds to the blanking period at the end of each field.

  If the frame rate of the moving image data stored in the moving image file is 25 fps and the frame rate of the composite video signal output from the video encoder 26 is 10 fps, the variable ENC_TIME is “1 / 10−α” seconds, The variable DEC_TIME becomes “1/25” seconds, and as a result, the variable BANK_N becomes “5”.

  In the SDRAM 24, a number of banks corresponding to the variable BANK_N determined in step S77 or S79 is formed. In step S81, a write bank control task and a read bank control task are activated, and then this task is terminated.

  Referring to FIG. 15, the write bank control task of this embodiment is the same as that of the above-described embodiment except that attention is paid to the vertical synchronization signal having a period corresponding to variable MOV_FPS in step S3 ′. The vertical synchronizing signal is output from the frequency divider 42 by the process of step S73.

  According to this embodiment, since the number of banks is changed based on the frame rate of moving image data stored in a moving image file, the SDRAM 24 can be used efficiently.

  In the above-described embodiment, only the image data is recorded on the recording medium. However, the audio data may be recorded together with the image data, and the associated image data and audio data may be reproduced simultaneously.

  In the above-described embodiment, the bank immediately before the write destination bank is designated as the read destination bank. However, if the number of banks is larger than three, the bank before the write destination bank or the bank before the third write destination bank is designated. It may be designated as a read destination bank.

It is a block diagram which shows the structure of one Example of this invention. It is an illustration figure which shows an example of the mapping state of SDRAM applied to FIG. 1 Example. It is an illustration figure which shows a part of operation | movement of FIG. 1 Example. It is a flowchart which shows a part of operation | movement of CPU applied to the FIG. 1 Example. It is a flowchart which shows a part of other operation | movement of CPU applied to the FIG. 1 Example. (A) is an illustrative view showing a reference timing, (B) is an illustrative view showing a part of processing directed to bank 0, and (C) shows a part of processing directed to bank 1. FIG. 4D is an illustrative view showing a part of the processing directed to the bank 2; It is a flowchart which shows a part of operation | movement of CPU applied to the other Example of this invention. (A) is an illustrative view showing a reference timing, (B) is an illustrative view showing a part of processing directed to bank 0, and (C) shows a part of processing directed to bank 1. FIG. 4D is an illustrative view showing a part of the processing directed to the bank 2; It is a block diagram which shows the structure of the other Example of this invention. FIG. 10 is a flowchart showing one portion of behavior of a CPU applied to the embodiment in FIG. 9; FIG. 10 is a flowchart showing another portion of behavior of the CPU applied to the embodiment in FIG. 9. (A) is an illustrative view showing a reference timing, (B) is an illustrative view showing a part of processing directed to bank 0, and (C) shows a part of processing directed to bank 1. FIG. 4D is an illustrative view showing a part of the processing directed to the bank 2; It is a block diagram which shows the structure of the other Example of this invention. FIG. 14 is a flowchart showing one portion of behavior of a CPU applied to the embodiment in FIG. 13; FIG. 14 is a flowchart showing another portion of behavior of the CPU applied to the embodiment in FIG. 13; FIG. 14 is an illustrative view showing one portion of behavior of the embodiment in FIG. 13;

Explanation of symbols

10 ... Digital video camera 14 ... Image sensor 24 ... SDRAM
26 ... Video encoder 30 ... CPU
40, 42 ... frequency divider 46 ... clock generator

Claims (9)

Selection means for cyclically selecting each of the plurality of memory areas for each first period;
Writing means for writing still image data obtained for each first period into the memory area selected by the selection means;
A specifying unit that specifies a memory area that is a predetermined number of areas away from the memory area selected by the selection unit among the plurality of memory areas, and stores the memory area in the memory area that is specified by the specifying unit. An image processing apparatus comprising reading means for reading out still image data. Further comprising decompression means for decompressing compressed still image data for each of the first periods;
The image processing apparatus according to claim 1, wherein the writing unit performs a writing process on the still image data expanded by the expansion unit.   The image processing apparatus according to claim 2, wherein the compressed still image data is image data compressed in accordance with an MPEG system. The reading means reads the still image data in an interlaced scanning manner;
4. The image processing apparatus according to claim 1, wherein the first period is one frame period corresponding to a first format, and the second period is one field period corresponding to a second format. 5.   The image processing device according to claim 4, wherein one frame period corresponding to the first format is shorter than one frame period corresponding to the second format and longer than one field period corresponding to the second format.   The image processing apparatus according to claim 1, wherein the still image data obtained for each first period forms a moving image. One of the first period and the second period corresponds to the NTSC system,
The image processing apparatus according to claim 1, wherein the other of the first period and the second period corresponds to a PAL system.   The image processing apparatus according to claim 1, further comprising a determination unit that determines the number of memory areas selected by the selection unit based on the first period and the second period.   A digital video camera comprising the image processing apparatus according to claim 1.

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