JP2005229552A - Slew rate control apparatus, output buffer and information processing apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent a malfunction by detecting presence/non-presence of ringing in an output signal waveform of an output buffer thereby changing a driving capability of a driving means without using a component, such as a damping resistor, inverse bias or ferrite beads and without adjusting and setting the driving capability from the outside. <P>SOLUTION: If ringing occurs when an output signal waveform (b) from an output buffer 20 rises and falls, it is detected, and driving capability of a PMOS transistor group in an H level side driving means 22a and of an NMOS transistor group in an L level side driving means 22b is controlled to be decreased step by step by driving signals from an H level side slew rate control apparatus 10a and an L level side slew rate control apparatus 10b. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a slew rate control apparatus applicable to, for example, a semiconductor integrated circuit, an output buffer using the slew rate control apparatus, and an information processing apparatus using the output buffer.

  In recent years, with the increase in the operating speed of semiconductor devices and the miniaturization of devices on which semiconductor devices are mounted, the narrowing of printed circuit board wiring has become a trend of the times. Accordingly, in an information processing apparatus including a memory and a logic (logic circuit), a high-speed operation is also required for an output buffer used for outputting data inside the chip to the outside.

  In order to meet the demand for higher operating speed for such an output buffer, the output signal waveform generally rises by increasing the driving capability of the output stage using a transistor having a size on the order of several hundred μm. In addition, a method of shortening the fall time is used.

  However, with this method, ringing in the output signal waveform due to an increase in driving capability due to the use of a large transistor, an increase in parasitic inductance components, and a difference between the load condition set during manufacturing and the load condition during actual use. Is likely to occur, and there is a high risk of malfunction.

  For example, as shown in FIG. 11, when an output signal waveform b (3) in which ringing as shown by a two-dot chain line is superimposed on an input signal waveform a as an output signal waveform b from the output buffer is output. think about.

  When such an output signal waveform b (3) is read by a CPU (central processing unit) of a computer, the output signal waveform b (3) is originally at the H level at time t1, but the output signal waveform b (3 The CPU that reads 3) misunderstands that it is within the L level voltage range.

  At time t2, the output signal waveform b (3) is originally at the L level, but the CPU that reads the output signal waveform b (3) may misunderstand that it is within the H level voltage range. As a result, the CPU fails to read the signal and runs out of control.

  Further, even when the output signal waveform b (3) on which such ringing is superimposed is input to other logic (logic circuit), for the same reason, a malfunction such as a glitch occurs in the logic output is caused. become.

  Further, since this ringing includes a lot of high frequency components, it causes EMI (Electro Magnetic Interference) and may cause malfunction not only to other peripheral circuits but also to other devices.

  In order to solve such ringing problems, conventionally, a damping resistor designed to suppress signal ringing is inserted in series in a signal transmission line (hereinafter simply referred to as a transmission line), or a reverse-biased diode. Alternatively, various methods such as clamping a transmission line to a power supply potential or a ground potential by a reverse-biased diode and a resistor, and further passing the transmission line through a ferrite bead are employed.

  In order to solve the above-described problem, Patent Document 1 discloses an output buffer as shown in FIG. The conventional output buffer disclosed in Patent Document 1 will be described below with reference to FIG.

  As shown in FIG. 12, the conventional output buffer 50 includes an enable period adjustment circuit 51 that outputs a plurality of pulse signals in response to rising of an input signal, and a drive pulse output from the enable period adjustment circuit 51. A plurality of output PMOS transistors P1, P2, and P3 that function in response to the signal, an enable period adjustment circuit 52 that outputs a plurality of pulse signals in response to the falling edge of the input signal, and an output from the enable period adjustment circuit 52 A plurality of output NMOS transistors N1, N2 and N3 which function in response to the drive pulse signal to be output, an inverter 53 provided in the input stage of these enable period adjusting circuits 51 and 52, and an output which outputs an output signal waveform b And a pad 54.

  Each of the enable period adjusting circuits 51 and 52 includes means for selecting a driving pulse output to each output transistor.

  The enable period adjusting circuit 51 receives the PMOS transistor pulse width selection signals PPS1 to PPS3 and the pulse delay selection signals PPD1 to PPD3, and selects the selected pulse width and desired one for each of the output PMOS transistors P1, P2 and P3. The drive pulse signals P-out1 to P-out3 having the delay values (delay values) are output.

  The enable period adjusting circuit 52 receives the NMOS transistor pulse width selection signals NPS1 to NPS3 and the pulse delay selection signals NPD1 to NPD3, and selects the selected pulse width and desired one for each of the output NMOS transistors N1, N2 and N3. The drive pulse signals N-out1 to N-out3 having the delay values (delay values) are output.

  FIG. 13 is a block diagram showing a circuit configuration example of the H level side enable period adjusting circuit 51 in the output buffer 50 of FIG.

  As illustrated in FIG. 13, the enable period adjustment circuit 51 includes three series of enable period adjustment circuits 511 to 513 in order to output the drive pulse signals P-out1 to P-out3.

  The enable period adjustment circuit 511 includes a pulse generation circuit that generates a pulse in which the pulse width of the input signal In (input signal waveform a1) from the inverter 53 is changed in a predetermined step from the through (input signal through). A selector (selector) 511a is provided which receives each of the pulse signals S1 to PPS1-1 and selectively outputs one of them based on the PMOS transistor pulse width selection signal PPS1.

  In the enable period adjustment circuit 512, each pulse signal S1 from each pulse generation circuit that generates a pulse in which the pulse width of the input signal In (input signal waveform a1) from the inverter 53 is changed in a predetermined step from through. A selector 512a is provided which receives .about.PPS2-1 as an input and selectively outputs one of them based on the PMOS transistor pulse width selection signal PPS2.

  In the enable period adjustment circuit 513, each pulse signal S1 from each pulse generation circuit that generates a pulse in which the pulse width of the input signal In (input signal waveform a1) from the inverter 53 is varied in a predetermined step from the through. A selector 513a is provided which takes .about.PPS3-1 as an input and selectively outputs one of them based on the PMOS transistor pulse width selection signal PPS3.

  The enable period adjustment circuit 511 is provided with a pulse delay adjustment circuit 511b that delays an input signal having a pulse width selected by the selector 511a. The pulse delay adjustment circuit 511b includes a pulse for a PMOS transistor. The delay-adjusted pulse signal is output as the drive pulse signal P-out1 by the delay selection signal PPD1.

  The enable period adjustment circuit 512 is provided with a pulse delay adjustment circuit 512b that delays an input signal having a pulse width selected by the selector 512a. The pulse delay adjustment circuit 512b receives a PMOS transistor pulse delay selection signal PPD2. The pulse signal after delay adjustment is output as the drive pulse signal P-out2.

  The enable period adjustment circuit 513 is provided with a pulse delay adjustment circuit 513b that delays an input signal having a pulse width selected by the selector 513a. The pulse delay adjustment circuit 513b receives a PMOS transistor pulse delay selection signal PPD3. The pulse signal after delay adjustment is output as the drive pulse signal P-out3.

  14 is a block diagram showing a circuit configuration example of the L level side enable period adjusting circuit 52 in the output buffer 50 of FIG.

  As shown in FIG. 14, the enable period adjustment circuit 52 includes three series of enable period adjustment circuits 521 to 523 in order to output drive pulse signals N-out1 to N-out3.

  In the enable period adjustment circuit 521, each pulse signal S1 from each pulse generation circuit that generates a pulse in which the pulse width of the input signal In (input signal waveform a1) from the inverter 53 is changed in a predetermined step from through. A selector 521a is provided which receives .about.NPS1-1 as an input and selectively outputs one of them based on the NMOS transistor pulse width selection signal NPS1.

  In the enable period adjustment circuit 522, each pulse signal S1 from each pulse generation circuit that generates a pulse in which the pulse width of the input signal In (input signal waveform a1) from the inverter 53 is changed in a predetermined step from through. A selector 522a is provided which receives .about.NPS2-1 as an input and selectively outputs one of them based on the NMOS transistor pulse width selection signal NPS2.

  In the enable period adjustment circuit 523, each pulse signal S1 from each pulse generation circuit that generates a pulse in which the pulse width of the input signal In (input signal waveform a1) from the inverter 53 is varied in a predetermined step from the through. A selector 523a is provided which receives .about.NPS3-1 as an input and selectively outputs one of them based on the NMOS transistor pulse width selection signal NPS3.

  The enable period adjustment circuit 521 is provided with a pulse delay adjustment circuit 521b for delaying an input signal having a pulse width selected by the selector 521a. The pulse delay adjustment circuit 521b receives a pulse delay selection signal for an NMOS transistor. The pulse signal after delay adjustment by NPD1 is output as drive pulse signal N-out1.

  The enable period adjustment circuit 522 is provided with a pulse delay adjustment circuit 522b that delays an input signal having a pulse width selected by the selector 522a. The pulse delay adjustment circuit 522b receives an NMOS transistor pulse delay selection signal NPD2. The pulse signal after delay adjustment is output as the drive pulse signal N-out2.

  The enable period adjustment circuit 523 is provided with a pulse delay adjustment circuit 523b that delays an input signal having a pulse width selected by the selector 523a. The pulse delay adjustment circuit 523b receives an NMOS transistor pulse delay selection signal NPD3. The pulse signal after delay adjustment is output as the drive pulse signal N-out3.

  FIG. 15 is a block diagram showing a circuit configuration example of the pulse delay adjustment circuits 511b to 513b in the H level side enable period adjustment circuit 51 of FIG.

  As shown in FIG. 15, each of the pulse delay adjustment circuits 511b to 513b generates a pulse in which the delay value given to the input signal whose pulse width is selected in the preceding stage is variably adjusted in a predetermined step from the through. Adjustment is made by selecting each delay adjustment pulse generation circuit (each pulse delay circuit).

  The pulse delay adjustment circuit 511b is provided with a selector 511c, and the selector 511c selects one of the pulses D1 to PPD1-1 input from each delay adjustment pulse generation circuit based on the pulse delay selection signal PPD1. Then, the drive pulse signal P-out1 after delay adjustment is output.

  The delay adjustment circuit 512b is provided with a selector 512c. The selector 512c selects and outputs one of the pulses D1 to PPD2-1 input from each delay adjustment pulse generation circuit based on the pulse delay selection signal PPD2. Then, the drive pulse signal P-out2 after delay adjustment is output.

  The delay adjustment circuit 513b is provided with a selector 513c. The selector 513c selects and outputs one of the pulses D1 to PPD3-1 input from each delay adjustment pulse generation circuit based on the pulse delay selection signal PPD3. Then, the drive pulse signal P-out3 after delay adjustment is output.

  FIG. 16 is a block diagram showing a circuit configuration example of the pulse delay adjustment circuits 521b to 523b in the L level enable period adjustment circuit 52 of FIG.

  As shown in FIG. 16, each of the pulse delay adjustment circuits 521b to 523b provides a delay value given to the input signal whose pulse width is selected in the preceding stage, and a pulse that is variably adjusted in a predetermined step from through and through. Adjustment is made by selecting each delay adjustment pulse generation circuit (pulse delay circuit) to be generated.

  The pulse delay adjustment circuit 521b is provided with a selector 521c, and the selector 521c selects one of the pulses D1 to NPD1-1 input from each delay adjustment pulse generation circuit based on the pulse delay selection signal NPD1. The drive pulse signal N-out1 after delay adjustment is output.

  The delay adjustment circuit 522b is provided with a selector 522c. The selector 522c selects and outputs one of the pulses D1 to NPD2-1 input from each delay adjustment pulse generation circuit based on the pulse delay selection signal NPD2. Then, the drive pulse signal N-out2 after delay adjustment is output.

  The delay adjustment circuit 523b is provided with a selector 523c. The selector 523c selectively outputs one of the pulses D1 to NPD3-1 input from the delay adjustment pulse generation circuit based on the pulse delay selection signal NPD3. Then, the drive pulse signal N-out3 after delay adjustment is output.

  Next, an example of the operation of the enable period adjusting circuit 51 will be described with reference to the internal signal timing chart shown in FIG.

  FIG. 17 shows the input signal waveform a to the inverter 53 which is the front stage of the output buffer 50 of FIG. 12, the inverted waveform a1 of the input output from the inverter 53 (input signal through; pulse S1), and the pulse width from through. Output from each pulse generation circuit for generating each pulse S2 to PPS1-1 that is sequentially variable in a predetermined step, and each pulse D2 to PPD1-1 that is sequentially variable in a predetermined step from through The output from each delay adjustment pulse generation circuit (each pulse delay circuit) to be performed and the selector output signal P-out without delay (input signal through; pulse D1) are shown.

  The output pulses S2 to PPS1-1 from the respective pulse generation circuits fall in correspondence with the falling of the input signal waveform a1, and a plurality of pulses S2 to PPS1-1 in which the pulse width (L level) is sequentially changed, respectively. generate. In the selector 511a, the width (change width) of the load condition that the output buffer 50 drives in advance from the pulses S2 to PPS1-1 and the inverted waveform a1 (input signal through; pulse S1) output from the inverter 53. ) Is selected to select a pulse necessary for adjusting the output buffer 50. Further, for example, in the pulse delay adjustment circuit 511b, an output signal (each pulse delay circuit) from each delay adjustment pulse generation circuit (each pulse delay circuit) that generates pulses D2 to PPD1-1 having delay values necessary for adjustment by the selector 511c therein. Pulse D2 to PPD1-1) and selector output signal P-out without delay (input signal through; pulse D1) are selected.

  In the example of FIG. 17, in the enable period adjustment circuit 511 of FIG. 13 that outputs the drive pulse signal P-out1 in the enable period adjustment circuit 51 of FIG. 12, first, the selector 511 a starts from a predetermined pulse generation circuit. The output pulse S4 is selectively output as a selector output signal P-out (pulse width selection signal) shown in FIG. Next, the selector 511c selectively outputs the pulse PPD1-1 output from the predetermined pulse delay circuit as a drive pulse signal P-out1 (pulse delay selection signal) which is a selector output signal shown in FIG.

  In the enable period adjustment circuit 51 of FIG. 13, in addition to the enable period adjustment circuit 511 described above, the enable period adjustment circuits 512 and 513, which are other series, also output the selector output signals in the same manner as described above. As described above, the pulse width selection signal and the pulse delay selection signal can be selectively output to simultaneously drive the buffer PMOS transistors P1 to P3, which are one of the final output stages in the output buffer 50 of FIG.

  On the other hand, the enable period adjustment circuit 52 generates a plurality of pulse signals P2 to NPS1-1 that rise in response to the rise of the input signal waveform a1 (output of the inverter 53) and have their pulse widths changed sequentially. The pulse width selection signal or the pulse delay selection signal is selectively output as each selector output signal by the same operation as the operation example of the enable period adjustment circuit 511, and is the other final output stage in the output buffer 50 of FIG. The NMOS transistors N1 to N3 can be driven simultaneously.

  Here, the output signal waveforms b (1) to b (3) in FIG. 11 will be described. The output signal waveform b (1) is obtained when the output buffer 50 includes the PMOS transistor P1 and the NMOS transistor N1, that is, The characteristics when the PMOS transistors P2 and P3 and the NMOS transistors N2 and N3 are turned off are shown. Further, the output signal waveform b (2) is obtained when the output buffer 50 is composed of PMOS transistors P1 and P2 and NMOS transistors N1 and N2, that is, when the PMOS transistor P3 and the NMOS transistor N3 are turned off. The characteristics are shown. Further, the output signal waveform b (3) shows the characteristics when the output buffer 50 is composed of PMOS transistors P1 to P3 and NMOS transistors N1 to N3.

  In the output signal waveform b (1), the driving capability is low, and the response of the output signal waveform b (1) to the input signal waveform a is delayed. The output signal waveform b (2) is a case where the transistors P2 and N2 are simply added as driving means, and the output signal waveform b (3) is simply added the transistors P2 and P3 and N2 and N3 as driving means. This is the case. In these cases, the drive capability of the output buffer 50 is improved, but undershoot and overshoot occur accordingly.

  FIG. 18 is a graph showing an example of output characteristics in the conventional output buffer 50 shown in FIG. Here, an example is shown in which the drive capability of the transistor is improved and the pulse output is delayed only during a predetermined output period.

  18, PMOS transistors P1 to P3 are operated when the rising edge of the input signal waveform a changes, and NMOS transistors N1 to N3 are operated when the falling edge of the input signal waveform a changes, and the output characteristics of the output buffer 50 shown in FIG. An example shows the output signal waveform b in contrast with the input signal waveform a. In FIG. 18, the drive pulse signal P-out1 (pulse output P-out1) and the drive pulse signal N-out1 (pulses) are selected so that the enable period adjustment circuits 511 and 521 select the through mode (input signal through) without any delay. This shows a case where the output N-out1) is selected and set, and the input signal is directly applied to the PMOS transistor P1 and the NMOS transistor N1.

  The output signal waveform b (4) shown by the solid line in FIG. 18 is obtained when the transmission path is driven by the PMOS transistor P1 and the NMOS transistor N1, that is, the inverted signal a1 of the input signal waveform a is generated in the PMOS transistor P1 and the NMOS transistor N1. The through mode is set, and pulse outputs P-out1 and N-out1 are applied to the gates of the PMOS transistor P1 and the NMOS transistor N1, respectively. The PMOS transistors P2, P3 and the NMOS transistors N2, N3 are set to OFF. The waveforms are shown when the pulse outputs P-out2 and P-out3 are fixed at the H level and the pulse outputs N-out2 and N-out3 are fixed at the L level.

  Further, the output signal waveform b (5) shown by the two-dot chain line in FIG. 18 indicates that the inverted signal a1 of the input signal waveform a is set to the through mode setting in the PMOS transistor P1 and the NMOS transistor N1 as in the output signal waveform b (4). Then, pulse outputs P-out1 and N-out1 are supplied to the gates of the PMOS transistor P1 and the NMOS transistor N1, respectively, and the gates of the PMOS transistors P2, P3 and the NMOS transistors N2, N3 are respectively shown in FIG. 18 shows waveforms when pulse outputs P-out2, P-out3 and pulse outputs N-out2, N-out3 shown in FIG.

  As shown in FIG. 18, in the output signal waveform b (4), the driving capability is low, and the response of the output signal waveform b to the input signal waveform a is delayed. On the other hand, in the output signal waveform b (5), during the period in which the pulse outputs P-out2, P-out3 and the pulse outputs N-out2, N-out3 are generated, the driving force is output signal waveform b (4 ) 3 times higher than As described above, the pulse width selection signals PPS1 to PPS3 and NPS1 to NPS3 input to the enable period adjustment circuits 51 and 52 and the set values of the pulse delay selection signals PPD1 to PPD3 and NPD1 to NPD3 are given, so that the pulse output P -Out1 to P-out3 and pulse outputs N-out1 to N-out3 delay values (indicated by (6) in FIG. 18) and pulse widths (indicated by (7) in FIG. 18) are set, and the output period And the output signal waveform b can be controlled. As a result, it is possible to meet the demand for higher speed operation for the output buffer 50 and to further suppress the occurrence of ringing.

Note that the setting values of the pulse width selection signals PPS1 to PPS3 and NPS1 to NPS3 and the pulse delay selection signals PPD1 to PPD3 and NPD1 to 3 input to the enable period adjustment circuits 51 and 52 are changed after the system startup. Divided into possible ones. The initial set value can be determined based on the result of a simulation performed in advance assuming a load condition. Further, the setting value can be changed after the system is started while observing the actual output signal waveform.
JP 2001-102913 A

  However, the method using the above-described damping resistor, reverse bias, ferrite bead and the like is a coping therapy method and is not a direct measure for eliminating the root cause of ringing. Providing these means increases the cost and mounting area, and is not preferable especially for small consumer devices.

  Further, according to the conventional output buffer 50 disclosed in Patent Document 1, the root cause of the ringing can be eliminated. However, in order to obtain the initial setting value when selecting the driving capability of the output buffer 50, It is necessary to perform a simulation, and it is necessary to change the set value after starting the system while observing the actual output signal waveform. In addition, the drive transistor capacity changes due to device lot-to-lot variations, differences in specifications, etc., and once the set value is determined, it is often not the optimum value. Therefore, it is necessary to change the set value each time. There is.

  The present invention solves the above-mentioned conventional problems, and by changing the driving capability of the driving means in accordance with the presence or absence of ringing in the output signal waveform of the output buffer, the damping resistance, reverse bias, ferrite A slew rate control device capable of preventing ringing and preventing malfunction without using parts such as beads or adjusting the driving ability from the outside, an output buffer using the same, and an information processing device using the slew rate control device The purpose is to provide.

  The slew rate control device according to the present invention includes a detecting means for detecting at least one of an overshoot at the rise of the output signal voltage waveform of the output buffer and an undershoot at the fall of the output signal voltage waveform, Each time the detection means detects the overshoot or undershoot, it has an output drive capacity control means for controlling the output drive capacity of the output buffer drive means to be sequentially reduced up to a predetermined number of times. This achieves the above object.

  Preferably, the detection means in the slew rate control device of the present invention includes reference voltage generation means for generating a reference voltage, and comparison means for comparing the reference voltage with the output signal voltage of the output buffer.

  Further preferably, the output drive capability control means in the slew rate control device of the present invention outputs storage information based on an output signal voltage from the detection means or the comparison means, and output from the storage means Distribution means for outputting the stored information from the output unit. That is, the output drive capability control means in the slew rate control device of the present invention outputs a storage means for outputting one or a plurality of storage information based on an output signal voltage from the detection means or the comparison means, and is output from the storage means. Distribution means for outputting one or more stored information from one or more output units.

  The slew rate control device according to the present invention includes a reference voltage generating means for generating a reference voltage, a comparing means for comparing the reference voltage with an output signal voltage of the output buffer, and stored information based on the output signal voltage from the comparing means. Storage means for outputting the information, and distribution means for outputting the storage information output from the storage means from the output unit, whereby the above object is achieved. That is, the slew rate control device according to the present invention is based on the reference voltage generating means for generating the reference voltage, the comparing means for comparing the reference voltage with the output signal voltage of the output buffer, and the output signal voltage from the comparing means. Storage means for outputting one or a plurality of storage information, and a distribution means for outputting one or a plurality of storage information output from the storage means from one or a plurality of output units, whereby the object Is achieved.

Preferably, the reference voltage generating means in the slew rate control device of the present invention is a reference voltage generator that generates a voltage higher than a power supply voltage by a predetermined voltage as the reference voltage,
The comparison means is composed of a differential amplifier, the output terminal of the output buffer is connected to the positive phase input terminal, the output terminal of the reference voltage generator is connected to the negative phase input terminal, and the output signal of the output buffer When the voltage exceeds the reference voltage, an output signal voltage is output.

  Further preferably, the reference voltage generating means in the slew rate control device of the present invention is a reference voltage generator that generates a voltage lower than a ground voltage (or power supply voltage) by a predetermined voltage as the reference voltage, and the comparing means Is constituted by a differential amplifier, the output terminal of the reference voltage generator is connected to the positive phase input terminal, the output terminal of the output buffer is connected to the negative phase input terminal, and the output signal voltage of the output buffer is Output signal voltage is output when the voltage falls below the reference voltage.

  Further preferably, the storage means in the slew rate control device of the present invention comprises a shift register, and an output terminal of the output signal voltage of the comparison means is connected to a clock input terminal of the shift register, and the clock from the comparison means A plurality of storage information shifted each time a high level signal is input to the input terminal is output from a plurality of output units of the shift register. In this shift register, the output terminal of the power supply voltage is connected to the data input terminal, and the shift operation of the plurality of stored information is performed for each clock input.

  Further preferably, the distribution means in the slew rate control device of the present invention comprises a demultiplexer, and when the input signal voltage is at a predetermined level, a plurality of storage information inputted from the storage means are respectively supplied to a plurality of output sections. Each is output as a plurality of drive signals.

  An output buffer according to the present invention includes the slew rate control device according to any one of claims 1 to 9 and drive means for outputting an output signal voltage based on a plurality of drive signals output from the slew rate control device. And the above object is achieved.

  Preferably, the driving means in the output buffer of the present invention is a plurality of driving transistors.

  6. The slew rate control device according to claim 5, wherein the output buffer of the present invention is capable of outputting a high level side drive signal when the input signal voltage rises, and can output a low level side drive signal when the input signal voltage falls. 7. The slew rate control device according to claim 6, high-level drive means for outputting a high-level output signal voltage based on the high-level drive signal, and a low-level output signal based on the low-level drive signal Low-level side driving means for outputting a voltage, thereby achieving the above object.

  Further preferably, the high level side driving means and the low level side driving means in the output buffer of the present invention are each a plurality of driving transistors.

  Further preferably, in the output buffer of the present invention, the high level side driving means is a plurality of PMOS transistors, and the low level side driving means is a plurality of NMOS transistors.

  Furthermore, preferably, in the output buffer of the present invention, a pre-buffer is further provided in front of the slew rate control device according to any one of claims 1 to 9.

  Furthermore, it is preferable that the output buffer of the present invention further includes a pre-buffer before the slew rate control device according to claim 5 and the slew rate control device according to claim 6.

  An information processing apparatus according to the present invention performs information processing using the output buffer according to any one of claims 10 to 16, and thereby achieves the above object.

  The operation of the present invention will be described below with the above configuration.

  The slew rate control device of the present invention includes a reference voltage generating means, a comparing means in which one of the reference voltage generating means and the output terminal from the output buffer is connected to the positive phase input, and the other is connected to the negative phase input. And a storage means to which the output terminal of the comparison means is connected, and a distribution means for distributing and outputting the drive signal to the drive means based on the storage information of the storage means.

  The comparison means is composed of, for example, a differential amplifier, and compares the output signal voltage from the output buffer with the reference voltage and outputs the comparison result to the storage means. For example, when a reference voltage generator that generates a voltage higher than the power supply voltage by a predetermined voltage is used as the reference voltage generating means, the output terminal from the output buffer is connected to the positive phase input terminal of the differential amplifier, and the negative phase input terminal A reference voltage generator is connected to the output amplifier so that the output signal voltage is output from the differential amplifier when the output signal voltage of the output buffer exceeds the reference voltage of the reference voltage generating means. Or / and when a reference voltage generator that generates a voltage lower than the ground voltage by a predetermined voltage is used as the reference voltage generating means, the reference voltage generator is connected to the positive phase input terminal of the differential amplifier, and the negative phase input terminal The output terminal of the output buffer is connected to the output buffer so that the output signal voltage is output from the differential amplifier when the output voltage of the output buffer falls below the reference voltage of the reference voltage generating means. As a result, the presence or absence of ringing in the output signal waveform from the output buffer can be detected.

  The storage means comprises a shift register or the like, and the comparison result output terminal of the comparison means is connected to the clock input terminal of this shift register. A plurality of storage information is stored in the shift register, and the plurality of storage information shifted each time a high level signal is input from the comparison means to the clock input terminal is respectively sent to a plurality of output units of the shift register. .

  A plurality of output signals from the storage means are input to a distribution means such as a demultiplexer, and the distribution means receives a plurality of pieces of storage information input from the storage means when the input signal voltage is at a predetermined level. It distributes to the output part and outputs each as a plurality of drive signals.

  As a result, the output buffer of the present invention detects the presence or absence of ringing in the output signal waveform, and uses a slew rate control device that reduces and controls the drive capability of the drive unit according to this, as in the past, Without using components such as a damping resistor, reverse bias, ferrite bead, etc., or adjusting the driving ability from the outside, a stable output signal waveform can be obtained by suppressing ringing, and malfunction can be prevented.

  According to the slew rate control device of the present invention and the output buffer of the present invention using the slew rate control device, it is not necessary to adjust the driving capability from the outside, and the presence or absence of ringing in the output signal waveform of the output buffer is detected by the comparison means. Accordingly, the ringing can be suppressed by changing (reducing) the drive capability of the drive means accordingly. In this case, unlike the patent document 1, it is not necessary for the user who uses the device to change the set value, and a suitable data transmission waveform can be obtained in real time. Further, EMI can be improved without using components such as a damping resistor, a reverse bias, and a ferrite bead, which is advantageous in terms of manufacturing cost and mounting area.

  Further, as described above, the information processing apparatus including the output buffer according to the present invention does not cause malfunction due to ringing of the output buffer, and is excellent in operation stability. In addition, EMI can contribute to the stability of the system without causing malfunction to other peripheral circuits and other devices.

  Embodiments of a slew rate control device, an output buffer using the slew rate control device, and an information processing device using the slew rate control device according to the invention will be described below with reference to the drawings.

  FIG. 1 is a block diagram showing a basic configuration in an embodiment of the slew rate control apparatus of the present invention.

  The slew rate control device 10 shown in FIG. 1 has a reference voltage generating means 11 for generating a reference voltage, and either an output terminal of the reference voltage generating means 11 or an output terminal from an output buffer is connected to a positive phase input. The other means connected to the opposite phase input, the storage means 13 connected to the output terminal of the comparison means 12, and a plurality of stored information from the storage means 13 as a plurality of drive signals as drive means. And distributing means 14 for outputting to each of them. The reference voltage generation means 11 and the comparison means 12 constitute detection means. The detection means is an overshoot at the rise of an output signal voltage waveform of an output buffer, which will be described later, and at the fall of the output signal voltage waveform. Detect at least one of the undershooted voltages. The storage means 13 and the distribution means 14 constitute an output drive capacity control means. The output drive capacity control means is an output buffer drive means described later each time the detection means detects overshoot or undershoot. The output drive capability is controlled so as to be sequentially reduced to a predetermined number n.

  The comparison means 12 compares an output signal voltage from the output buffer of the present invention, which will be described later, with a reference voltage generated by the reference voltage generation means 11 and outputs the comparison result to the storage means 13.

  The storage unit 13 outputs a plurality of output signals (stored information) corresponding to the input comparison results to the distribution unit 14.

  The distribution unit 14 distributes a plurality of pieces of storage information from the storage unit 13 to the output units (dr0 to dr2) of the distribution unit 14 as a plurality of drive signals, respectively, and outputs them.

  FIG. 2 is a block diagram showing a basic configuration in an embodiment of an output buffer using the slew rate control device 10 of FIG.

  As shown in FIG. 2, the output buffer 20 includes a pre-buffer 21 having an inverter for inverting and outputting input signal data, and an H level side driving means 22a having H level side driving PMOS transistors P0, P1, P2, and P3. The H level side slew rate control device 10a for controlling the H level side driving PMOS transistors P0 to P3 when the input signal rises, and the L level side driving means having the L level side driving NMOS transistors N0, N1, N2 and N3. 22b, an L-level side slew rate control device 10b for controlling the L-level side driving NMOS transistors N0 to N3 when the input signal falls, and an output pad 23 for outputting an output signal of the output buffer 20.

  FIG. 3 is a block diagram showing a detailed configuration of the H level slew rate control device 10a in FIG. 2, and FIG. 4 is a block diagram showing a detailed configuration of the L level slew rate control device 10b in FIG.

  As shown in FIG. 3, the H level slew rate control device 10a compares a reference voltage generator 11a as a reference voltage generating means for generating a voltage Vcc + ΔV higher than the power supply voltage Vcc and a difference amplifier as a comparing means. And a demultiplexer 14a as distribution means.

  The signal output terminal from the output buffer 20 is connected to the positive phase input (+) of the comparator 12a, and the voltage output terminal of the reference voltage generator 11a is connected to the negative phase input (−). When the output voltage exceeds the reference voltage from the reference voltage generator 11a, an H level pulse signal is output from the comparator 12a.

  Predetermined storage information (H level) is stored in the shift register 13a, and the signal output terminal of the comparator 12a is connected to the clock input terminal CLK. Every time a clock is input to the clock input terminal CLK, the shift register 13a The stored information is sequentially shifted and sent to a plurality of output units Q0 to Q2 of 13a. Note that an output terminal of the power supply voltage Vcc is connected to the data input terminal of the shift register 13a, and a reset signal output terminal is connected to the RST input terminal.

  The demultiplexer 14a has three NAND gates, and the drive signal H-drive (the output signal of the prebuffer 21 in FIG. 2) is inverted and input to one input terminal of each NAND gate. Output signals from the plurality of output units Q0 to Q2 of the shift register 13a are inverted and input to the other input terminal of each NAND gate. In the demultiplexer 14a, when the drive signal H-drive is at a predetermined level (L level), the drive signal is output to the output units drh0 to drh2 of the respective NAND gates based on each storage information input from the shift register 13a. Output to be distributed.

  As shown in FIG. 4, the L level slew rate control device 10b includes a reference voltage generator 11b as a reference voltage generating means for generating a voltage Vss−ΔV lower than the ground voltage (or power supply voltage) Vss, and a comparing means. A comparator 12b such as a differential amplifier, a shift register 13b as storage means, and a demultiplexer 14b as distribution means.

  In the comparator 12b, the reference voltage generator 11b is connected to the positive phase input (+), the signal output terminal from the output buffer 20 is connected to the negative phase input (−), and the output voltage of the output buffer 20 is When the voltage falls below the reference voltage of the reference voltage generator 11b, an H level pulse signal is output from the output terminal of the comparator 12b.

  Predetermined storage information (H level) is stored in the shift register 13b, the signal output terminal of the comparator 12b is connected to the clock input terminal CLK, and an H level pulse signal is output from the comparator 12b to the clock input terminal CLK. Each time it is input, the stored information is sequentially sent to the plurality of output units Q0 to Q2 of the shift register 13b. In addition, the output terminal of the power supply voltage Vcc is connected to the data input terminal of the shift register 13b, and the reset signal output terminal is connected to the RST input terminal.

  The demultiplexer 14b has three AND gates, and a drive signal L-drive (an output signal of the pre-buffer 21 in FIG. 2) is input to one input terminal of each AND gate. Output signals from the plurality of output units Q0 to Q2 of the shift register 13b are respectively inverted and input to the other input terminal. In the demultiplexer 14b, when the drive signal L-drive (the output signal of the pre-buffer 21 in FIG. 2) is at a predetermined level (H level), the drive signal is received based on the storage information input from the shift register 13b. The output is distributed to the output parts drl0 to drl2 of the AND gate.

  Next, an operation example of the H level slew rate control device 10a of FIG. 3 will be described based on an internal timing chart shown in FIG. FIG. 5 shows a clock signal CLK, data D (H level power supply voltage Vcc) input to the shift register 13a, output signals Q0 to Q2 from the shift register 13a, and output signals drh0 to drh2 from the demultiplexer 14a. It is shown.

  As shown in FIGS. 3 and 5, first, prior to the operation of the H level slew rate control device 10a, the reset signal reset is input to the reset input terminal RST of the shift register 13a. As a result, all of the three output units (the output terminals of the output signals Q0 to Q2) of the shift register 13a are reset to the L level. As the reset signal reset, a system reset signal input from the outside of the device can be used. Alternatively, a reset circuit that operates by detecting that power is supplied to the chip (IC chip) may be provided, and the output signal thereof may be used as the reset signal reset.

  Next, the signal output terminal of the output buffer 20 is connected to the positive phase input terminal of the comparator 12a, and the reference voltage generator 11a that generates a voltage higher than the power supply voltage is connected to the negative phase input terminal. The comparator 12a compares the input voltages of these two systems. When the output voltage from the output buffer 20 applied to the positive phase input terminal of the comparator 12a exceeds the reference voltage of the reference voltage generator 11a, the comparator 12a sends an H level shift pulse to the clock input of the shift register 13a. Apply to terminal CLK.

  Further, the H level power supply voltage Vcc is applied to the shift register 13a, and 1-bit H level information is sequentially stored in the shift register 13a. Therefore, when a shift pulse is applied to the clock input terminal CLK. In addition, an H level signal is output from the output section of the shift register 13a (output terminal of the output signal Q0), and an L level signal is output from the other output sections (output terminals of the output signals Q1 and Q2). The Similarly, after that, the output voltage of the output buffer 20 applied to the positive phase input terminal of the comparator 12a exceeds the reference voltage of the reference voltage generator 11a, and the H level shift pulse becomes the clock of the shift register 13a. Each time it is applied to the input terminal CLK, H level information is sequentially sent to the three output sections of the shift register 13a. Therefore, as shown in the timing chart of FIG. 5, every time a shift pulse from the comparator 12a is input to the clock input terminal CLK, output signals (output signals Q0 to Q2 of the output signals Q0 to Q2) from the three output units of the shift register 13a. Each output terminal) is “L”, “L” and “L” → “H”, “L” and “L” → “H”, “H” and “L” → “H”, “H” and It changes in order as “H”.

  When the input signal (H-drive) from the pre-buffer 21 to the demultiplexer 14a is at L level (when the input signal to the pre-buffer 21 is at H level), the outputs drh0 to drh2 from the demultiplexer 14a are lower (drh0). ) Are sequentially fixed to H level, and “L”, “L” and “L” → “H”, “L” and “L” → “H”, “H” and “L” → “H”, “H” and “H” are sequentially changed.

  Next, an operation example of the L-level slew rate control device 10b in FIG. 4 will be described based on the internal timing chart shown in FIG. FIG. 6 shows a clock signal CLK, data D (H level power supply voltage Vcc) input to the shift register 13b, output signals Q0 to Q2 from the shift register 13b, and output signals dr10 to drl2 from the demultiplexer 14b. Has been.

  As shown in FIGS. 4 and 6, first, prior to the operation of the L level slew rate control device 10b, the reset signal reset is input to the reset input terminal RST of the shift register 13b. As a result, all the output units of the shift register 13b (the output terminals of the output signals Q0 to Q2) are all reset to the L level.

  Next, the output voltage terminal of the reference voltage generator 11b that generates a voltage lower than the ground voltage is connected to the positive phase input terminal of the comparator 12b, and the signal output terminal of the output buffer 20 is connected to the negative phase input terminal. The comparator 12b compares these two systems of input voltages. When the output voltage of the output buffer 20 applied to the negative phase input terminal of the comparator 12b falls below the reference voltage of the reference voltage generator 11b, the comparator 12b sends an H level shift pulse from the output terminal of the shift register 13b. Apply to clock input terminal CLK.

  Further, the H level power supply voltage Vcc is applied to the shift register 13b, and 1-bit H level information is sequentially stored in the shift register 13b, so that the shift pulse from the comparator 12b is transferred to the clock input terminal CLK. Is applied to the output of the shift register 13b (output terminal of the output signal Q0), and an H level signal is output from the other output of the shift register 13b (output terminals of the output signals Q1 and Q2). Outputs an L level signal. Similarly, after that, the output voltage of the output buffer 20 applied to the negative phase input terminal of the comparator 12b is lower than the reference voltage of the reference voltage generator 11b, and the H level shift pulse becomes the clock of the shift register 13b. Each time it is applied to the input terminal CLK, H level information is sequentially sent to each output section (each output terminal of the output signals Q0 to Q2) of the shift register 13b. Therefore, as shown in the timing chart of FIG. 6, every time a shift pulse is input to the clock input terminal CLK, the output signals Q0 to Q2 from the shift register 13b are “L”, “L” and “L” → “H”, “L” and “L” → “H”, “H” and “L” → “H”, “H” and “H” are sequentially changed.

  When the input signal (L-drive) from the pre-buffer 21 to the demultiplexer 14b is at H level (when the input signal to the pre-buffer 21 is at L level), the outputs drl0 to drl2 from the demultiplexer 14b are lower (drl0) ) Are sequentially fixed to L level, and “H”, “H” and “H” → “L”, “H” and “H” → “L”, “L” and “H” → “L”, respectively. “L” and “L” are sequentially changed.

  Next, an operation example of the output buffer 20 shown in FIG. 2 according to the present embodiment will be described with reference to a timing chart shown in FIG. FIG. 7 shows the input signal DATA input to the prebuffer 21, the drive signal H-drive (L-drive) inverted from the prebuffer 21, the reference voltage Vcc + ΔV generated by the reference voltage generator 11a, and the output pad. 23, the output voltage of the output buffer 20, the reference voltage Vss-ΔV generated by the reference voltage generator 11b, the output signal of the comparator 12a, the output signals Q0 to Q2 from the shift register 13a, the demultiplexer 14a Output signals drh0 to drh2, the output signal of the comparator 12b, the output signals Q0 to Q2 from the shift register 13b, and the output signals dr10 to drl2 of the demultiplexer 14b are shown. In the example of FIG. 7, the PMOS transistors P1 to P3 are operated when the rising edge of the input signal DATA is changed, and the NMOS transistors N1 to N3 are operated when the falling edge is changed.

  Prior to the operation of the output buffer 20 of FIG. 2, both the shift registers 13a and 13b are reset by a reset signal reset from a reset circuit (not shown), and the output signals Q0 to Q2 are all set to the L level.

  First, the rise time of the input signal DATA (H level side slew rate control device 10a) will be described.

  When the input signal DATA to the prebuffer 21 rises to H level at time t0 in FIG. 7, the drive signal H-drive (L-drive) output from the prebuffer 21 is inverted and falls to L level. At the same time, in the H level side driving means 22a, the gate voltage of the H level side driving PMOS transistor P3 becomes L level, the PMOS transistor P3 is turned on, and all the outputs drh0 to drh2 of the demultiplexer 14a are all. Becomes L level. As a result, the gate voltages of the PMOS transistors PO to P2 also become L level, and the PMOS transistors PO to P2 are all turned on. As a result, the output signal b from the output pad 23 starts to change to the H level.

  At time t1, when ringing as shown by a solid line in FIG. 7 occurs in the output signal of the output pad 23 and exceeds the reference voltage Vcc + ΔV, the output signal of the comparator 12a becomes H level, and the shift register 13a The output signal Q0 becomes H level, and the output signal drh0 of the demultiplexer 14a also becomes H level. As a result, in the H level side driving means 22a, the PMOS transistor P0 is turned off among the H level side driving PMOS transistors P0 to P3, and the driving capability of the H level side driving PMOS transistor group is reduced and output. The output signal from the pad 23 is braked. As a result, the ringing of the output signal waveform b is gently improved as shown by the dotted line in FIG. If the braking effect on the output signal output from the output pad 23 is not sufficient and ringing occurs again, the output signals drh0 to drh2 of the demultiplexer 14a are “L”, “L” and “L”. → “H”, “L” and “L” → “H”, “H” and “L” → “H”, “H” and “H” in order, and the H level side driving PMOS step by step Control for reducing the driving capability of the transistor is performed to suppress ringing of the output signal waveform b.

  Next, a description will be given of the time when the input signal DATA falls (L level side slew rate control device 10b).

  At time t2 in FIG. 7, when the input signal DATA to the prebuffer 21 falls to the L level, the drive signal L-drive (H-drive) output from the prebuffer 21 rises to the H level. At the same time, in the L level side driving means 22b, the gate voltage of the L level side driving NMOS transistor N3 becomes H level, the NMOS transistor N3 is turned on, and all the output signals dr10 to drl2 of the demultiplexer 14b are supplied. Become H level. As a result, the gate voltages of the NMOS transistors N0 to N2 also become H level, and the NMOS transistors N0 to N2 are all turned on. As a result, the output signal waveform b (output of the output pad 23) of the output buffer 20 output from the output pad 23 starts to change to the L level.

  Further, when ringing as shown by a solid line in FIG. 7 occurs at the output of the output pad 23 at time t3 and falls below the reference voltage Vss−ΔV, the output signal of the comparator 12b becomes H level, and the shift register The output signal Q0 of 13b becomes H level, and the output signal dr10 of the demultiplexer 14b becomes L level. As a result, in the L level side driving means 22b, the NMOS transistor N0 is turned off among the L level side driving NMOS transistors N0 to N3, and the driving capability of the L level side driving NMOS transistor group is reduced and output. Braking is applied to the output of the pad 23 (the output signal waveform b of the output buffer 20). As a result, the ringing of the output signal waveform is gently improved as shown by the dotted line in FIG. If the braking effect on the output from the output pad 23 is not sufficient and ringing occurs again, the outputs drl0 to drl2 of the demultiplexer 14b are “H”, “H” and “H” → “L”. , “H” and “H” → “L”, “L” and “H” → “L”, “L” and “L” are sequentially changed, and the L-level side driving NMOS transistor group is driven step by step. Control is performed to reduce the ability.

  Next, an embodiment of the information processing apparatus of the present invention will be described.

  FIG. 8 is a block diagram showing a basic configuration in the embodiment of the information processing apparatus of the present invention using the output buffer of the present invention.

  As shown in FIG. 8, the information processing apparatus 30 includes a CPU 31 (central processing unit) as a control means, a 64M bit flash memory 32, a 16M bit SRAM 33, and an output port 34 as an 8 bit parallel port. Each of which is provided with the output buffer of the present invention (for example, the output buffer 20 of FIG. 2).

  In this embodiment, the memory space of the CPU 31 is 16 Mbytes, and the bus width is 16 bits.

  FIG. 9 shows an example of memory space mapping in the CPU 31 using hexadecimal numbers. In FIG. 9, 16M bit SRAM 33 is arranged in 2M bytes of 000000H to 1FFFFFFH in the memory space, and 64M bit flash memory 32 is arranged in 8M bytes of 800000H to FFFFFFH. Further, the 8-bit parallel port 34 is arranged in the lower byte (in the case of little endian) 0H of the I / O space.

  In the information processing apparatus 30 shown in FIG. 8, the CPU 31 receives an address selection signal A0 to A23, a memory read signal OE #, a memory write signal WE #, an I / O read signal IOR #, and an I / O write signal. IOW # and memory space / I / O space identification signal M / I / O # are output. The data signals D0 to D15 are output signals when viewed from the CPU 31 when the CPU 31 writes to the 64M bit flash memory 32 or the like, and when the CPU 31 reads from the 64M bit flash memory 32 or the like, the CPU 31 From the input signal. The CPU 31 reads and executes instructions by appropriately controlling these signals, and takes in data (for example, sensor output) from the outside by processing data on the memory and inputting I / O signals. The motor is controlled by ON / OFF.

  In the information processing apparatus 30 of this embodiment, control signals (address selection signals A0 to A23, a memory read signal OE #, a memory write signal WE #, an I / O read signal IOR #, and an I / O write signal output from the CPU 31. For example, the output buffer 20 shown in FIG. 2 can be applied as an output buffer inside the CPU 31 that outputs (IOW #, memory space / I / O space identification signal M / IO #).

  The data signals D0 to D7 are input signals for the output signals to the 8-bit parallel port 34 and others, and the data signals D8 to D15 are input / output signals of the CPU 31, the 64M bit flash memory 32 and the 16M bit SRAM 33. In the CPU 31, 64M bit flash memory 32 and 16M bit SRAM 33, input / output buffers for inputting / outputting data signals D0 to D15 are provided. As this input / output buffer, for example, the output buffer 20 shown in FIG. 2 cannot be used as it is.

  Therefore, an output identification signal OE # indicating that the data signals D0 to D15 are input signals when viewed from the CPU 31, and an inverted OE signal of the memory read signal OE # input from the CPU 31 in the 64-bit flash memory 32 and the 16M bit SRAM 33. (In the 64 Mbit flash memory 32 and the 16 Mbit SRAM 33, this signal is added to OE # in FIG. 10), for example, to satisfy the following logical expressions (1) and (2) and the truth table shown in Table 1 below. 2 is provided in place of the prebuffer 21 in the output buffer 20 shown in FIG. 2, the output buffer 20 shown in FIG. 2 can function as an input / output buffer, thereby improving the ringing effect. It is possible to obtain Note that the output identification signal OE # indicating that the data signals D0 to D15 are input signals when viewed from the CPU 31 are different from the memory read signal OE # output from the CPU 31 to the outside, and are originally distinguished from each other. However, in the present embodiment, in the following logical formula and the truth table shown in Table 1 below, the same signal name is used for convenience of explanation.

図１０に示すプリバッファ２１ａは、ＮＡＮＤゲートとＮＯＲゲートとを有している。ＮＡＮＤゲートの一方の入力端にはそれぞれデータ信号ＤＡＴＡが接続され、他方の入力には出力識別信号ＯＥ＃（またはメモリ読み出し信号）が接続されており、駆動信号Ｈ−ｄｒｉｖｅが出力される。また、ＮＯＲゲートの一方の入力端にはデータ信号ＤＡＴＡが接続され、他方の入力端には出力識別信号ＯＥ＃（またはメモリ読み出し信号）が反転されて接続されており、駆動信号Ｌ−ｄｒｉｖｅが出力される。

The pre-buffer 21a shown in FIG. 10 has a NAND gate and a NOR gate. The data signal DATA is connected to one input terminal of the NAND gate, and the output identification signal OE # (or memory read signal) is connected to the other input, and the drive signal H-drive is output. Further, the data signal DATA is connected to one input terminal of the NOR gate, the output identification signal OE # (or the memory read signal) is inverted and connected to the other input terminal, and the drive signal L-drive is supplied. Is output.

  As shown in Table 1, when the output identification signal OE # (or memory read signal) is at the H level and the data signal DATA is at the H level, the drive signals H-drive and L- output from the pre-buffer 21a. drive becomes L level. When the output identification signal OE # (or the memory read signal) is at the H level and the data signal DATA is at the L level, the drive signals H-drive and L-drive output from the prebuffer 21a are at the H level. . In these cases, in the output buffer provided with the prebuffer 21a instead of the prebuffer 21 shown in FIG. 2, the PMOS transistors P0 to P3 are driven when the H-drive is at the L level, and the L-drive is at the H level. NMOS transistors N0 to N3 are driven to function as an output buffer.

  Further, when the output identification signal OE # (or the memory read signal) is at the L level, the drive signal H− output from the pre-buffer 21a regardless of whether the data signal DATA is at the H level or the L level. The drive becomes H level, and the drive signal L-drive becomes L level. In these cases, the output buffer provided with the prebuffer 21a instead of the prebuffer 21 shown in FIG. 2 does not drive all the driving transistors, that is, the PMOS transistors P0 to P3 and the NMOS transistors N0 to N3 are both driven. Instead, it functions as an input buffer.

  As described above, according to the present embodiment, when ringing occurs at the rise and fall of the output signal waveform b from the output buffer 20, this is detected and the H level side slew rate control device 10a and the L level side are detected. In accordance with the drive signal from the slew rate control device 10b, the drive capability of the PMOS transistor group of the H level side drive means 22a and the NMOS transistor group of the L level side drive means 22b are controlled stepwise. As a result, there is no need to use components such as a damping resistor, reverse bias, and ferrite bead as in the prior art, and no adjustment of the driving capability from the outside, and the presence or absence of ringing in the output signal waveform b of the output buffer 20 Can be detected, and the drive capability of the drive means can be changed accordingly to prevent malfunction.

  In the above embodiment, the comparators (difference amplifiers) 12a and 12b are used as the comparison means 12 used in the slew rate control device 10, but other differential amplifiers are used instead of the comparators 12a and 12b. Also good. Further, as the H level side driving transistors P0 to P3 and the L level side driving transistors N0 to N3, which are driving means used in the output buffer 20, respectively, PMOS transistors and NMOS transistors are used, but the demultiplexers 14a and 14b By appropriately selecting the logic, all the drive transistors can be of the same conductivity type. The drive transistor may be related to a bipolar and Bi-CMIS process. The output form from the output buffer 20 need not be a drive transistor alone, but may be a drive transistor + load resistor, an open drain (open collector), a totem pole, or the like. Further, the slew rate control device 10 of the present invention may be provided in only one of the H level side driving means and the L level side driving means. Furthermore, in the present embodiment, the number of output bits of the shift registers 13a and 13b is set to “3”, but is not limited to this, and other factors such as chip layout and controllability are taken into consideration. It is also possible to change appropriately.

  As mentioned above, although this invention has been illustrated using preferable embodiment of this invention, this invention should not be limited and limited to this embodiment. It is understood that the scope of the present invention should be construed only by the claims. It is understood that those skilled in the art can implement an equivalent range based on the description of the present invention and the common general technical knowledge from the description of specific preferred embodiments of the present invention. Patents, patent applications, and documents cited herein should be incorporated by reference in their entirety, as if the contents themselves were specifically described herein. Understood.

  The present invention relates to a slew rate control device applicable to, for example, a semiconductor integrated circuit, an output buffer using the slew rate control device, and an information processing device using the output buffer. It is possible to detect the presence or absence of ringing in the output signal waveform of the output buffer without adjusting the setting value or by the user who uses the device, and adjust the driving capability of the driving means based on this. A data transmission waveform can be obtained. Further, EMI can be improved and malfunction of the information processing apparatus can be prevented without using components such as a damping resistor, a reverse bias, and a ferrite bead as in the prior art. By applying the present invention, it is possible to construct an information processing system excellent in operational stability.

It is a block diagram which shows the basic composition in one Embodiment of the slew rate control apparatus of this invention. It is a block diagram which shows the basic composition in embodiment of the output buffer using the slew rate control apparatus of FIG. FIG. 3 is a block diagram showing a detailed configuration of the H level side slew rate control device of FIG. 2. FIG. 3 is a block diagram showing a detailed configuration of the L level side slew rate control device of FIG. 2. FIG. 4 is a timing chart showing each signal during operation of the H level side slew rate control device of FIG. 3. FIG. 5 is a timing chart showing each signal during operation of the L-level slew rate control device of FIG. 4. FIG. 3 is a timing chart showing each signal during operation of the output buffer of FIG. 2. It is a block diagram which shows the basic composition in embodiment of the information processing apparatus of this invention using the output buffer of this invention. FIG. 9 is a mapping diagram of a memory space in the information processing apparatus of FIG. 8. FIG. 9 is a circuit diagram illustrating a schematic configuration of a prebuffer provided in an input / output buffer in the information processing apparatus of FIG. 8. It is a wave form diagram which shows the input signal waveform and output signal waveform in the conventional output buffer. It is a block diagram which shows the schematic structure of the conventional output buffer. FIG. 13 is a block diagram illustrating a circuit configuration example of an H level side enable period adjusting circuit in the output buffer of FIG. 12. FIG. 13 is a block diagram illustrating a circuit configuration example of an L level enable period adjustment circuit in the output buffer of FIG. 12. FIG. 14 is a block diagram illustrating a circuit configuration example of a pulse delay adjustment circuit in the H level side enable period adjustment circuit of FIG. 13. FIG. 15 is a block diagram illustrating a circuit configuration example of a pulse delay adjustment circuit in the L level enable period adjustment circuit of FIG. 14. 14 is a timing chart of internal signals showing an example of operation in the enable period adjustment circuit of FIG. 13. It is a graph which shows an example of the output characteristic in the conventional output buffer shown in FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Slew rate control apparatus 10a H level side slew rate control apparatus 10b L level side slew rate control apparatus 11 Reference voltage generation means 11a, 11b Reference voltage generator 12 Comparison means 12a, 12b Comparator 13 Storage means 13a, 13b Shift register 14 Distributing means 14a, 14b Demultiplexer 20 Output buffer 21, 21a Pre-buffer 22a H level side driving means 22b L level side driving means 23 Output pad 30 Information processing device 31 CPU
32 64Mbit flash memory 33 16Mbit SRAM
34 8-bit parallel port P0, P1, P2, P3 H level side driving PMOS transistor N0, N1, N2, N3 L level side driving NMOS transistor

Claims (17)

Detecting means for detecting at least one of overshoot at the rise of the output signal voltage waveform of the output buffer and undershoot at the fall of the output signal voltage waveform;
A slew rate control device comprising output drive capability control means for controlling the output drive capability of the output buffer drive means to be sequentially reduced to a predetermined number of times each time the detection means detects the overshoot or undershoot. The detection means includes
A reference voltage generating means for generating a reference voltage;
2. The slew rate control device according to claim 1, further comprising comparison means for comparing the reference voltage with the output signal voltage of the output buffer. The output drive capability control means includes
Storage means for outputting storage information based on an output signal voltage from the detection means or comparison means;
The slew rate control apparatus according to claim 1, further comprising a distribution unit that outputs the storage information output from the storage unit from an output unit. A reference voltage generating means for generating a reference voltage;
Comparing means for comparing the reference voltage with the output signal voltage of the output buffer;
Storage means for outputting storage information based on the output signal voltage from the comparison means;
A slew rate control apparatus comprising: distribution means for outputting storage information output from the storage means from an output unit. The reference voltage generating means is a reference voltage generator that generates a voltage higher than a power supply voltage by a predetermined voltage as the reference voltage,
The comparison means is composed of a differential amplifier, the output terminal of the output buffer is connected to the positive phase input terminal, the output terminal of the reference voltage generator is connected to the negative phase input terminal, and the output signal of the output buffer 5. The slew rate control device according to claim 2, wherein an output signal voltage is output when the voltage exceeds the reference voltage. The reference voltage generating means is a reference voltage generator that generates a voltage lower than a ground voltage by a predetermined voltage as the reference voltage.
The comparison means comprises a differential amplifier, the output terminal of the reference buffer is connected to the positive phase input terminal, the output terminal of the output buffer is connected to the negative phase input terminal, and the output signal of the output buffer The slew rate control device according to claim 2 or 4, wherein an output signal voltage is output when the voltage falls below the reference voltage.   The storage means is composed of a shift register, and an output signal voltage output terminal of the comparison means is connected to a clock input terminal of the shift register, and a high level signal is input from the comparison means to the clock input terminal. The slew rate control device according to any one of claims 3 to 6, wherein the plurality of shifted storage information are respectively output from the plurality of output units of the shift register.   8. The slew rate control device according to claim 7, wherein the shift register has a data input terminal connected to an output terminal of a power supply voltage, and performs a shift operation of the plurality of stored information for each clock input.   The distribution means is composed of a demultiplexer, and outputs a plurality of storage information inputted from the storage means to a plurality of output sections as a plurality of drive signals, respectively, when an input signal voltage is at a predetermined level. The slew rate control device according to claim 7.   10. An output buffer comprising: the slew rate control device according to claim 1; and a drive unit that outputs an output signal voltage based on a plurality of drive signals output from the slew rate control device.   The output buffer according to claim 10, wherein the driving unit is a plurality of driving transistors.   7. The slew rate control device according to claim 5, wherein a high-level drive signal can be output when the input signal voltage rises, and a low-level drive signal can be output when the input signal voltage falls. A slew rate control device; high-level drive means for outputting a high-level output signal voltage based on the high-level drive signal; and a low-level drive for outputting a low-level output signal voltage based on the low-level drive signal And an output buffer.   13. The output buffer according to claim 12, wherein each of the high level side driving means and the low level side driving means is a plurality of driving transistors.   14. The output buffer according to claim 13, wherein the high level side driving means is a plurality of PMOS transistors, and the low level side driving means is a plurality of NMOS transistors.   The output buffer according to claim 10 or 11, further comprising a pre-buffer in a previous stage of the slew rate control device according to any one of claims 1 to 9.   15. The output buffer according to claim 12, further comprising a pre-buffer in a preceding stage of the slew rate control device according to claim 5 and the slew rate control device according to claim 6.   An information processing apparatus that performs information processing using the output buffer according to claim 10.

Images