JP2005228947A - Electromagnetic solenoid drive circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent adverse effects in variation in the amount of current on other signals, by suppressing increase in the amount of current due to a drive signal being fed to a plurality of electromagnetic solenoids. <P>SOLUTION: A first electromagnetic solenoid and a second electromagnetic solenoid are subjected to drive control, by duty control based on first and second solenoid drive signals, respectively. When the first and second solenoid drive signals are turned on/off intermittently, after being turned on, power is supplied to the first and second electromagnetic solenoids which are thereby turned on. Subsequently, the first and second electromagnetic solenoids are supplied with power intermittently and subjected to drive control. The first solenoid drive signal is outputted from a first output terminal 2-1 and fed to the first electromagnetic solenoid; whereas the second solenoid drive signal is outputted from a second output terminal 2-2 and fed to the first electromagnetic solenoid; and the phases of the first and second solenoid drive signals are set in reverse. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an electromagnetic solenoid drive circuit that collectively controls driving of a plurality of electromagnetic solenoids.

Conventionally, as an apparatus for driving and controlling an electromagnetic solenoid, for example, those described in the following documents are known (see Patent Document 1 and Patent Document 2). In the techniques described in these documents, when duty controlling an electromagnetic solenoid, the power supply voltage is controlled by intermittently controlling a pulse signal (drive signal) supplied to the electromagnetic solenoid after a predetermined time elapses when the duty control is turned on. A predetermined electromagnetic solenoid operating force is obtained by intermittently applying the electromagnetic solenoid. As a result, the rise and fall of the valve device controlled to open and close by the electromagnetic solenoid is quick, and even if the drive frequency is increased, the minimum duty ratio capable of flow control is not increased, the flow control range is not narrowed, and precision is increased. Flow control was possible.
Japanese Patent Laid-Open No. 11-153245 JP-A-63-232065

  As described above, in the conventional electromagnetic solenoid drive circuit, when a plurality of electromagnetic solenoids are duty controlled, when a reference signal serving as a reference for generating a drive signal for driving the electromagnetic solenoid is shared, In the drive signal supplied to each electromagnetic solenoid, the signal waveform at the time of chopper output that is turned on / off intermittently after a predetermined time elapses when the drive signal is on is the same, and the drive signal is turned on / off intermittently Are synchronized with the drive signal supplied to each electromagnetic solenoid.

  When the drive signal becomes like this, for example, when the resistance value of the electromagnetic solenoid is low, such as at low temperatures, the amount of current flowing through the electromagnetic solenoid increases, and the input that is input to the electromagnetic solenoid drive circuit that outputs the drive signal due to current fluctuation This may adversely affect signals, for example, input signals of various sensors necessary for driving control of the electromagnetic solenoid, and may cause a problem that the level of the input signal is likely to fluctuate.

  Therefore, the present invention has been made in view of the above, and an object of the present invention is to suppress an increase in the amount of current due to a drive signal supplied to a plurality of electromagnetic solenoids, and to another signal due to fluctuations in the amount of current. It is an object of the present invention to provide an electromagnetic solenoid drive circuit that prevents adverse effects of the above.

  In order to achieve the above object, according to the first aspect of the present invention, the plurality of electromagnetic solenoids are driven and controlled by duty control based on drive signals respectively corresponding to the plurality of electromagnetic solenoids, and the drive signals are turned on. An electromagnetic solenoid drive circuit that intermittently turns on / off a drive signal to supply power to the electromagnetic solenoid and then intermittently supplies power to drive the electromagnetic solenoid. The drive signals are output from different output terminals and supplied to the corresponding electromagnetic solenoids, and the plurality of drive signals have different phases.

  According to the first aspect of the present invention, it is possible to suppress an increase in the current amount of the drive signal when the drive signal is output, and to prevent adverse effects on other signals due to fluctuations in the current amount. be able to.

  According to a second aspect of the invention, in the first aspect of the invention, the electromagnetic solenoid drive circuit controls the drive of two electromagnetic solenoids, and the phases of drive signals supplied to the two electromagnetic solenoids are opposite to each other. The phase is set.

  According to the second aspect of the present invention, it is possible to suppress an increase in the current amount of the drive signal when the drive signal is output, and to prevent adverse effects on other signals due to fluctuations in the current amount. be able to.

  DESCRIPTION OF THE PREFERRED EMBODIMENTS The best embodiment for carrying out the present invention will be described below with reference to the drawings.

  1 is a diagram showing a configuration of an electromagnetic solenoid drive circuit according to a first embodiment of the present invention, and FIG. 2 is a diagram showing an operation timing chart of the circuit shown in FIG. The electromagnetic solenoid drive circuit of the first embodiment shown in FIG. 1 generates and outputs two first and second solenoid drive signals corresponding to two first and second electromagnetic solenoids (not shown). A reference signal for PWM control (pulse width modulation control) of the electromagnetic solenoid, and a first solenoid drive signal is generated based on the first timer signal, the second timer signal, and the first PWM signal output from the CPU 1 Then, the second solenoid drive signal is generated based on the third timer signal, the fourth timer signal and the second PWM signal which are supplied from the first output terminal 2-1 to the first electromagnetic solenoid and output from the CPU 1. 2 Supply from the output terminal 2-2 to the second electromagnetic solenoid.

  The CPU 1 determines each of the first and second drive signals based on each signal functioning as various control factors when driving and controlling the electromagnetic solenoid input from an external sensor and the like, and a program provided in the CPU 1. The frequency, the duty ratio, and the like are determined, and the first timer signal, the second timer signal, the third timer signal, the fourth timer signal, the first PWM signal, and the second PWM signal are output according to the results. The CPU 1 outputs the first timer signal, the second timer signal, the third timer signal, the fourth timer signal, the first PWM signal, and the second PWM signal from different output terminals, and outputs the first timer signal to the first timer output terminal ( Output from the output port), the second timer signal is output from the second timer output terminal (output port), the first PWM signal is output from the first PWM output terminal (output port), and the third timer signal is output to the third timer. Output from the terminal (output port), output the fourth timer signal from the fourth timer output terminal (output port), and output the second PWM signal from the second PWM output terminal (output port). Further, the CPU 1 outputs both signals at a timing when the first PWM signal and the second PWM signal are in opposite phases.

  The first timer signal output from the CPU 1 is input to the anode terminal of one diode D1 of the two diodes D1 and D2 whose cathode terminals are commonly connected. The two diodes D1 and D2 function as an OR gate that takes a logical sum (OR) of the first timer signal input to the anode terminal of the diode D1 and the signal input to the anode terminal of the diode D2. A pull-down resistor R1 for preventing the outputs of the diodes D1 and D2 from becoming unstable is connected to the cathode terminals of the commonly connected diodes D1 and D2. The output signals of the diodes D1 and D2 are given to the first solenoid drive signal output unit 3 via the resistor R2. The resistor R2 is provided to limit the current applied to the input terminal of the first solenoid drive signal output unit 3 to which the output signals of the diodes D1 and D2 are input, and to protect the input terminal.

  The first solenoid drive signal output unit 3 receives the output signals of the diodes D1 and D2 and the power supply from the power source VIGN, generates a first solenoid drive signal, and outputs the generated first solenoid drive signal to the first output terminal 2- Output to 1.

  On the other hand, the second timer signal and the first PWM signal are supplied to a NAND (NAND) gate 4. The NAND gate 4 takes a negative logical product of the second timer signal and the first PWM signal, and gives the result to the base terminal of the bipolar transistor T1. The input terminal to which the second timer signal of the NAND gate 4 is input is grounded through the resistor R3.

  The transistor T1 has its emitter terminal grounded and its collector terminal connected to the power supply VCC via the anode terminal of the diode D2 and the resistor R4. The transistor T1 receives the output signal of the NAND gate 4 and has an inverted output signal level. A signal is applied to the anode terminal of the diode D2. The resistor R4 functions as a resistor that pulls up the collector terminal to a high level when the transistor T1 is off.

  The first timer signal is given to the base terminal of the bipolar transistor T2. The emitter terminal of the transistor T2 is grounded, the collector terminal is connected to the base terminal of the bipolar transistor T3, and ON / OFF control is performed based on the first timer signal. The transistor T3 has an emitter terminal connected to the power supply VIGN ', a collector terminal connected to the gate terminal of an FET (field effect transistor) T4 via a resistor R4, and a signal at a level obtained by inverting the output signal level of the transistor T2. Output. Therefore, the transistors T2 and T3 control the on / off of the FET T4 based on the second timer signal. The resistor R4 functions as a current limiting resistor that limits the current flowing through the gate terminal of the FET T4.

  The FET T4 has a source terminal connected to the first output terminal 2-1 via the diode D3, a drain terminal connected to the ground, and a gate terminal connected to the source terminal via a level fixing resistor R5. The FET T4 is ON / OFF controlled by the transistors T2 and T3 based on the second timer signal, and the conduction is controlled so that the FET T4 is ON only for a time specified by the second timer signal. Thus, the FET T4 supplies a ring current from the ground potential to the first output terminal 2-1 via the diode D3 when the first solenoid drive signal is chopped.

  On the other hand, the third timer signal, the fourth timer signal, and the second PWM signal output from the CPU 1 generate the first solenoid driving signal based on the first timer signal, the second timer signal, and the first PWM signal. The same circuit configuration (not shown) as the configuration is applied to generate a second solenoid drive signal, the generated second solenoid drive signal is applied to the second output terminal 2-2, and the second output terminal 2- 2 to the second electromagnetic solenoid.

  Next, the operation of the drive circuit will be described with reference to the timing chart of FIG. In FIG. 1, the signal waveform of the first timer signal (point a in FIG. 1), the signal waveform of the second timer signal (point b in FIG. 1), the signal waveform of the first PWM signal (point c in FIG. 1), Signal waveform of first solenoid drive signal (point d in FIG. 1), signal waveform of third timer signal (point e in FIG. 1), signal waveform of fourth timer signal (point f in FIG. 1), second solenoid drive The signal waveform of the signal (point g in FIG. 1) and the signal waveform of the second PWM signal (point h in FIG. 1) are as shown in FIG. 2, and the timing relationship of each signal changes as shown in FIG. It shall be.

  First, the first timer signal, the second timer signal, and the first PWM signal are output from the CPU 1 of the electromagnetic solenoid drive circuit at the timing shown in FIG. As a result, as shown in FIG. 2, the first output terminal 2-1 is turned on / off intermittently after a predetermined time has elapsed (when chopper is output, the period indicated by A in FIG. 2). A first solenoid drive signal is provided.

  At the timing of each signal shown in FIG. 2, the duty ratio of the first solenoid drive signal is determined by the logical sum of the first timer signal and the second timer signal, and the chopper output of the first solenoid drive signal is the second timer signal. And the first PWM signal.

  On the other hand, a third timer signal, a fourth timer signal, and a second PWM signal are output from the CPU 1 of the electromagnetic solenoid drive circuit at the timing shown in FIG. As a result, as shown in FIG. 2, the second output terminal 2-2 intermittently turns on / off after a predetermined time at the time of on (period shown by B in FIG. 2 at the time of chopper output). A second solenoid drive signal is provided.

  At the timing of each signal shown in FIG. 2, the duty ratio of the second solenoid drive signal is determined by the logical sum of the third timer signal and the fourth timer signal, and the chopper output of the second solenoid drive signal is the fourth timer signal. And the second PWM signal.

  In the process of generating the first and second solenoid drive signals in this way, the phases of the first PWM signal related to the generation of the first solenoid drive signal and the second PWM signal related to the generation of the second solenoid drive signal are: As shown in FIG. 2, it is set and output by the CPU 1 so as to have an opposite phase. As a result, a period (period indicated by A in FIG. 2) that intermittently turns on / off after a predetermined time elapses when the first solenoid drive signal is turned on, and an intermittent period after a predetermined time elapses when the second solenoid drive signal is turned on. Compared with the period during which the signal is turned on / off (the period indicated by B in FIG. 2), the timing when both are turned on / off is reversed. That is, when the first solenoid drive signal is high level (on), the second solenoid drive signal is low level (off), while when the first solenoid drive signal is low level (off), the second solenoid drive signal is high level (off). ON).

  Accordingly, the output current of the first solenoid drive signal and the output current of the second solenoid drive signal are averaged during a period in which the first and second solenoid drive signals are intermittently turned on / off after a predetermined time has elapsed. Therefore, it is possible to suppress an increase in the amount of current, and it is possible to prevent an influence on other signals input to the electromagnetic solenoid drive circuit due to current fluctuation.

  In the first embodiment, the case where two electromagnetic solenoids are driven and controlled in parallel has been described. However, when three or more electromagnetic solenoids are controlled in parallel, a plurality of drive solenoids that drive and control each electromagnetic solenoid are used. By shifting the phase of the solenoid drive signal and setting the timing phase of each solenoid drive signal so that all solenoid drive signals are not in phase, the increase in current can be reduced as in the first embodiment. It becomes.

It is a figure which shows the structure of the electromagnetic solenoid drive circuit which concerns on Example 1 of this invention. It is a figure which shows the operation | movement timing chart which concerns on Example 1 of this invention.

Explanation of symbols

1 ... CPU
2-1 ... 1st output terminal 2-2 ... 2nd output terminal 3 ... 1st solenoid drive signal output part 4 ... NAND gate D1, D2, D3 ... Diode R1, R2, R3, R4, R5 ... Resistance T1, T2 , T3 ... Transistor T4 ... FET

Claims (2)

The electromagnetic solenoids are driven and controlled by duty control based on drive signals respectively corresponding to the plurality of electromagnetic solenoids, and the drive signals are intermittently turned on / off after the drive signals are turned on. An electromagnetic solenoid drive circuit that intermittently supplies power after the power is supplied to the power supply to drive and control the electromagnetic solenoid,
The plurality of drive signals are output from different output terminals and supplied to the corresponding electromagnetic solenoids, and the plurality of drive signals have different phases. The electromagnetic solenoid driving circuit according to claim 1, wherein the electromagnetic solenoid driving circuit drives and controls two electromagnetic solenoids, and phases of drive signals supplied to the two electromagnetic solenoids are set to opposite phases to each other. Solenoid drive circuit.

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