JP2005226494A - Electronic control unit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent an electronic control unit (ECU) from determining a timer circuit to be abnormal even when it operates normally. <P>SOLUTION: The ECU has a timer IC for starting a microcomputer when a certain period of time elapses after the microcomputer is stopped operating and is constructed so that the microcomputer does not write data in a RAM when voltage supplied to the operating microcomputer becomes lower than predetermined voltage. In this ECU, when the microcomputer is started by the timer IC (S120:YES) and determines that data are not to be written in the RAM (S130:YES), a starting history R indicating the starting by the timer IC is not written in the RAM, a count value of the timer IC is reset (S180) and operation is terminated. When the microcomputer is started thereafter by an ignition switch before the count value reaches a setting value, this causes no contradiction that the count value exceeds the setting value whereas the starting history R is not written. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an electronic control device that controls an engine of a vehicle and the like, and more particularly, in the electronic control device, an electronic control provided with a timer circuit that starts a microcomputer when a certain time has elapsed after the operation of the microcomputer (microcomputer) is stopped It relates to the device.

  Conventionally, in an electronic control device that controls a vehicle engine, for example, a secondary power supply circuit that always outputs a constant power supply voltage Vs based on battery power and a vehicle ignition switch that is not always on are turned on. And a main power supply circuit that outputs a constant power supply voltage Vm based on the power of the battery.

  The power supply voltage Vm from the main power supply circuit is supplied to a microcomputer or the like with large power consumption, and the power supply voltage Vs from the sub power supply circuit is much higher than that of a microcomputer or the like although it must always operate. It is supplied to a small circuit or memory (so-called backup RAM).

  In particular, in this type of electronic control device, the time during which the microcomputer stops operating (in other words, the power supply voltage Vm is output from the main power supply circuit by the timer circuit operated by the power supply voltage Vs from the sub power supply circuit. In some cases, the timer circuit outputs the power supply voltage Vm from the main power supply circuit and starts the microcomputer when the measurement time reaches a predetermined set time. .

  By providing such a timer circuit, it is possible to carry out a desired process when a set time elapses after the ignition switch is turned off even if the microcomputer is not constantly operated. Power consumption can be significantly reduced.

More specifically, the following configurations (a) and (b) are adopted.
(A) The main power supply circuit is configured to output the power supply voltage Vm when an ignition switch is turned on or an operation command signal generated inside the electronic control device is at an active level.

  (B) In the timer circuit, when its own count value is initialized by the microcomputer and when the ignition switch is turned off and the power supply voltage Vm is not supplied from the main power supply circuit to the microcomputer, the timer circuit counts from the initial value (for example, Start up-counting). When the count value reaches a set value corresponding to the set time, the timer circuit activates the operation command signal to the main power supply circuit to output the power supply voltage Vm from the main power supply circuit. Let

  As an electronic control device that requires such a timer circuit, for example, there is one that performs diagnosis of an evaporative purge system as described in Patent Document 1. In other words, in this type of evaporation purge system diagnosis, for example, a system for recovering evaporation gas (evaporative gas fuel generated from fuel) from an engine fuel tank is closed and pressurized or depressurized. The pressure tightness of the system is detected by detecting pressure fluctuations (ie, the presence or absence of leaks), but the fuel in the fuel tank is likely to evaporate immediately after the engine is operated for a long time under a high load condition. Test results are difficult to obtain. For this reason, after a predetermined time has elapsed after the engine is stopped, the above-described vapor purge system is inspected by a microcomputer.

Some electronic control devices of this type diagnose whether or not the timer circuit is operating normally.
When the microcomputer is activated by the timer circuit as an electronic control device having a function of diagnosing an abnormality in the timer circuit, the microcomputer performs a specific process, and after the process ends, the processed flag is set to a nonvolatile memory. If the microcomputer is started by the ignition switch, the microcomputer resets the processed flag and initializes the count value of the timer circuit when the microcomputer finishes its operation. There is something that is. The processed flag is a flag indicating that the microcomputer is started by the timer circuit while the operation is stopped.

If the microcomputer is started by an ignition switch, the microcomputer determines whether the processed flag is stored in the nonvolatile memory, and determines that the processed flag is stored. If it is determined that the timer circuit is operating normally, but if it is determined that the processed flag is not stored, it is further determined whether or not the count value of the timer circuit exceeds the set value. If it is determined that the count value does not exceed the set value, it is determined that the timer circuit is operating normally, and if it is determined that the count value of the timer circuit exceeds the set value, It is determined that the timer circuit is not operating normally (that is, an abnormality has occurred in the timer circuit) (see, for example, Patent Document 2).
JP-A-8-35452 JP 2003-139874 A

  Incidentally, in general, in an electronic control unit, a power supply voltage Vm supplied to a microcomputer from a main power supply circuit is a specific voltage (for example, normal) that is considered that the microcomputer cannot accurately perform an operation of storing information in a memory. When the power supply voltage drops to 90% of the power supply voltage Vm), a prohibition function is provided so that the microcomputer does not perform the storage operation.

  For this reason, in such an electronic control device, even if the timer circuit operates normally, if the power supply voltage Vm from the main power supply circuit supplied to the microcomputer drops to the specific voltage, the microcomputer May mistakenly determine that the timer circuit function is abnormal. In other words, when the microcomputer is started by the timer circuit, if the power supply voltage Vm from the main power supply circuit supplied to the microcomputer has dropped to the specific voltage, the microcomputer sets the processed flag in the nonvolatile memory. After that, when the ignition switch is turned on and the microcomputer is started again, the count value of the timer circuit exceeds the set value even though the processed flag is not stored in the nonvolatile memory. Therefore, the microcomputer erroneously determines that the timer circuit function is abnormal.

  On the other hand, if the power supply voltage Vm supplied from the main power supply circuit to the microcomputer is reduced to the specific voltage when the microcomputer is started up even if the electronic control device is not provided with the prohibition function, the microcomputer May be able to store information accurately in memory, but if it cannot be stored correctly, problems similar to those described above will occur.

  The present invention has been made to solve the above problem, and in the electronic control device, the timer circuit for starting the microcomputer is operating normally after a certain period of time has elapsed after the microcomputer stops operating. Regardless, the object is to prevent erroneous determination that an abnormality has occurred in the timer circuit.

  The electronic control device according to claim 1, which is made to achieve the above object, operates with a power supply voltage constantly output from the first power supply circuit to perform a count operation, and a power switch is turned on. Or a second power supply circuit that outputs a power supply voltage when the operation command signal generated inside the electronic control device is at an active level, and a microcomputer that operates with the power supply voltage output from the second power supply circuit. And. The first power supply circuit and the second power supply circuit output each power supply voltage by a battery voltage supplied from the battery.

  In this electronic control device, when the count value of the timer circuit reaches a preset value in a state where the power supply voltage is not output from the second power supply circuit, the timer circuit transfers to the second power supply circuit. When the operation command signal becomes active level and the power supply voltage is output from the second power supply circuit, the microcomputer is activated.

  Further, when the microcomputer starts its operation upon receiving the power supply voltage from the second power supply circuit, the microcomputer performs a start reason determination process for determining whether the current start is due to the power switch or the timer circuit. When the microcomputer determines that the current activation is due to the timer circuit by the activation reason determination process, the microcomputer performs an activation history storage process for storing an activation history indicating that the timer circuit is activated in the storage unit, Only until the specific processing is completed, the operation command signal to the second power supply circuit is kept at the active level and the state where the power supply voltage is output from the second power supply circuit is maintained. Conversely, if the microcomputer determines that the current activation is due to the power switch by the activation reason determination process, the function of the timer circuit is abnormal based on the activation history in the storage means and the count value of the timer circuit. An abnormality detection process is performed to determine whether or not.

  In particular, in the electronic control device according to claim 1, the battery voltage is lower than a set voltage set to a voltage at which the microcomputer cannot accurately perform the operation of storing information in the storage means or a voltage higher than that. In such a case, the reset means resets the count value of the timer circuit.

  In such an electronic control device according to the first aspect, when the battery voltage falls below the set voltage, the count value of the timer circuit is reset, so that the microcomputer accurately stores the information in the storage means. In situations where it cannot be performed, the timer circuit is not activated.

  For this reason, if the timer circuit is operating normally, there is a contradiction that when the microcomputer is started by the power switch, the count value exceeds the set value even though the activation history is not stored in the storage means. No longer occurs.

Therefore, it is possible to prevent erroneous determination that an abnormality has occurred in the timer circuit even though the timer circuit is operating normally.
By the way, the electronic control device according to claim 1 can be configured specifically as described in claim 2.

  That is, the timer circuit is configured such that the count value is reset when the power supply voltage from the first power supply circuit is lower than the minimum operating voltage at which the timer circuit can operate. It is sufficient that the count value of the timer circuit is reset by prohibiting the supply of the power supply voltage from the first power supply circuit to the timer circuit when the voltage drops to the set voltage.

Further, the reset means is not limited to the electronic control device according to claim 2, and may be configured as described in claim 3, for example.
That is, the timer circuit is configured such that the count value is reset when the power supply voltage from the first power supply circuit becomes lower than the minimum operating voltage, and the reset means is configured to operate when the battery voltage drops to the set voltage. The count value of the timer circuit may be reset by making the power supply voltage supplied from the first power supply circuit to the timer circuit lower than the minimum operating voltage.

  Next, the electronic control device according to claim 4 includes the first and second power supply circuits, the timer circuit, and the microcomputer similar to those of the electronic control device according to claim 1. And invalidation means.

  Then, the detecting means is a specific voltage that is set such that the power supply voltage supplied to the microcomputer from the second power supply circuit is not more than a voltage value at which the microcomputer cannot accurately perform the operation of storing information in the storage means. Detects that it has dropped to.

  Further, the activation invalidating means is configured such that when the operation command signal from the timer circuit to the second power supply circuit becomes an active level and the microcomputer starts operation, the power supply voltage supplied from the second power supply circuit to the microcomputer is If it is detected by the detecting means that the voltage has dropped to the specific voltage, the microcomputer prohibits the execution history storing process, and further terminates the operation of the microcomputer and counts the timer circuit. To reset.

  In such an electronic control device according to claim 4, when the microcomputer is started by the timer circuit, the detection means detects that the power supply voltage supplied to the microcomputer from the second power supply circuit has dropped to a specific voltage. In this case, the activation history is not stored in the storage means, and the count value is reset when the operation of the microcomputer is completed, and the timer circuit starts counting from the initial value again from that point. .

  Therefore, after that, for example, if the microcomputer is activated by the power switch before the count value of the timer circuit reaches the set value, the count value exceeds the set value even though the activation history is not stored in the storage means. There is no contradiction.

Therefore, it is possible to prevent erroneous determination that an abnormality has occurred in the timer circuit even though the timer circuit is operating normally.
By the way, in the electronic control device according to the first aspect, even if the activation history is stored in the storage unit, the count value is reset if the battery voltage falls below the set voltage. There is a possibility that another contradiction may occur such that the count value does not exceed the set value even though is stored.

  That is, after the microcomputer is activated by the timer circuit and the activation history is stored in the storage means, the operation history is stored in the storage means after the microcomputer finishes the operation and is activated again by the power switch. In the case where the battery voltage drops below the set voltage and the microcomputer is activated by the power switch before the count value of the timer circuit reaches the set value, the activation history is stored in the storage means. However, a contradiction occurs that the count value does not exceed the set value.

  For this reason, in the electronic control device according to claim 1, if the microcomputer detects an abnormality in the timer circuit when the count value exceeds the set value even though the activation history is not stored in the storage means, In addition to the first determination process for determining that the timer has occurred, an abnormality has occurred in the timer circuit when the count value does not exceed the set value even though the activation history is stored in the storage means If the second determination process of determining is also performed, the microcomputer erroneously determines that the timer circuit is normal but abnormal in the second determination process in the above case.

  On the other hand, in the electronic control device according to claim 4, even if the microcomputer is activated by the timer circuit, the activation history is not stored in the storage means (that is, the power supply voltage from the second power supply circuit reaches a specific voltage). When the detection means detects that the value has decreased, the count value is reset, so that a contradiction may occur such that the activation value is stored in the storage means but the count value does not exceed the set value. Absent.

  Therefore, according to the electronic control device of claim 4, it is said that an abnormality has occurred in the timer circuit even if the second determination process is performed as the abnormality detection process in addition to the first determination process. An erroneous determination can be prevented, and the presence or absence of an abnormality in the timer circuit can be determined more reliably.

  Hereinafter, an electronic control device according to an embodiment to which the present invention is applied will be described with reference to the drawings. An electronic control device (hereinafter referred to as an ECU) of each embodiment described below mainly controls a vehicle engine.

First, FIG. 1 is a configuration diagram showing the configuration of the ECU 1 of the first embodiment.
As shown in FIG. 1, the ECU 1 includes a microcomputer 11 that performs various processes for controlling the engine, a timer IC 13 that measures the time during which the microcomputer 11 has stopped operating, and a main unit for operating the microcomputer 11. A main power supply unit 15a that outputs a power supply voltage Vm, a first sub power supply unit 15b that outputs a sub power supply voltage Vs1 for the RAM 11a built in the microcomputer 11 to always hold data, and a sub power supply for operating the timer IC 13 And a power supply circuit 15 including a second sub power supply unit 15c that outputs a voltage Vs2. In the present embodiment, the main power supply voltage Vm and the sub power supply voltage Vs2 output from the main power supply unit 15a and the second sub power supply unit 15c are 5 [V], and the sub power output from the first sub power supply unit 15b. The power supply voltage Vs1 is 3 [V]. Moreover, what is indicated by a circle (◯) in the ECU 1 in FIG. 1 is a terminal of the ECU 1. This also applies to FIG. 7 described later. In the following description, the RAM 11a that can always hold data by being supplied with the sub power supply voltage Vs1 is referred to as an SRAM 11a.

  A voltage VBAT (normally about 12 [V], hereinafter referred to as a battery voltage) VBAT of the vehicle battery 17 is constantly supplied to the first and second sub power supply units 15b and 15c. The first and second sub power supply units 15b and 15c always generate and output the sub power supply voltages Vs1 and Vs2 from the battery voltage VBAT.

  Further, the main power supply unit 15a has the ECU 1 when the ignition switch (hereinafter referred to as IGSW) 19 of the vehicle is turned on or when the output request signal PI output from the timer IC 13 is at a high level. The battery voltage VBAT is supplied through a main relay 21 for power supply provided outside. The output request signal PI is high when at least one of a power activation signal SK output from a counter 13a (to be described later) of the timer IC 13 and a microcomputer holding signal SH output from the microcomputer 11 is high. It comes to become. In the following description, the battery voltage supplied from the positive terminal of the battery 17 via the main relay 21 will be referred to as the battery voltage VB, and supplied from the positive terminal of the battery 17 without passing through the main relay 21. The battery voltage is referred to as battery voltage VBAT.

The main power supply unit 15a generates and outputs a main power supply voltage Vm from the battery voltage VB supplied via the main relay 21.
Specifically, first, when the battery voltage VBAT is input to the ECU 1 via the IGSW 19, the ECU 1 generates and outputs a 5 [V] IGSW signal SIG corresponding to a high level from the battery voltage VBAT. When the IGSW 19 is turned off and the battery voltage VBAT is no longer input, an input circuit 23 is provided for setting the IGSW signal SIG to 0 [V] corresponding to the low level. That is, the IGSW signal SIG is a signal indicating the on / off state of the IGSW 19.

  The ECU 1 has a collector connected to the other end of the coil of the main relay 21 whose one end is connected to the ground potential, and an emitter connected to the battery voltage VBAT. From a PNP transistor 25a for passing current, and a NOR circuit 25b for turning on the PNP transistor 25a when at least one of the IGSW signal SIG from the input circuit 23 and the output request signal PI from the timer IC 13 is at a high level. A main relay control circuit 25 is provided.

  In the main relay control circuit 25, when the NOR circuit 25b turns on the PNP transistor 25a, the coil of the main relay 21 is energized to short-circuit (turn on) the contact of the main relay 21. Although not shown, the main relay control circuit 25 (specifically, the NOR circuit 25b) operates in response to the sub power supply voltage Vs2 from the second sub power supply unit 15c, similarly to the timer IC 13.

  Therefore, when either the IGSW signal SIG or the output request signal PI is at a high level, the main relay 21 is turned on and the battery voltage VB is supplied to the main power supply unit 15a, and the main power supply voltage is supplied from the main power supply unit 15a. Vm is output. In the present embodiment, the logic levels of the signals SIG, SH, SK, PI are high level active levels, and the opposite low level is passive levels.

  Further, the main power supply unit 15a changes its logic level when the main power supply voltage Vm generated by the main power supply unit 15a falls below a predetermined voltage value Va (4.5 [V] in the present embodiment). A write inhibit signal WI is output to the microcomputer 11.

  More specifically, the write inhibit signal WI is a signal for causing the microcomputer 11 to inhibit the write operation to the SRAM 11a, and as shown in FIG. 2, 5 [V] output from the main power supply unit 15a. When the main power supply voltage Vm decreases to the predetermined voltage value Va at time ta, the output level changes from the high level to the low level. Thereafter, when the main power supply unit 15a can output the main power supply voltage Vm of 5 [V] at time tb, the output level of the write inhibit signal WI is increased at time tc delayed by time T. It becomes high level again. In this embodiment, the logic level of the write inhibit signal WI is an active level at a low level.

  The main power supply unit 15a also has a so-called power-on reset function that outputs a reset signal to the microcomputer 11 for a very short time when the main power supply voltage Vm is considered to be stable at the start of output of the main power supply voltage Vm. For this reason, when the main power supply unit 15a starts outputting the main power supply voltage Vm, the microcomputer 11 starts operation (ie, starts) from the initial state.

  The timer IC 13 is one of a counter 13a that performs a counting operation (in this embodiment, an up-counting operation), a microcomputer holding signal SH from the microcomputer 11, and a power activation signal SK output from the counter 13a of the timer IC 13. OR circuit 13b that outputs a high-level output request signal PI when is at a high level.

The timer IC 13 has the following functions (1) to (5).
(1) Upon receiving a “counter clear instruction” from the microcomputer 11, the count value of the counter 13 a (that is, the count value of the timer IC 13, hereinafter referred to as a counter value) is reset to an initial value (zero).

  (2) A set value Ns to be compared with the counter value is transmitted from the microcomputer 11 and set. In the present embodiment, the microcomputer 11 sets a value smaller than the maximum value (max value) that can be counted by the counter 13a (a value before the final value of the counter value) as the set value Ns. ing.

  (3) When the counter value reaches the set value Ns set by the microcomputer 11 (counter value = set value Ns), the output level of the power activation signal SK to the OR circuit 13b is held at a high level. Then, the OR circuit 13b to which the high-level power supply activation signal SK is input holds the output level of the output request signal PI to the NOR circuit 25b of the main relay control circuit 25 at a high level.

(4) When “SK clear instruction” is received from the microcomputer 11, the output level of the power activation signal SK is reset to a low level.
(5) The counter value can be read by the microcomputer 11 and an arbitrary value can be set.

  On the other hand, when the microcomputer 11 starts operating upon receiving the main power supply voltage Vm from the main power supply unit 15a, the microcomputer holding signal SH to the timer IC 13 is set to the high level, and the main power supply voltage Vm is output from the main power supply unit 15a. (That is, a state in which the microcomputer 11 is operable). That is, when the microcomputer holding signal SH becomes high level, the output request signal PI becomes high level. Therefore, the microcomputer 11 is in a state in which the battery voltage VB is supplied from the main relay 21 to the ECU 1, and the main power supply unit 15a. Thus, the state where the main power supply voltage Vm is output is maintained.

The microcomputer 11 does not operate to write data to the SRAM 11a when the write inhibit signal WI input from the main power supply unit 15a is at a low level.
Further, when the microcomputer 11 is activated when the IGSW 19 is turned on (in other words, when the IGSW signal SIG is changed to a high level), the processing for stopping the engine is completed after the IGSW 19 is turned off. Further, assuming that the operation stop condition is satisfied, the microcomputer holding signal SH is set to the low level, and the supply of the main power supply voltage Vm from the main power supply unit 15a is stopped, so that the operation of itself is finished.

  On the other hand, when the microcomputer 11 is activated when the output request signal PI (specifically, the power activation signal SK) from the timer IC 13 becomes high level while the IGSW 19 is off, the microcomputer 11 is activated by the timer IC 13 first. A startup history R indicating this is written to the SRAM 11a.

  After that, when a specific process (in this embodiment, the evaporative purge system diagnosis process) executed at the time of completion of the operation is completed, it is assumed that the operation stop condition is satisfied. ”To cause the power supply activation signal SK from the timer IC 13 to go low.

Further, the microcomputer 11 stops its operation by setting the microcomputer holding signal SH to a low level and stopping the supply of the main power supply voltage Vm from the main power supply unit 15a.
In the present embodiment, the timer IC 13 corresponds to a timer circuit, the main power supply unit 15a corresponds to a second power supply circuit, and the second sub power supply unit 15c corresponds to a first power supply circuit. The SRAM 11a corresponds to a storage unit, the IGSW 19 corresponds to a power switch, and the output request signal PI corresponds to an operation command signal.

Next, processing executed by the microcomputer 11 will be described with reference to the flowcharts of FIGS.
First, when the microcomputer 11 is activated upon receiving the main power supply voltage Vm from the main power supply unit 15a, the microcomputer 11 executes the processing of FIG.

  Then, in S110, the microcomputer holding signal SH to the timer IC 13 is set to the high level, and the main power supply voltage Vm is output from the main power supply unit 15a (that is, the output request signal PI is in the high level state). The state in which the main relay 21 is on) is maintained.

  Next, in subsequent S120, in order to determine whether the current activation is due to turning on the IGSW 19 or the timer IC 13, the logic level of the power activation signal SK from the timer IC 13 is read and the power activation signal SK is read. It is determined whether or not is at a high level. If it is determined in S120 that the power activation signal SK is at the high level, it is determined that the current activation is due to the timer IC 13 (S120: YES), and the process proceeds to S130.

In S130, the logic level of the write inhibit signal WI from the main power supply unit 15a described above is read to determine whether or not the write inhibit signal WI is at a low level.
If it is determined in S130 that the write inhibit signal WI is not low level (high level), the process proceeds to S140, and the activation history R is written in the SRAM 11a.

  Next, in the subsequent S150, an evaporation purge system diagnosis process (hereinafter referred to as an evaporation diagnosis process) is performed. As described above, the contents of the evaporation diagnosis process are as follows. The system for recovering the evaporated gas from the engine fuel tank is closed and pressurized or depressurized, and the pressure fluctuation in the system is detected to detect the fluctuation of the system. Such as checking for airtightness.

  The diagnosis result of the evaporation diagnosis process is stored in, for example, the SRAM 11a. And the diagnostic result memorize | stored in the SRAM11a is read to the diagnostic apparatus connected to ECU1 via a communication line, or when there exists abnormality, it is displayed on the indicator of a vehicle.

  When the evaporation diagnosis process in S150 is completed, the process proceeds to S160, where a “SK clear instruction” is output to the timer IC 13 and the power activation signal SK from the timer IC 13 is set to the low level.

  In S170, the microcomputer holding signal SH to the timer IC 13 is returned to the low level. Then, the output level of the output request signal PI changes to a low level, and the main relay 21 is turned off. As a result, the output of the main power supply voltage Vm is stopped from the main power supply unit 15a, and the microcomputer 11 (and thus the ECU 1) stops operating.

  If it is determined in S130 that the write inhibit signal WI is not at a high level (low level), the process proceeds to S180, where a “counter clear instruction” is transmitted to the timer IC 13, and the timer IC 13 Reset the counter value. The microcomputer 11 also transmits and sets the next set value Ns when transmitting a “counter clear instruction” to the timer IC 13.

  When the process of S180 is completed, the process proceeds to S160, where a “SK clear instruction” is transmitted to the timer IC 13, and in S170, the microcomputer holding signal SH is returned to the low level. Then, as described above, the main relay 21 is turned off, and the operations of the microcomputer 11 and the ECU 1 are stopped.

  On the other hand, if it is determined in S120 that the power activation signal SK is at a low level (not a high level), it is determined that the current activation is due to the IGSW 19, and the process proceeds to S190.

  In S190, in order to determine whether or not the IGSW 19 is turned off, the logic level of the IGSW signal SIG from the input circuit 23 is read to determine whether or not the IGSW signal SIG is at a low level. If it is determined in S190 that the IGSW signal SIG is not at a low level (high level), it is determined that the IGSW 19 is on, and waits until the IGSW signal SIG is at a low level. .

  If it is determined in S190 that the IGSW signal SIG is at the low level, it is determined that the IGSW 19 has been turned off, and the process proceeds to S200, and the ECU 1 operates the engine during the ON period of the current IGSW 19. It is determined whether or not it has been made.

  If it is determined in S200 that the engine has been operated, the process proceeds to S210 where the startup history R is deleted, and in S220, a "counter clear instruction" is transmitted to the timer IC 13 and the next setting is made. The value Ns is also transmitted and set.

  When the process of S220 is completed, the process proceeds to S170, and the microcomputer holding signal SH is returned to the low level. Then, as described above, the main relay 21 is turned off, and the operations of the microcomputer 11 and the ECU 1 are stopped. If the time corresponding to the set value Ns elapses after the IGSW 19 remains off, the microcomputer 11 is started by the timer IC 13.

  On the other hand, if it is determined in S200 that the engine is not operating, it is not necessary to perform the evaporation diagnosis process before the microcomputer 11 is activated by the IGSW 19 next time, and the process proceeds to S230.

  In S230, the counter value is set to the maximum value so that the microcomputer 11 is not activated by the timer IC 13. For this reason, the count value has already exceeded the set value Ns, and the microcomputer 11 will not be started by the timer IC 13 after the current operation is completed.

Next, in subsequent S240, the flag FA in the SRAM 11a indicating that the activation of the microcomputer 11 by the timer IC 13 is prohibited is set, and the process proceeds to S170.
In S170, the microcomputer holding signal SH to the timer IC 13 is returned to the low level. Then, as described above, the main relay 21 is turned off, and the operations of the microcomputer 11 and the ECU 1 are stopped.

  Next, FIG. 4 is a flowchart of the abnormality determination process executed when it is determined in S120 of FIG. 3 that the current activation of the microcomputer 11 is caused by the IGSW 19 (S120: NO).

  When the microcomputer 11 starts the process of FIG. 4, it is first determined in S305 whether or not the flag FA is set. If it is determined that the flag FA is set (S305: YES), the process proceeds to S307. Then, the flag FA is reset and the process is terminated as it is. That is, in this case, it is not necessary to determine whether the timer IC 13 is normal or abnormal.

On the other hand, if it is determined in S305 that the flag FA is not set (S305: NO), the process proceeds to S310.
In 310, the counter value is read from the timer IC 13, and the read counter value is written in the SRAM 11a. In the following description, the read counter value is referred to as counter value CNT.

  When the process of S310 is completed, the process proceeds to S320, and it is determined whether or not the activation history R is written in the SRAM 11a. If it is determined in S320 that the activation history R is written in the SRAM 11a, the process proceeds to S330. Conversely, if it is determined that the activation history R is not written in the SRAM 11a, the process proceeds to S340. .

In S330 and S340, it is determined whether or not the counter value CNT written in the SRAM 11a in S310 exceeds the set value Ns.
Here, when it is determined that the activation history R is written in the SRAM 11a and it is determined that the counter value CNT exceeds the set value Ns (S320: YES and S330: YES), or the activation history is stored in the SRAM 11a. If it is determined that R has not been written and it is determined that the counter value CNT does not exceed the set value Ns (S320: NO and S340: NO), the process proceeds to S350. In S350, it is determined that there is no abnormality (normal) in the function of the timer IC 13, and the process ends.

  On the other hand, when it is determined that the activation history R is written in the SRAM 11a and it is determined that the counter value CNT does not exceed the set value Ns (S320: YES and S330: NO), or the activation history R is stored in the SRAM 11a. When it is determined that the counter value CNT exceeds the set value Ns (S320: NO and S340: YES), the process proceeds to S360.

  In S360, it is determined that the function of the timer IC 13 is abnormal. In S370, the diag code is stored in the SRAM 11a, and the process is terminated. The diagnosis code is diagnosis information indicating, for example, that an abnormality has occurred and the content of the abnormality.

  Next, the operation of the ECU 1 of the first embodiment as described above will be described using the time charts of FIGS. 5 and 6. FIG. 5 shows the normal operation. FIG. 5A shows the case where the write inhibit signal WI is at a high level when the microcomputer 11 is started by the timer IC 13. FIG. This shows a case where the write inhibit signal WI is at a low level when the microcomputer 11 is activated by the timer IC 13. FIG. 6 shows the action when an abnormality occurs.

First, the normal operation will be described with reference to FIG.
As shown on the left side of time t1 in FIG. 5A, since the IGSW signal SIG is at a high level while the IGSW 19 is on, the main power supply voltage Vm is output from the main power supply unit 15a and the microcomputer 11 Works. Then, the microcomputer 11 performs ignition control, fuel injection control, and the like for the engine. In this state, the power activation signal SK from the timer IC 13 is reset to a low level.

  Thereafter, if the IGSW 19 is turned off at time t1 in FIG. 5 (a), the microcomputer 11 erases the activation history R (S210) by the processes S170, S210, and S220 executed in FIG. The value is reset to zero (S220), and finally the microcomputer holding signal SH is set to low level (S170). The microcomputer 11 activated by the IGSW 19 sets a set value Ns corresponding to a predetermined set time Ts in the timer IC 13 when transmitting a “counter clear instruction” to the timer IC 13 (S220). . In this example, the set time Ts is a waiting time from when the microcomputer 11 stops operating until it starts again and performs the evaporation diagnosis process. In this embodiment, the set time Ts is set to 5 hours.

Then, the main power supply voltage Vm is not output from the main power supply unit 15a, and the microcomputer 11 stops its operation.
When the IGSW 19 is turned off and the microcomputer 11 stops operating as described above, the counter 13a starts counting from the initial value in the timer IC 13.

  Thereafter, when the set time Ts elapses and the counter value in the timer IC 13 reaches the set value Ns, the power activation signal SK from the timer IC 13 becomes a high level at time t2, so that the main relay control is performed from the timer IC 13. The output request signal PI to the circuit 25 becomes high level, and accordingly, the main relay 21 is turned on, and the main power supply voltage Vm is output from the main power supply unit 15a.

  Then, the microcomputer 11 starts to operate, and first, the supply of the main power supply voltage Vm is secured by setting the microcomputer holding signal SH to the high level in S110 of FIG. At normal time, the microcomputer 11 determines that the power activation signal SK from the timer IC 13 is at a high level in S120.

  In this example, when the microcomputer 11 is activated by the timer IC 13, the write inhibit signal WI is at a high level. Therefore, the microcomputer 11 determines that the write inhibit signal WI is not at a low level (high level) in S130 of FIG. Is determined).

Then, the microcomputer 11 performs the evaporation diagnosis process after writing the activation history R in the SRAM 11a in S140.
Further, the microcomputer 11 resets the power activation signal SK from the timer IC 13 to the low level (S160), and finally sets the microcomputer holding signal SH to the low level (S170). Then, since the output request signal PI from the timer IC 13 becomes low level, the main relay 21 is turned off, the main power supply voltage Vm is not output from the main power supply unit 15a, and the microcomputer 11 stops its operation again. It will be.

When the microcomputer 11 stops operating as described above, in the timer IC 13, the counter 13a continues the count operation without resetting the counter value.
Thereafter, for example, it is assumed that the IGSW 19 is turned on at time t3 before the counter value reaches the maximum value.

  Then, the main relay 21 is turned on by the IGSW signal SIG, the main power supply voltage Vm is output from the main power supply unit 15a, and the microcomputer 11 starts operating. In this case as well, the microcomputer 11 first ensures the supply of the main power supply voltage Vm by setting the microcomputer holding signal SH to the high level in S110 of FIG.

  In this case, the microcomputer 11 determines that the IGSW 19 is activated in S120 of FIG. 3 (S120: NO), and starts the process of FIG. In this example, it is determined that the activation history R is written in the SRAM 11a (S320: YES), it is determined that the counter value CNT exceeds the set value Ns (S330: YES), and the timer IC 13 It is determined that there is no abnormality in the function (S350).

Thereafter, the microcomputer 11 repeats the process of S190 in FIG. 3 until the IGSW 19 is turned off, and performs ignition control, fuel injection control, and the like for the engine.
Further, as shown in FIG. 5B, it is assumed that the IGSW 19 is turned off at time t4, and then the microcomputer 11 is activated when the counter value in the timer IC 13 reaches the set value Ns at time t5.

  In this example, when the microcomputer 11 is activated by the timer IC 13, the write inhibit signal WI is at a low level. Therefore, the microcomputer 11 determines in S130 of FIG. 3 that the write inhibit signal WI is at a low level. Will be.

  Then, the microcomputer 11 resets the counter value without writing the activation history R in the SRAM 11a, and ends its own operation. For this reason, as shown at time t5, when the microcomputer 11 stops its operation, the timer IC 13 resets the counter value and starts the count operation from the initial value.

  Thereafter, if the IGSW 19 is turned on at time t6 before the counter value reaches the set value Ns, the microcomputer 11 is activated again, and the activation history R is not written to the SRAM 11a in the processes S320 to S340 of FIG. (S320: NO), it is determined that the counter value CNT does not exceed the set value Ns (S340: NO), and it is determined that there is no abnormality in the function of the timer IC 13 (S350).

  The microcomputer 11 activated by the IGSW 19 at times t3 and t6 resets the counter value when the predetermined time T1 has elapsed after activation, for example, when a certain time has elapsed since the microcomputer 11 reset the counter value. This is because the subsequent counter value is read, and based on this, it is determined whether or not the counting operation is normally performed.

  On the other hand, the timer IC 13 has an abnormality in which the main power supply unit 15a cannot be activated (for example, disconnection of the signal line of the output request signal PI from the timer IC 13 to the main relay control circuit 25 or short circuit failure to the low level side) Suppose that occurred.

  When such an abnormality has occurred, as illustrated in FIG. 6, a set time Ts has elapsed after the IGSW 19 is turned off at time t7, and the counter value in the timer IC 13 is set to the set value at time t8. Even when Ns is reached, the high-level output request signal PI is not input to the main relay control circuit 25, and the main power supply voltage Vm remains at 0 [V]. As a result, the microcomputer 11 remains stopped. .

  Then, when the IGSW 19 is turned on at the subsequent time t9 and the microcomputer 11 starts to operate, the microcomputer 11 determines that the activation by the IGSW 19 is performed in S120 of FIG. 3, and performs the abnormality determination process of FIG. However, in this case, when the microcomputer 11 is activated and the processing of S310 in FIG. 4 is performed, the activation history R is not written in the SRAM 11a, but the counter value CNT of the timer IC 13 has already exceeded the set value Ns. Will be.

  For this reason, the microcomputer 11 determines in S320 that the activation history R has not been written in the SRAM 11a, and in subsequent S340, determines that the counter value CNT exceeds the set value. Therefore, the microcomputer 11 determines that there is an abnormality in the function of the timer IC 13 in S360 of FIG.

  In the ECU 1 of the first embodiment as described above, when the activation history R is not written in the SRAM 11a but the counter value CNT exceeds the set value Ns (S320: NO and S340: YES), When the activation history R is written in the SRAM 11a, but the counter value CNT does not exceed the set value Ns (S320: YES and S330: NO), it is determined that an abnormality has occurred in the timer IC 13 It has become.

  That is, in the ECU 1 according to the first embodiment, as an abnormality determination of the timer IC 13, an abnormality occurs in the timer IC 13 when the counter value CNT exceeds the set value Ns even though the activation history R is not written in the SRAM 11a. A first determination process for determining that the timer IC 13 is abnormal when the activation history R is written in the SRAM 11a and the counter value CNT does not exceed the set value Ns. 2 is executed.

  In the ECU 1, when the microcomputer 11 activated by the timer IC 13 does not write the activation history R in the SRAM 11a (that is, when it is determined that the write prohibition signal WI is at a low level (S130: YES)), When the operation of the microcomputer 11 ends, the counter value is reset (S180).

  Therefore, for example, if the microcomputer 11 is activated by the IGSW 19 before the counter value of the timer IC 13 reaches the set value Ns, for example, the counter value CNT is set even though the activation history R is not written in the SRAM 11a. There is no contradiction in the first determination process that the value Ns is exceeded.

  Furthermore, in the ECU 1 of the present embodiment, when the microcomputer 11 activated by the timer IC 13 writes the activation history R in the SRAM 11a (that is, when it is determined that the write inhibit signal WI is at a high level (S130: NO)). In this case, since the counter value is not reset, inconsistency may occur in the second determination process in which the counter value CNT does not exceed the set value Ns even though the activation history R is written in the SRAM 11a. Absent.

  Therefore, according to the present ECU 1, it is possible to prevent erroneous determination that an abnormality has occurred in the timer IC 13 although the timer IC 13 is operating normally.

  In S120 of FIG. 3, whether or not the timer IC 13 is activated is determined based on the power supply activation signal SK, but may be determined based on the IGSW signal SIG. In this case, the microcomputer 11 determines that the timer IC 13 is activated when the IGSW signal SIG is at a low level. In the first embodiment, the process of S120 corresponds to the activation reason determination process, the process of S140 corresponds to the activation history storage process, and the processes of S320 to S370 correspond to the abnormality detection process. And the process of S130 is equivalent to a detection means, and the process of S160-S180 is equivalent to a starting invalid means.

  Next, the ECU of the second embodiment will be described with reference to FIGS. FIG. 7 is a block diagram showing the configuration of the ECU 2 of the second embodiment, and FIG. 8 is a block diagram showing the configuration of the power supply circuit 27 for supplying the power supply voltage Vs3 to the timer IC 13 of the ECU 2. In FIGS. 7 and 8, the same components and signals as those of the ECU 1 of the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted. This also applies to a third embodiment described later.

The ECU 2 of the second embodiment differs from the ECU 1 of the first embodiment in the following points (1) to (4).
(1) If the microcomputer 11 determines in S120 of FIG. 3 that the timer IC 13 is activated (S120: YES), the process proceeds to S140 without performing the process of S130. That is, when the microcomputer 11 is started by the timer IC 13, even if the write inhibit signal WI is at a low level, the microcomputer 11 gives a “counter clear instruction” to the timer IC 13 when the microcomputer 11 ends its operation. Do not send.

  (2) If the microcomputer 11 determines that there is the activation history R in S320 of FIG. 4 (S320: YES), the process proceeds to S350 without performing the process of S330. That is, the ECU 2 does not perform the second determination process. For this reason, if the microcomputer 11 determines that the activation history R is written in the SRAM 11a, it determines that the timer IC 13 is operating normally.

  (3) As shown in FIG. 7, the ECU 2 includes a power supply circuit 27 that supplies a power supply voltage Vs3 to the timer IC 13. That is, in the ECU 1 of the first embodiment, the sub power supply voltage Vs2 from the second sub power supply unit 15c is supplied to the timer IC 13. However, in the present ECU 2, the power supply voltage Vs3 from the power supply circuit 27 is supplied to the timer IC 13. It is supposed to be.

  Then, as shown in FIG. 8, the power supply circuit 27 includes resistors Ra and Rb that divide the battery voltage VBAT, resistors Rc and Rd that divide the sub power supply voltage Vs2 generated from the second sub power supply unit 15c, The comparator 27a that compares the divided voltage Vo generated at the connection point of the voltage dividing resistors Ra and Rb and the divided reference voltage Vref generated at the connection point of the voltage dividing resistors Rc and Rd and the output signal SC from the comparator 27a are high. In the case of the level, a power supply unit 27b that generates a power supply voltage Vs3 of 5 [V] from the battery voltage VBAT and supplies the power supply voltage Vs3 to the timer IC 13 is provided.

The comparator 27a outputs a high-level output signal SC to the power supply unit 27b if “Vo ≧ Vref”.
Therefore, the power supply unit 27b does not supply the power supply voltage Vs3 to the timer IC 13 if “Vo <Vref”, and supplies the power supply voltage Vs3 to the timer IC 13 if “Vo ≧ Vref”.

  Further, the resistance ratio of the resistors Ra and Rb and the resistance ratio of the resistors Rc and Rd are set to a voltage higher than the voltage at which the battery voltage VBAT cannot accurately perform the operation of the microcomputer 11 writing data into the SRAM 11a. For example, “Ra: Rb = 1: 1”, “Rc: Rd” so that “Vo <Vref” when the voltage drops below the set voltage Vb (6 [V] in the second embodiment). = 2: 3 ".

For this reason, in the present ECU 2, when the battery voltage VBAT drops below 6 [V], the power supply circuit 27 does not supply the power supply voltage Vs 3 to the timer IC 13.
(4) Further, the timer IC 13 is configured such that the counter value is reset when the power supply voltage Vs3 becomes lower than the minimum operating voltage Vt at which the timer IC 13 can operate. In the second embodiment, the minimum operating voltage Vt of the timer IC 13 is 3.5 [V].

  In such an ECU 2, when the battery voltage VBAT falls below the set voltage Vb and the divided voltage Vo falls below the divided reference voltage Vref, the output signal SC from the comparator 27a becomes low level, and the power supply Since the supply unit 27b does not supply the power supply voltage Vs3 to the timer IC 13, the timer IC 13 resets the counter value and stops its own operation.

  For this reason, since the microcomputer 11 is not activated by the timer IC 13 in a situation where the operation of writing the activation history R in the SRAM 11a cannot be performed accurately, if the timer IC 13 operates normally, the microcomputer 11 When activated by the IGSW 19, there is no inconsistency that the counter value CNT exceeds the set value Ns even though the activation history R is not written in the SRAM 11a.

  Therefore, it is possible to prevent the processing of S320 and S340 in FIG. 4 from erroneously determining that an abnormality has occurred in the timer IC 13 even though the timer IC 13 is operating normally.

  In the second embodiment, S320 and S340 to S370 in FIG. 4 correspond to abnormality detection processing, the power supply unit 27b corresponds to the first power supply circuit, and the resistors Ra to Rd and the comparator 27a are reset. Corresponds to means.

Next, the ECU 3 of the third embodiment will be described.
As shown in FIG. 7, the ECU 3 of the third embodiment includes a power supply circuit 29 instead of the power supply circuit 27 as compared with the ECU 2 of the second embodiment.

  As shown in FIG. 9, the power supply circuit 29 has resistors R1 and R2 that divide the battery voltage VBAT, one end connected to a connection point between the voltage dividing resistors R1 and R2, and the other end connected to the power supply terminal of the timer IC 13. A resistor R3 connected to VDD, a Zener diode ZD having a cathode connected between the resistor R3 and the power supply terminal VDD of the timer IC 13, and an anode connected to the ground potential, and a power supply terminal VDD of the Zener diode ZD and the timer IC 13 And a capacitor C1 having one end connected to the ground and the other end connected to the ground potential.

In this embodiment, a Zener diode ZD having a Zener voltage Vz of 5 [V] is used.
In addition, the resistance ratio between the resistor R1 and the resistor R2 is such that the battery voltage VBAT is set to a set voltage Vc that is set to a voltage higher than a voltage at which the microcomputer 11 cannot accurately perform the operation of writing data to the SRAM 11a. In the third embodiment, when the voltage drops below 5.6 [V]), the power supply voltage Vs4 supplied to the timer IC 13 is less than 3.5 [V] which is the minimum operating voltage Vt of the timer IC 13. For example, “R1: R2 = 3: 5” is set.

  In such an ECU 3, when the battery voltage VBAT is lower than the set voltage Vc, the power supply circuit 29 supplies only the power supply voltage Vs4 smaller than the minimum operating voltage Vt to the timer IC 13, and the timer IC 13 has its own counter value. Will be reset and its operation will be stopped.

For this reason, the effect similar to ECU2 of 2nd Embodiment can be acquired.
By the way, when the ECU 3 and the ECU 2 of the second embodiment are configured to perform not only the first determination process but also the second determination process, like the ECU 1 of the first embodiment described above, the second determination is performed. There is a possibility of misjudgment in the processing. More specifically, in the ECUs 2 and 3, if the battery voltage VBAT drops below the set voltage Vb after the microcomputer 11 activated by the timer IC 13 ends its operation, the counter value of the timer IC 13 is reset. Therefore, after that, when the microcomputer 11 is activated by the IGSW 19, there is a contradiction that the counter value CNT does not exceed the set value Ns even though the activation history R is written in the SRAM 11a. is there.

For this reason, the ECU 1 of the first embodiment is more advantageous than the ECUs 2 and 3 because it can more reliably determine the presence or absence of an abnormality.
In the third embodiment, the resistors R1 and R2 correspond to the reset means, and the resistor R3, the Zener diode ZD, and the capacitor C1 correspond to the first power supply circuit.

As mentioned above, although one Embodiment of this invention was described, it cannot be overemphasized that this invention can take a various form.
In this embodiment, the startup history R, the diagnosis result of the evaporation diagnosis process, the flag FA, and the diagnosis code are written in the SRAM 11a. However, the present invention is not limited to the SRAM 11a, and the data can be rewritten and the data can be retained. Other memories such as EEPROM and flash ROM may be used.

  Further, the set voltages Vb and Vc of the ECU 2 and ECU 3 may be any voltage as long as the microcomputer 11 can accurately write data in the SRAM 11a. In this case, the set voltages Vb and Vc can be changed by changing the ratio of the voltage dividing resistors.

It is a block diagram showing the electronic controller (ECU) of 1st Embodiment. 3 is a time chart for explaining the operation of a write inhibit signal (WI) in the ECU. It is a flowchart showing the process which the microcomputer in the ECU performs. FIG. 4 is a flowchart illustrating a process executed by the ECU and executed in parallel with the process of FIG. 3. It is a time chart explaining the normal operation of the ECU. It is a time chart explaining the effect | action at the time of abnormality of the ECU. It is a block diagram showing ECU of 2nd Embodiment and 3rd Embodiment. It is a block diagram showing the power supply circuit of ECU of 2nd Embodiment. It is a block diagram showing the power supply circuit of ECU of 3rd Embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Electronic control unit (ECU), 11 ... Microcomputer, 11a ... RAM (SRAM), 13 ... Timer IC, 13a ... Counter, 15 ... Power supply circuit, 15a ... Main power supply part, 15b ... First sub power supply part, 15c ... Second auxiliary power supply unit, 17 ... battery, 19 ... ignition switch (IGSW), 21 ... main relay, 23 ... input circuit, 25 ... main relay control circuit, 27, 29 ... power supply circuit, 27a ... comparator, 27b ... Power supply unit, Ra to Rd, R1 to R3... Resistor, ZD... Zener diode, C1.

Claims (4)

A timer circuit that operates by a power supply voltage constantly output from the first power supply circuit and performs a counting operation;
A second power supply circuit that outputs a power supply voltage when a power switch is turned on or an operation command signal generated inside the device is at an active level;
A microcomputer that operates with a power supply voltage output from the second power supply circuit,
When the count value of the timer circuit reaches a preset value in a state where no power supply voltage is output from the second power supply circuit, the operation command signal from the timer circuit to the second power supply circuit Becomes the active level and the power supply voltage is output from the second power supply circuit, whereby the microcomputer is activated,
When the microcomputer starts operating upon receiving the power supply voltage from the second power supply circuit, the microcomputer performs start-up reason determination processing for determining whether the current start is due to the power switch or the timer circuit. When the activation reason is determined by the timer circuit as a result of the activation reason determination process, an activation history storage process for storing an activation history indicating activation by the timer circuit in a storage unit is performed, and a specific Only until the processing is completed, the operation command signal to the second power supply circuit is kept at the active level to maintain the state in which the power supply voltage is output from the second power supply circuit, and conversely the activation reason determination processing If it is determined that the current activation is due to the power switch, the timing is based on the activation history in the storage means and the count value of the timer circuit. Performing an abnormality detection process to determine whether or not the function of the circuit is abnormal,
Further, in the electronic control device configured to output the respective power supply voltages by the battery voltage supplied from the battery, the first power supply circuit and the second power supply circuit,
The timer circuit counts when the battery voltage falls below a set voltage set to a voltage at which the microcomputer cannot accurately store information in the storage means or a voltage higher than that. Having reset means for resetting the value;
An electronic control device. The electronic control device according to claim 1.
The timer circuit is configured such that the count value is reset when the power supply voltage from the first power supply circuit is lower than the lowest operating voltage at which the timer circuit can operate,
The reset means resets the count value of the timer circuit by prohibiting the supply of the power supply voltage from the first power supply circuit to the timer circuit when the battery voltage drops to the set voltage. To do,
An electronic control device. The electronic control device according to claim 1.
The timer circuit is configured such that the count value is reset when the power supply voltage from the first power supply circuit is lower than the lowest operating voltage at which the timer circuit can operate,
The reset means is configured such that when the battery voltage drops to the set voltage, the power supply voltage supplied from the first power supply circuit to the timer circuit is lower than the minimum operating voltage. Resetting the count value of the timer circuit;
An electronic control device. A timer circuit that operates by a power supply voltage constantly output from the first power supply circuit and performs a counting operation;
A second power supply circuit that outputs a power supply voltage when a power switch is turned on or an operation command signal generated inside the device is at an active level;
A microcomputer that operates with a power supply voltage output from the second power supply circuit,
When the count value of the timer circuit reaches a preset value in a state where no power supply voltage is output from the second power supply circuit, the operation command signal from the timer circuit to the second power supply circuit Becomes the active level and the power supply voltage is output from the second power supply circuit, whereby the microcomputer is activated,
When the microcomputer starts operating upon receiving the power supply voltage from the second power supply circuit, the microcomputer performs start-up reason determination processing for determining whether the current start is due to the power switch or the timer circuit. When the activation reason is determined by the timer circuit as a result of the activation reason determination process, an activation history storage process for storing an activation history indicating activation by the timer circuit in a storage unit is performed, and a specific Only until the processing is completed, the operation command signal to the second power supply circuit is kept at the active level to maintain the state in which the power supply voltage is output from the second power supply circuit, and conversely the activation reason determination processing If it is determined that the current activation is due to the power switch, the timing is based on the activation history in the storage means and the count value of the timer circuit. The electronic control unit configured as function of the circuit is performing the abnormality detection process that determines whether the abnormality,
The power supply voltage supplied to the microcomputer from the second power supply circuit is reduced to a specific voltage that is set to a voltage value or higher at which the microcomputer cannot accurately perform the operation of storing information in the storage means. Detecting means for detecting
When the operation command signal from the timer circuit to the second power supply circuit becomes an active level and the microcomputer starts operating, the detection means supplies the microcomputer to the microcomputer from the second power supply circuit. If it is detected that the power supply voltage has dropped to the specific voltage, the microcomputer is prohibited from performing the startup history storage process, and the operation of the microcomputer is terminated, and A start invalid means for resetting the count value of the timer circuit;
An electronic control device comprising:

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