JP2005224093A - Pulse width modulation inverter and its control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problems of a pulse width modulation inverter that switching of a carrier frequency signal, at a time when the number of pulses contained in the fundamental wave component of an output waveform is small, causes the current ripple to change suddenly; switching of the carrier frequency in a low frequency area becomes frequent, resulting in larger magnetic noise. <P>SOLUTION: When the number of pulses at intervals of a half cycle contained in the fundamental wave component of an output waveform is either less than or not more than a preset optional value, a reference carrier frequency signal fbb, a reference wave modulation frequency signal fs, and one or plural numbers of computing element signals for frequency correction are input, the carrier setting frequency signal fbc of asynchronous pulse width modulation for conducting appropriate frequency correction is output. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a pulse width modulation inverter device, and relates to a pulse width modulation inverter device capable of converting power from DC power to AC power by pulse width modulation based on amplitude comparison between a fundamental wave modulation frequency signal fs and a carrier frequency signal fb. It relates to the control method.

  In the method of controlling the output waveform of the pulse width modulation inverter device, the amplitudes of the fundamental frequency modulation frequency signal fs constituting the fundamental wave component of the output waveform and the carrier frequency signal fb constituting the pulse width of the output waveform are compared. From the result, an output waveform quantized and modulated in pulse width is obtained. When performing output waveform control by this pulse width modulation, there is an asynchronous pulse width modulation control which is not synchronized with a synchronous pulse width modulation control in which the fundamental wave modulation frequency signal fs and the carrier frequency signal fb are synchronized.

  FIG. 7 is a circuit configuration diagram of a pulse width modulation inverter device in the prior art, which will be described below by dividing it into a main circuit configuration and a control circuit configuration.

  The main circuit configuration is that an AC power source (for example, a three-phase AC power source shown in the figure) 1 is connected to a forward converter circuit (eg, a forward converter circuit by diode rectification shown in the figure) 2 to obtain DC power and this DC power is reversed A conversion circuit (for example, an inverse conversion circuit using an IGBT inverter shown in the figure) 4 outputs AC power having an arbitrary voltage and frequency to a load facility (commercial power supply, electric motor, etc.) 5. In order to reduce and smooth the pulsation contained in the output waveform of the forward conversion circuit 2, a DC capacitor 3 is connected in parallel with the circuit in the DC circuit portion. The method for obtaining DC power is not limited to the method for obtaining DC power from the AC power source 1 described above via the forward conversion circuit 2, but also power storage equipment such as a storage battery and a large capacity capacitor (not shown), a DC generator, DC power generation equipment such as photovoltaic power generation equipment may be used.

  On the other hand, the control circuit configuration outputs a carrier frequency signal fb having an arbitrary frequency to the carrier signal generation circuit 10, and outputs a carrier waveform signal fbd having an arbitrary waveform shape to the comparator circuits 12a, 12b, and 12c. Further, a fundamental wave modulation frequency signal fs having an arbitrary frequency is output to a voltage-frequency output characteristic setting device (hereinafter referred to as V / F setting device) 8 and a phase integrator 9. The V / F setting unit 8 outputs an output voltage setting signal Vref set in advance so as to correspond to the inputted fundamental wave modulation frequency signal fs, and the phase integrator 9 makes the inputted fundamental wave modulation frequency signal fs three-phase balanced. The phase setting signal yoref is output to the three-phase fundamental wave generator 14 to output the fundamental wave modulation frequency signals fsu, fsv, fsw of each phase. The product signals of the output voltage setting signal Vref and the fundamental wave modulation frequency signals fsu, fsv, fsw of each phase are obtained by multipliers 13a, 13b, 13c, and the amplitude comparison of this product signal and the carrier waveform signal fbd is performed for each phase. Performed by the comparators 12a, 12b, and 12c to obtain a pulse width modulation signal. Each of the semiconductor elements (15a, 15b, 15c, 15d, 15e, 15f) is obtained as a semiconductor element drive signal (Gu, Gx, Gv, Gy, Gw, Gz) in which the pulse width modulation signal is added to the dead time generation circuit 11 in consideration of the dead time. ).

  Next, the operation of the conventional pulse width modulation control will be described. In the synchronous pulse width modulation control, since the fundamental frequency modulation frequency signal fs and the carrier frequency signal fb are synchronized, the fundamental wave component of the output waveform is symmetrical every half cycle, and the load to be connected (such as a commercial power supply or an electric motor) Is a three-phase alternating current, the ratio of the carrier frequency signal fb to the fundamental wave modulation frequency signal fs (hereinafter referred to as the ratio of fb / fs) is set to an odd multiple integer ratio of 3 in order to make the output waveform three-phase balanced. For this reason, as the frequency of the fundamental wave modulation frequency signal fs increases, the switching frequency also increases. The switching frequency allowed by the semiconductor element, or the switching frequency set in advance by the circuit design and the limitation of the load to be connected (hereinafter referred to as arbitrary switching frequency). In the case of exceeding the frequency), the carrier frequency signal fb is lowered to a frequency at which the ratio of fb / fs becomes an odd multiple integer ratio of 3 to reduce the number of pulses of the output waveform.

On the other hand, in the asynchronous pulse width modulation control, since the carrier frequency signal fb is constant regardless of the fundamental wave modulation frequency signal fs, the configuration of the control circuit is simple and the circuit scale is relatively small, and the fundamental wave of the output waveform There is little change in the timbre of magnetic noise generated when the component is in the low frequency region.
JP-A-9-261966 IEEJ Technical Report No.635 “Latest Technical Trend of PWM Inverter Control System”

  In the above prior art, synchronous pulse width modulation control guarantees waveform symmetry and three-phase balance in the fundamental component of the output waveform, and asynchronous pulse width modulation control ensures that the fundamental component of the output waveform is in the low frequency region. Although it has excellent advantages such as reduction of generated magnetic noise, it has the following problems.

  In the pulse width modulation inverter device, the synchronous pulse width modulation control is appropriately switched to a carrier frequency signal fb having an odd multiple integer ratio of 3 with a ratio of fb / fs as the fundamental wave modulation frequency signal fs changes. The frequency is controlled so as not to exceed the switching frequency. However, when the carrier frequency signal fb is switched when the number of pulses per half cycle contained in the fundamental wave component of the output waveform is small, the change in pulse width is large and the current ripple changes suddenly, which may be excessive depending on the state of the connected load. Protective relays such as a current protective relay may inadvertently operate and the device may stop. Further, when the fundamental wave component of the output waveform is in the low frequency region, the carrier frequency signal fb is raised to suppress the generation of low-order harmonics and the decrease in control accuracy, but the ratio of fb / fs is large and slightly Since the carrier frequency signal fb greatly increases with the increase of the fundamental wave modulation frequency signal fs, the carrier frequency signal fb is frequently switched, and the magnetic noise to the surroundings is large, which is very disturbing.

  On the other hand, in the asynchronous pulse width modulation control, the waveform symmetry for each half cycle is not guaranteed unless the ratio of fb / fs is an integer ratio, and the ratio of fb / fs is 3 when the connected load is a three-phase alternating current. Other than the odd multiple ratio, three-phase equilibrium is not guaranteed. For this reason, when the number of pulses per half cycle contained in the fundamental wave component of the output waveform is small, the waveform symmetry and the three-phase balance deteriorate significantly, and the output waveform contains a large amount of pulsation and the output waveform The fundamental wave component becomes unbalanced. As a result, the characteristics of the connected load may be degraded, failure or damage, or the leakage current flowing through the grounding wire of the device will increase, and protective relays such as a leakage detector will operate and the device will stop carelessly. is there. Also, when fb / fs <20 and close to an integer, and the fundamental wave component of the output waveform is operated in a high frequency region, magnetic noise is generated that becomes a swell sound with a slow cycle.

  The present invention has been made in view of the above circumstances, and is excellent in an output waveform control method in a pulse width modulation inverter device, has little pulse width change and output waveform pulsation due to switching of the carrier frequency signal fb, and outputs. By suppressing the magnetic noise, which is a swell sound with a slow period, generated when the fundamental component of the waveform is almost balanced, and when the protective relays are inadvertently stopped, the magnetic noise It is an object of the present invention to provide a pulse width modulation inverter device that can stably supply power to a connected load and a control method thereof.

A first aspect of the present invention for solving the above problems is a pulse width capable of converting power from DC power to AC power by pulse width modulation based on amplitude comparison between the fundamental wave modulation frequency signal fs and the carrier frequency signal fb. In the modulation inverter device,
The fundamental frequency modulation frequency signal fs, the reference carrier frequency signal fbb, and one or a plurality of calculation element signals for frequency correction are input, a carrier frequency calculation unit for performing frequency correction is provided, and a pulse width modulation inverter Asynchronous pulse width modulation control that appropriately performs frequency correction when the number of pulses per half cycle included in the fundamental wave component of the output waveform of the device is less than or less than a preset arbitrary value Is.
According to a second aspect of the present invention, when the number of pulses per half cycle included in the fundamental wave component of the output waveform of the pulse width modulation inverter device is less than or less than a preset arbitrary value, By inputting the frequency signal fbb, the fundamental wave modulation frequency signal fs, the carrier correction frequency signal fbo, and the common divisor correction value flg, the carrier setting frequency signal fbc for asynchronous pulse width modulation for performing frequency correction as appropriate is calculated by the following equation: It is characterized by doing.

fbc = INT (fbb / fs) .fs + fbo + flg (1)
INT (fs / fbo) · when fbo = fs, flg = 1 (2)
When INT (fs / fbo) · fbo ≠ fs, flg = 0 (3)
According to a third aspect of the present invention, when the number of pulses per half cycle included in the fundamental wave component of the output waveform of the pulse width modulation inverter device is less than or less than a predetermined value, the fundamental frequency is input to the carrier frequency calculation unit. A carrier correction frequency coefficient kos with a fixed value (fbo / fs) of the carrier correction frequency signal fbo to the modulation frequency signal fs, the reference carrier frequency signal fbb, and the fundamental wave modulation frequency signal fs is input and frequency correction is performed as appropriate. The carrier setting frequency signal fbc for asynchronous pulse width modulation is calculated by the following equation.

fbc = INT (fbb / fs) · fs + {INT (fs · kos) +1} (4)
fbo = INT (fs · kos) (5)
A fourth aspect of the present invention is characterized in that a carrier smoothing unit is provided on the output side of the carrier frequency calculation unit, and the carrier setting frequency signal fbc is smoothed by the carrier smoothing unit.
A fifth aspect of the present invention is characterized in that the carrier smoothing unit performs a change rate limiting process on the unit step input of the carrier set frequency signal fbc.
A sixth aspect of the present invention is characterized in that the carrier smoothing unit performs a first-order lag filter process on the carrier set frequency signal fbc.
A seventh aspect of the present invention is a pulse width modulation inverter device that converts power from DC power to AC power by pulse width modulation based on amplitude comparison between a fundamental frequency modulation frequency signal and a carrier frequency signal.
A carrier frequency calculation unit for generating a carrier setting frequency signal by inputting the fundamental wave modulation frequency signal, a reference carrier frequency signal, and a carrier correction frequency signal which is a calculation element consisting of one or more for correction, is provided. The output signal of the carrier frequency calculation unit is configured to be a carrier waveform signal via the carrier signal generation unit.
According to an eighth aspect of the present invention, the carrier frequency calculation unit includes a divider that obtains a ratio signal between the fundamental modulation frequency signal and the reference carrier frequency signal, and an integer output unit that obtains an integer signal by rounding off the decimal part of the ratio signal. And a multiplier for obtaining a product signal of the integer signal from the integer output unit and the reference carrier frequency signal, and a common signal 1 obtained by adding the carrier correction frequency signal and the common divisor correction value flg determined by the determination calculation value. And a second adder that obtains a sum signal 2 by adding the sum signal 1 and the product signal of the multiplier.
According to a ninth aspect of the present invention, the carrier frequency calculation unit includes a divider that obtains a ratio signal between the fundamental wave modulation frequency signal and the reference carrier frequency signal, and a first that obtains an integer signal by rounding off the decimal part of the ratio signal. An integer output unit; a first multiplier for obtaining a product signal of the integer signal from the integer output unit and the reference carrier frequency signal; and a product of the fundamental modulation frequency signal and a predetermined carrier correction frequency coefficient A second multiplier that obtains a signal; a second integer output unit that obtains an integer signal by truncating the fractional part of the product signal; and a first adder that adds an output signal from the integer output unit and a constant 1 And a second adder for adding the output of the adder and the output signal of the first multiplier.
According to a tenth aspect of the present invention, a carrier smoothing unit having a change rate limiting processing function or a first-order lag filter processing function for a unit step input of a carrier set frequency signal is provided on the output side of the carrier frequency calculator. The obtained carrier smoothing set frequency signal is output to the carrier signal generator.

  As described above, according to the pulse width modulation inverter device and the control method thereof of the present invention, there is no frequency limitation due to switching of the carrier frequency fb, and the carrier set frequency that is the asynchronous pulse width modulation control with appropriate frequency correction. When the number of pulses per half cycle contained in the fundamental wave component of the output waveform is small due to the signal fbc, the change in pulse width is small even when the carrier frequency signal fb is switched, so that a sudden change in current ripple can be suppressed and output can be suppressed. The waveform symmetry and the three-phase balance of the fundamental wave component of the waveform can be ensured by considering the average of multiple periods. In addition, these effects can suppress magnetic noise caused by a low-frequency beat sound generated in the high frequency region, and can also suppress a leakage current flowing through the ground wire. Therefore, a stable power supply to the load connected to the apparatus can be realized by the above-described plurality of effects.

The present invention controls a carrier frequency in a pulse width modulation inverter device that drives an AC motor as a load so that the ratio of the carrier frequency and the sine wave modulation signal in the control circuit does not become an integer. . Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a control circuit configuration diagram of the pulse width modulation inverter device according to the first embodiment of the present invention, and the main circuit portion is the same as the main circuit portion composed of 2 to 4 and 15a to 15f shown in FIG. In the following description, it is omitted. This apparatus operates when the number of pulses included in the fundamental wave component of the output waveform is less than or less than a preset value. When the number of pulses is other than the set value described above, the control circuit section is also shown in FIG. Since it is the same as 8-14 shown, it abbreviate | omits.

  The control circuit configuration diagram shown in FIG. 1 outputs the fundamental wave modulation frequency signal fs set to an arbitrary frequency to the carrier frequency calculation unit 107, the V / F setting unit 108, and the phase integrator 109. The carrier frequency calculation unit 107 inputs the fundamental wave modulation frequency signal fs, the reference carrier frequency signal fbb of an arbitrary frequency, and one or more calculation element signals for frequency correction, and the carrier setting frequency signal fbc. Is generated. This carrier setting frequency signal fbc is output to the carrier signal waveform generation circuit 110 as a carrier signal that performs asynchronous pulse width modulation that is not synchronized with the fundamental wave modulation frequency signal fs corrected to a frequency as appropriate. In the carrier signal waveform generation circuit 110, the carrier setting frequency signal fbc is output to the comparators 112a, 112b, and 112c provided for each phase as a carrier waveform signal fbd having a waveform for comparing the amplitude with the fundamental wave modulation frequency signal fs. To do. The V / F setting unit 108 outputs an output voltage setting signal Vref set in advance so as to correspond to the inputted fundamental wave modulation frequency signal fs, and the phase integrator 109 sets the inputted fundamental wave modulation frequency signal fs to a three-phase balance. Is output to the three-phase fundamental wave generation unit 114 as the phase setting signal Yoref, and the fundamental wave modulation frequency signals fsu, fsv, fsw of each phase are outputted. A product signal of the output voltage setting signal Vref and the fundamental wave modulation frequency signals fsu, fsv, and fsw of each phase is obtained from multipliers 113a, 113b, and 113c, and the product signal and the carrier waveform signal fbd are compared with the comparators 112a and 112b. 112c, an amplitude comparison calculation process is performed to obtain an asynchronous pulse width modulation signal. This asynchronous pulse width modulation signal is used as a semiconductor element drive signal (Gu, Gx, Gv, Gy, Gw, Gz) in which the dead time is added by the dead time generation circuit 111, so that each semiconductor element (115a, 115b, 115c, 115d, 115e, 115f).

  FIG. 2 is a control block diagram of the carrier frequency calculation unit 107 used in the present invention, which operates when the number of pulses included in the fundamental wave component of the output waveform is less than or less than a preset value.

  That is, the fundamental frequency modulation frequency signal fs, the reference carrier frequency signal fbb, the carrier correction frequency signal fbo, and the common divisor correction value flg are input to the carrier frequency calculation unit 207, and the reference carrier frequency signal fbb and the fundamental wave modulation frequency are input by the divider 216. A ratio signal with respect to the signal fs is obtained, an integer signal rounded down by an integer output unit (INT) 217 is obtained, and a product signal of the integer signal and the fundamental modulation frequency signal fs is obtained by a multiplier 218. In addition, it is determined whether or not the carrier correction frequency signal fbo is a common divisor of the fundamental wave modulation frequency signal fs. When the carrier correction frequency signal fbo is a common divisor, the common divisor correction value flg is “1”, and when it is not a common divisor. By inputting “0”, the adder 219 obtains a sum signal 1 obtained by adding the common divisor correction value flg to the carrier correction frequency signal fbo. Further, an asynchronous pulse width for which frequency correction is appropriately performed by a carrier setting frequency signal fbc obtained by adding the product signal obtained by the multiplier 218 and the sum signal 1 obtained by the adder 219 by an adder 220 different from the above. The output waveform can be controlled by modulation. A series of these control calculations is shown in the calculation formula (1). In FIG. 2, the calculation element signals 1 to n in FIG. 1 are set as the carrier correction frequency signal fbo and the common divisor correction value flg, and the determination calculation of the common divisor correction value flg is represented by calculation expressions (2) and (3). .

fbc = INT (fbb / fs) .fs + fbo + flg (1)
INT (fs / fbo) · when fbo = fs, flg = 1 (2)
When INT (fs / fbo) · fbo ≠ fs, flg = 0 (3)
“INT” included in the above arithmetic expression is an arithmetic function in a computer language, and a value after the decimal point is rounded down and only an integer is output with respect to an expression in parentheses indicated by INT.

  Therefore, according to the pulse width modulation inverter device of the first embodiment, the number of pulses is small because there is no frequency limitation by switching the carrier frequency and the asynchronous pulse width modulation control appropriately corrects the frequency of the carrier setting frequency signal fbc. In addition to suppressing sudden changes in current ripple at the same time, the fundamental wave component of the output waveform of each phase is almost balanced and has little pulsation, so it is possible to suppress slow-period magnetic noise that occurs in the high-frequency region and to suppress leakage current flowing through the ground wire Can be realized. Also, frequency correction can be realized when the correction frequency signal fbo is a common divisor of the fundamental wave modulation frequency signal fs.

FIG. 3 is a control block diagram of the carrier frequency calculation unit according to the second embodiment of the present invention, in which the number of pulses included in the fundamental wave component of the output waveform is preset.
Operates when below or below the value.
The carrier frequency calculation unit 307 shown in FIG. 3 includes a carrier having a fixed value of the ratio (fbo / fs) of the carrier correction frequency signal fbo to the fundamental wave modulation frequency signal fs, the reference carrier frequency signal fbb, and the fundamental wave modulation frequency signal fs. A correction frequency coefficient kos and a constant 1 are input. A divider 316 obtains a ratio signal between the reference carrier frequency signal fbb and the fundamental wave modulation frequency signal fs, and an integer output unit (INT) 317 obtains an integer signal 1 obtained by rounding down the decimal point. A product signal 1 with the carrier frequency signal fbb is obtained from a multiplier 318. Further, a product signal 2 of the fundamental wave modulation frequency signal fs and the carrier correction frequency coefficient kos is obtained by a multiplier 321 different from the above, and this product signal 2 is converted into a decimal point by an integer output device (INT) 322 different from the above. Thereafter, the rounded-down integer signal 2 is obtained, and the sum signal 1 obtained by adding the constant 1 to the integer signal 2 is obtained from the adder 319. Further, the sum signal 2 obtained by adding the sum signal 1 obtained by the multiplier 318 and the sum signal 1 obtained by the adder 319 by the adder 320 different from the above becomes the carrier setting frequency signal fbc, and frequency correction is appropriately performed. The output waveform can be controlled by asynchronous pulse width modulation. A series of these control calculations is shown by an arithmetic expression (4), and a definition expression of the carrier correction frequency coefficient kos is shown by an arithmetic expression (5).

fbc = INT (fbb / fs) · fs + {INT (fs · kos) +1} (4)
fbo = INT (fs · kos) (5)
Except for the control calculation for obtaining the carrier set frequency signal fbc in the second embodiment, the invention can be implemented by the same circuit configuration and control method as in the first embodiment, and the main circuit configuration and the number of pulses However, the control circuit configuration other than the set values described above is the same as the conventional circuit configuration shown in FIG.

  Therefore, according to the output waveform control method of the second embodiment, in addition to having the same effect as that of the first embodiment, the common divisor determination operation is not performed with the fbo / fs ratio as the carrier correction frequency coefficient kos. Compared with the first embodiment, it is possible to realize control with higher response.

FIG. 4 is a control circuit configuration diagram of the pulse width modulation inverter device according to the third embodiment of the present invention. In the case of the first and second embodiments, the calculation result of INT (fbb / fs) is not as high as that of the conventional synchronous modulation system due to the increase or decrease of fs, but the occurrence of current ripple due to the change of the pulse width is slightly expected. Therefore, in this third embodiment, the calculation result is not directly set to fb, but a carrier having a function of processing an input signal by a time function such as a change rate limiting processing circuit or a first-order lag filter circuit on the output side of the carrier frequency calculation unit 407. A smoothing unit 423 is provided, and a carrier set frequency signal fbc obtained by the same control method as in the first or second embodiment is input to the carrier smoothing unit 423 to obtain an output fch (carrier frequency signal fb). .
FIG. 5 shows an example of the carrier smoothing unit 423 used in FIG. 4, FIG. 5 (a) is a control block diagram when the change rate limiting process is performed, and FIG. 5 (b) is a first-order lag filter. It is a control block diagram at the time of performing a process. In FIG. 5A, reference numeral 423a denotes a subtraction unit that performs subtraction with the previous output value stored in the input signal fbc memory unit 423c, and outputs the deviation signal to the limiter unit 423b. In the limiter unit, the rate of change is limited to ± 1.0 / (Tf / Ts) with respect to the unit step input (size 1.0) and output to the adding unit 423d. This adding unit adds the previous output value and outputs the result to the carrier signal generation circuit 410 as the carrier smoothing set frequency signal fhc. In FIG. 5B, a first-order-lag filter unit 423e is provided in place of the limiter unit 423b in FIG. 5A to perform the calculation of Ts / Ts + Tf, and the rest is configured in the same manner as in FIG. The

  FIG. 6 shows the input / output characteristics of the carrier smoothing unit 423. In the same figure, the vertical axis is output and the horizontal axis is time, line i is the input signal, line b is the output characteristic when the change rate processing according to FIG. 5A is performed, and line c is FIG. The output characteristic by the first order lag filter process by (b) is shown. The change rate limiting process is set to allow a unit step width in 10 control cycles, and the first-order lag filter process is set to have a time constant 10 times the control cycle. In any case, since the final change in the carrier frequency becomes smooth, it is possible to further suppress the sudden change in the current ripple.

  Therefore, according to the pulse width modulation inverter device of the third embodiment and the control method thereof, the carrier smoothing unit 423 is provided in addition to the effect of reducing the pulse width change and the current ripple as in the first or second embodiment. By providing, it is possible to further suppress the occurrence of minute current ripple that occurs when the change in pulse width is small.

The control circuit block diagram of the pulse width modulation inverter apparatus concerning Embodiment 1 of this invention. The control block diagram of the carrier frequency calculating part concerning Embodiment 1 of this invention. The control block diagram of the carrier frequency calculating part concerning Embodiment 2 of this invention. The control circuit block diagram of the pulse width modulation inverter apparatus concerning Embodiment 3 of this invention. (A) is a control block diagram of the rate-of-change restriction process as an example of the carrier smoothing unit, and (b) is a control block diagram of the first-order lag filter process in the same manner. Input / output characteristic diagram of the carrier smoothing section. The main circuit block diagram and control circuit block diagram of the pulse width modulation inverter apparatus of a prior art.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... AC power source 2 ... Forward conversion circuit 3 ... DC capacitor 4 ... Inverse conversion circuit 5 ... Load equipment 8 ... Voltage-frequency output characteristic setting device (V / F setting device)
DESCRIPTION OF SYMBOLS 9 ... Phase integrator 10 ... Carrier signal generation circuit 11 ... Dead time creation circuit 12a ... Comparator (U phase)
12b: Comparator (V phase)
12c: Comparator (W phase)
13a: Multiplier (U phase)
13b: Multiplier (V phase)
13c: Multiplier (W phase)
14: Three-phase fundamental wave generator 15a: Semiconductor element (U phase)
15b ... Semiconductor element (X phase)
15c: Semiconductor element (phase V)
15d: Semiconductor element (Y phase)
15e: Semiconductor element (W phase)
15f ... Semiconductor element (Z phase)
107: Carrier frequency calculation unit 108: Voltage-frequency output characteristic setting device (V / F setting device)
DESCRIPTION OF SYMBOLS 109 ... Phase integrator 110 ... Carrier signal generation circuit 111 ... Dead time creation circuit 112a ... Comparator (U phase)
112b... Comparator (V phase)
112c: Comparator (W phase)
113a ... Multiplier (U phase)
113b ... Multiplier (V phase)
113c ... Multiplier (W phase)
114 ... Three-phase fundamental wave generator 207 ... Carrier frequency calculation unit 216 ... Divider 217 ... Integer output device (INT)
218 ... multiplier 219 ... adder 220 ... adder 307 ... carrier frequency calculation unit 316 ... divider 317 ... integer output unit (INT)
318 ... multiplier 319 ... adder 320 ... adder 321 ... multiplier 322 ... integer output device (INT)
407: Carrier frequency calculation unit 408: Voltage-frequency output characteristic setting unit 409 ... Phase integrator 410 ... Carrier signal generation circuit 411 ... Dead time generation circuit 412a ... Comparator (U phase) )
412b: Comparator (phase V)
412c: Comparator (W phase)
413a: Multiplier (U phase)
413b... Multiplier (V phase)
413c: Multiplier (W phase)
414 ... Three-phase fundamental wave generator 423 ... Carrier smoothing unit

Claims (10)

In a pulse width modulation inverter device capable of converting power from DC power to AC power by pulse width modulation based on amplitude comparison between the fundamental wave modulation frequency signal fs and the carrier frequency signal fb,
The fundamental frequency modulation frequency signal fs, the reference carrier frequency signal fbb, and one or a plurality of calculation element signals for frequency correction are input, a carrier frequency calculation unit for performing frequency correction is provided, and a pulse width modulation inverter Asynchronous pulse width modulation control that appropriately performs frequency correction when the number of pulses per half cycle included in the fundamental wave component of the output waveform of the device is less than or less than a preset arbitrary value Control method of pulse width modulation inverter device When the number of pulses per half cycle included in the fundamental wave component of the output waveform of the pulse width modulation inverter device is less than or less than a predetermined value, a reference carrier frequency signal fbb, fundamental wave modulation is sent to the carrier frequency calculation unit. The carrier set frequency signal fbc, which is an asynchronous pulse width modulation that performs frequency correction as appropriate, is input by inputting the frequency signal fs, the carrier correction frequency signal fbo, and the common divisor correction value flg, and is calculated by the following equation: Item 8. A method for controlling a pulse width modulation inverter device according to Item 1.
fbc = INT (fbb / fs) .fs + fbo + flg (1)
INT (fs / fbo) · when fbo = fs, flg = 1 (2)
When INT (fs / fbo) · fbo ≠ fs, flg = 0 (3) When the number of pulses per half cycle contained in the fundamental wave component of the output waveform of the pulse width modulation inverter device is less than or less than a preset arbitrary value, the carrier frequency calculation unit receives the fundamental wave modulation frequency signal fs and the reference carrier Asynchronous pulse width modulation for appropriately performing frequency correction by inputting a carrier correction frequency coefficient kos with a fixed value (fbo / fs) of the carrier correction frequency signal fbo to the frequency signal fbb and the fundamental modulation frequency signal fs The control method of the pulse width modulation inverter device according to claim 1, wherein the carrier setting frequency signal fbc is calculated by the following equation.
fbc = INT (fbb / fs) · fs + {INT (fs · kos) +1} (4)
fbo = INT (fs · kos) (5) 4. The method of controlling a pulse width modulation inverter apparatus according to claim 1, wherein a carrier smoothing unit is provided on an output side of the carrier frequency calculation unit, and the carrier smoothing unit smoothes the carrier set frequency signal fbc. . 5. The method of controlling a pulse width modulation inverter according to claim 1, wherein the carrier smoothing unit performs a rate-of-change limiting process on a unit step input of a carrier setting frequency signal fbc. 5. The method of controlling a pulse width modulation inverter device according to claim 1, wherein the carrier smoothing unit performs a first-order lag filtering process on a carrier set frequency signal fbc. In a pulse width modulation inverter device that converts power from DC power to AC power by pulse width modulation based on amplitude comparison between a fundamental frequency modulation frequency signal and a carrier frequency signal,
A carrier frequency calculation unit for generating a carrier setting frequency signal by inputting the fundamental wave modulation frequency signal, a reference carrier frequency signal, and a carrier correction frequency signal which is a calculation element consisting of one or more for correction, is provided. A pulse width modulation inverter device characterized in that an output signal of a carrier frequency calculation unit is configured to be a carrier waveform signal via a carrier signal generation unit. The carrier frequency calculation unit includes a divider that obtains a ratio signal between the fundamental wave modulation frequency signal and the reference carrier frequency signal, an integer output unit that obtains an integer signal by rounding off the decimal part of the ratio signal, and an integer output unit. A first multiplier that obtains a sum signal 1 by adding the carrier correction frequency signal and a common divisor correction value flg determined by a determination calculation value. 8. A pulse width modulation inverter apparatus according to claim 7, wherein the sum signal 1 and a product signal obtained by the multiplier are added to obtain a sum signal 2. The carrier frequency calculation unit includes a divider for obtaining a ratio signal between the fundamental modulation frequency signal and the reference carrier frequency signal, a first integer output unit for obtaining an integer signal by rounding off the decimal point of the ratio signal, and the integer A first multiplier for obtaining a product signal of the integer signal from the output unit and the reference carrier frequency signal; and a second multiplication for obtaining a product signal of the fundamental modulation frequency signal and a predetermined carrier correction frequency coefficient. A second integer output unit for obtaining an integer signal by rounding off the decimal part of the product signal, a first adder for adding an output signal from the integer output unit and a constant 1, and an output of the adder And a second adder for adding the output signal of the first multiplier and the output signal from the first multiplier. Provided on the output side of the carrier frequency calculator is a carrier smoothing unit having a rate-of-change limiting function or a first-order lag filter processing function for a unit step input of a carrier setting frequency signal, and the carrier smoothing setting frequency obtained by this smoothing unit 10. The pulse width modulation inverter apparatus according to claim 7, wherein the signal is output to a carrier signal generator.

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