JP2005223145A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device, wherein the effect of channel length modulation is reduced and the leak of drain output analog signals into the source is made small, and to provide a method for manufacturing the same. <P>SOLUTION: The semiconductor device has a MOS transistor 100 comprising a silicon substrate 1, a gate oxide film 15 provided on the silicon substrate 1, a gate electrode 13 provided on the gate oxide film 15, an n-type source and drain provided on the silicon substrate 1 exposed from under the gate electrode 13, and a p-type channel region positioned in between the source and the drain. The p-type channel region has a low-Vth region 29, provided at a specified location adjoining the drain and not adjoining the source, and the low-Vth region 29 contains more n-type impurities, such as phosphorus, than the other locations of the p-type channel region. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device suitable for application to a CMOS analog circuit and a manufacturing method thereof.

Conventionally, CMOS analog circuits have been used as circuits for processing analog signals such as video and audio signals. In such a CMOS analog circuit, a pMOS transistor or an nMOS transistor generally operates and is used as an analog element in its saturation region.
5A to 5C are conceptual diagrams showing a configuration example (No. 1) of a MOS transistor according to a conventional example and Vd-Id characteristics thereof.

In a conventional MOS transistor as shown in FIG. 5 (A), as shown in FIG. 5 (C), when the MOS transistor is used as an analog element in its saturation region operation, as shown in FIG. 5 (B). In addition, the pinch-off point of the inverted channel layer is inevitably formed in the vicinity of the high concentration drain end.
In this state, when an analog signal is applied to the drain, fluctuations in the drain voltage (Vds) cause potential fluctuations at the nearest pinch-off point, and the pinch-off point fluctuates. Here, since the effective channel length of the MOS transistor is expressed by the distance between the source and the pinch-off point, the fluctuation of the pinch-off point causes a channel length modulation effect.

That is, when the drain voltage is increased, the effective channel length is shortened and the drain current (Ids) is likely to flow, so that a slope is generated in the Vd-Id characteristic as illustrated in FIG. This slope means that the drain voltage becomes a drain current and escapes to the source. That is, a part of the drain output analog signal is lost (leaked) to the source, leading to a decrease in output voltage. This decrease in output voltage is a phenomenon that becomes a problem in the design of analog signal amplifier circuits and the like.
As a countermeasure against such a problem, generally, as shown in FIG. 6, a designer of an analog circuit has a name of “cascode” in which two of a high Vth MOS transistor and a low Vth MOS transistor are connected in series. A circuit structure is used.

  In the cascode structure, the low Vth MOS transistor plays a role of absorbing all drain voltage fluctuations, and since the drain voltage fluctuation is not transmitted to the intermediate M point potential, the M point potential is constant. Since the potential at the point M is constant, the drain current is also constant, resulting in a Vd-Id characteristic with a very small slope. Therefore, the leak of the drain output analog signal to the source can be prevented. However, since this cascode structure requires two MOS transistors, there is a drawback that the voltage drop becomes large and it is difficult to use in a low voltage circuit.

  7A and 7B are conceptual diagrams showing a configuration example (No. 2) of the MOS transistor according to the conventional example. This MOS transistor 200 solves the above-mentioned drawbacks of the cascode structure. As shown in FIG. 7A, in this MOS transistor, the channel layer is divided into a high Vth region 227 and a low Vth region 229. Thus, the provision of the high Vth region 227 and the low Vth region 229 in one MOS transistor 200 means that two MOS transistors having different Vths are connected in series as shown in FIG. It is equivalent and becomes a circuit equivalent to cascode.

  According to such a configuration, the low Vth region 229 is almost depleted with respect to the drain voltage, and serves to separate the pinch-off point from the drain 225. This large depletion layer suppresses the fluctuation of the potential at the pinch-off point with respect to the fluctuation of the drain voltage. Thereby, the channel length modulation effect is reduced, and the leak of the drain output analog signal to the source 223 is reduced. That is, it becomes a high gain MOS transistor. Further, since the cascode structure is not required, the drain voltage drop is small, which is advantageous for a low voltage operation circuit. The transistor gain (Tr gain) is expressed by equation (1).

Tr gain = Drain output voltage / Gate input voltage = ΔVds / ΔVgs
= (ΔIds / ΔVgs) / (ΔIds / ΔVds)
= Gm / gds (1)
In the equation (1), Vds is a drain voltage, Vgs is a gate voltage, Ids is a drain current, gm is a mutual conductance, and gds is a drain conductance.

  Further, as shown in FIG. 7B, the formation of the high Vth region 227 in the MOS transistor 200 employs a method of injecting conductivity type impurities from the source side into the channel region with an oblique inclination. (For example, see Patent Document 1, Non-Patent Document 1, and Non-Patent Document 2.) For example, in the case of an nMOS transistor, the high Vth region 227 is formed by obliquely implanting boron ions from the source side to the channel region with the drain-side silicon substrate 201 covered with the resist pattern 241.

FIG. 8 shows the result of simulation of the impurity concentration distribution of the MOS transistor 200 based on predetermined process parameters. The impurity concentration in silicon at the interface between the gate oxide film and the silicon substrate is plotted along the direction from the source to the drain. It is a thing. In FIG. 8, the horizontal axis indicates the distance [μm] from the center of the gate electrode in the direction of the source 223 and the drain 225. The source 223 direction is negative and the drain 225 direction is positive. The vertical axis represents the common logarithm (log ₁₀ ) of the concentration [/ cm ³ ] of the conductive impurities contained in the silicon.

As and P in FIG. 8 are the concentrations of arsenic and phosphorus, respectively. These As and P constitute the source 223 and the drain 225 having the LDD structure shown in FIG. B is the concentration of boron. Further, Net is a canceling concentration between the P-type impurity and the N-type impurity. In FIG. 8, in the range of about −0.35 to 0.35 [μm], the concentration of B is larger than that of As and P. Therefore, in this range, Net is almost the same as the concentration of B. In this simulation, process parameters were set as follows.
Gate length: 1 [μm]
Gate oxide film: 65 [Å]
Ion implantation conditions from the source side to the channel region: boron, 50 [kev], 1E + 13 [/ cm ² ], implantation angle (Tilt) 30 [°]

By such oblique ion implantation of boron or the like, the boron concentration on the drain side becomes relatively smaller than that on the source side. Accordingly, since the channel region on the source side becomes the high Vth region 227 and the channel region on the drain side becomes the low Vth region 229 (see FIG. 7B), the channel length modulation effect can be reduced, Gaining can be achieved.
JP 2001-77361 A IEEE Electron Devices, Vol.46, No.8, P1699 (1999) Miyamoto IEEE Electon Device Letters, Vol.22, No.12, P588 (2001) Deshpande

As shown in FIG. 7B, in the MOS transistor 200 according to the conventional example, boron is ion-implanted obliquely from the source side to the channel region to form the high Vth region 227 and the low Vth region 229. Was.
However, in such an oblique ion implantation method from the source side, the boron implantation amount tends to vary two-dimensionally along the surface of the silicon substrate, compared to an ion implantation method with an implantation angle close to normal vertical. is there. Here, the Vth of the MOS transistor is governed by the impurity concentration of the channel region on the source side, that is, the impurity concentration of the high Vth region. Therefore, in the oblique ion implantation method from the source side as shown in FIG. 7B, there is a possibility that the Vth of the MOS transistor varies more greatly than in the normal ion implantation method.

  Further, as shown in FIG. 8, in the MOS transistor 200 according to the conventional example, a high concentration region of boron in the source side channel region (approximately in the range of −0.20 to −0.50 [μm]) is abrupt. Since it is formed in a gradient, boron was easily diffused and varied in this region. Therefore, in the heat treatment step after ion implantation of boron from the source side obliquely, there is a problem that Vth of the MOS transistor 200 is likely to change greatly due to fluctuations in the heat treatment temperature. Variation in Vth of MOS transistors is a particularly serious problem for analog circuits.

Further, in the oblique ion implantation method from the source side, as shown in FIG. 7B, the gate electrode functions as a mask. Therefore, even if a high-concentration boron layer (that is, a high Vth region) 227 can be formed on the source side of the channel region, the high Vth region 227 is formed to have a certain size or more so as to extend to the drain side. I couldn't.
Therefore, in a plurality of types of MOS transistors having different gate lengths, when the high Vth region 227 is formed on the source side of each channel region, the length along the channel direction of the low Vth region 229 on the drain side is different. . Therefore, when the gate length of the MOS transistor is different, there is a problem that the performance of the low Vth region 229 as the “drain voltage fluctuation absorbing layer” is greatly different.

In order to avoid such a variation in the performance of the low Vth region 229, an analog circuit designer cannot freely select and use a plurality of types of MOS transistors having different gate lengths when designing an analog circuit. It was. That is, the MOS transistor 200 having the structure shown in FIG. 7A has a problem that it is not easy to use.
The present invention has been made to solve the above-described problems, and it is an object of the present invention to provide a semiconductor device capable of reducing the channel length modulation effect and reducing the leak of the drain output analog signal to the source, and a method of manufacturing the same. And

  In order to solve the above-described problem, a first semiconductor device according to the present invention includes a semiconductor substrate, a gate insulating film provided on the semiconductor substrate, and a gate electrode portion provided on the gate insulating film. Of the one conductivity type source and drain provided on the semiconductor substrate exposed from below the gate electrode portion and the opposite conductivity type channel region sandwiched between the source and drain, adjacent to the drain and adjacent to the source A transistor having an MIS structure including an impurity canceling layer provided at a specific portion that is not included, and the impurity canceling layer includes an impurity of one conductivity type in a higher concentration than other portions of the channel region. It is characterized by.

The second semiconductor device according to the present invention is the above-described first semiconductor device, wherein the impurity canceling layer is provided from the semiconductor substrate immediately below the drain to the specific portion so as to be adjacent to the lower portion of the drain. It is characterized by being.
Furthermore, a third semiconductor device according to the present invention is the above-described first or second semiconductor device, wherein the drain includes a first impurity diffusion layer containing the one conductivity type impurity, and the first impurity. It comprises a second impurity diffusion layer having an impurity concentration of one conductivity type lower than that of the diffusion layer, and the impurity offset layer is adjacent to the second impurity diffusion layer.

  According to the first to third semiconductor devices according to the present invention, the specific part of the channel region (hereinafter referred to as “the drain side of the channel region”) is another part of the channel region (hereinafter referred to as “channel region”). The impurity concentration of one conductivity type is higher than that of the "source side". In particular, on the drain side of the channel region, the one conductivity type impurity and the opposite conductivity type impurity are electrically canceled out.

  With such a configuration, the threshold voltage on the drain side of the channel region can be made lower than the threshold voltage on the source side of the channel region. Therefore, when a drain voltage is applied to the MIS structure transistor, the drain side of the channel region, that is, the impurity canceling layer can be almost depleted, and the pinch-off point can be separated from the drain. Thereby, the potential fluctuation at the pinch-off point with respect to the fluctuation of the drain voltage can be suppressed, and the channel length modulation effect can be reduced. Therefore, the leak of the drain output analog signal to the source can be reduced, and the gain of the transistor can be increased.

Further, according to the first to third semiconductor devices according to the present invention, it is not necessary to adopt the cascode structure as shown in FIG. 6, and therefore, the drain voltage drop can be reduced. It can also contribute to miniaturization and high integration of CMOS analog circuits and the like.
Furthermore, according to the first to third semiconductor devices according to the present invention, for example, the impurity canceling layer is formed from the semiconductor substrate immediately below the drain to the drain side of the channel region so as to be adjacent to the lower portion of the drain of one conductivity type. It is good to provide. With such a configuration, the parasitic capacitance of the drain can be reduced.

  In a fourth semiconductor device according to the present invention, in the first to third semiconductor devices described above, the length of the impurity canceling layer along the channel direction is 0.10 [μm] or more and 0.20 [μm]. It is characterized by the following. According to the fourth semiconductor device of the present invention, the length of the impurity cancellation layer along the channel direction is 0.10 [μm] or more and 0.20 [μm] or less, more preferably 0.15 [μm]. By doing so, the function of the impurity canceling layer as a “drain voltage fluctuation absorbing layer” can be sufficiently exerted.

  A method of manufacturing a semiconductor device according to the present invention is a method of manufacturing any one of the first to fourth semiconductor devices described above, and after forming the gate electrode portion on the gate insulating film, The impurity canceling layer is formed by ion-implanting one conductivity type impurity obliquely from above the semiconductor substrate on the drain side toward the specific portion of the semiconductor substrate. Here, the oblique means an inclination in a range of, for example, 25 [°] to 35 [°] with respect to the vertical direction of the semiconductor substrate surface.

  According to the method of manufacturing a semiconductor device according to the present invention, as in the conventional example shown in FIG. 7B, in the process of forming a MIS structure transistor, the opposite conductivity from above the source toward the source side of the channel region. There is no need to implant the impurity of the mold at an angle. Accordingly, variation in the impurity concentration of the opposite conductivity type on the source side of the channel region can be suppressed, which can contribute to stabilization of the threshold voltage of the transistor.

  Further, according to the method for manufacturing a semiconductor device according to the present invention, when forming the impurity canceling layer on the drain side of the channel region, ion implantation conditions (for example, implantation energy, implantation angle, etc.) of one conductivity type impurity are formed. By adjusting the length, the length of the impurity canceling layer along the channel direction can be adjusted within a certain range. Therefore, an impurity canceling layer having the same length along the channel direction can be formed between a plurality of types of MOS transistors having different gate lengths, and the function of the impurity canceling layer as a “drain voltage fluctuation absorbing layer” is uniform. Can be Thereby, when designing an analog circuit, a plurality of types of MOS transistors having different gate lengths can be freely selected, which contributes to an improvement in the degree of freedom in circuit design.

According to the present invention, the channel length modulation effect can be reduced, and the leak of the drain output analog signal to the source can be reduced. Thus, the gain of the MIS structure transistor can be increased.
In addition, according to the present invention, it is not necessary to adopt the cascode structure as shown in FIG. 6, which can contribute to miniaturization and high integration of the semiconductor device.

  Furthermore, according to the present invention, as in the conventional example shown in FIG. 7B, in the process of forming a MIS structure transistor, impurities of opposite conductivity type are obliquely applied from above the source toward the source side of the channel region. There is no need for ion implantation. Therefore, as compared with the conventional example, variation in the impurity concentration of the opposite conductivity type on the source side of the channel region can be suppressed, which can contribute to stabilization of the threshold voltage of the transistor.

Hereinafter, a semiconductor device and a manufacturing method thereof according to embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a cross-sectional view showing a configuration example of a MOS transistor 100 according to an embodiment of the present invention. The MOS transistor 100 is one element constituting, for example, a CMOS analog circuit.
As shown in FIG. 1, the N-type MOS transistor 100 includes a silicon substrate 1, an element isolation layer 103 provided on the silicon substrate 1, and a silicon substrate 1 in a region isolated by the element isolation layer 103. P-type well diffusion layer 5 (p-well) provided on the gate diffusion layer 5, a gate oxide film 15 provided on the well diffusion layer 5, a gate electrode 13 provided on the gate oxide film 15, and the gate An N-type source and drain provided on the silicon substrate 1 exposed from below the electrode 13, a side wall spacer 33, a high Vth region 27, a low Vth region 29, and the like are included.

In FIG. 1, the element isolation layer 103 is made of, for example, a silicon oxide film, and is formed by, for example, the LOCOS method. The well diffusion layer 5 is formed, for example, by boron ion implantation and thermal diffusion. The concentration of boron in the well diffusion layer 5 is, for example, about 2E + 17 [/ cm ³ ]. Furthermore, the gate oxide film 15 is a silicon oxide film formed by thermal oxidation, for example. The thickness of this gate oxide film is, for example, 65 [Å]. The gate electrode 13 is made of polysilicon doped with a conductive impurity such as phosphorus. The gate length of the gate electrode 13 is, for example, 1 [μm].

As shown in FIG. 1, the source 23 and the drain 25 have a so-called LDD structure. That is, the drain 25 is composed of an N-type high concentration layer (N ⁺⁺ ) 25b and a low concentration layer (n ⁻ ) 25a in which the concentration of N-type impurities is lower than that of the high concentration layer. The N ⁻ layer 25 a is provided between the N ⁺⁺ layer 25 b and the well diffusion layer 5. Similarly, the source 23 is also an ^{N ++} layer 23b, N ^- are composed of a layer 23a, N ^- layer 23a is provided between the ^{N ++} layer 23b and the well diffusion layer 5.

The sidewall spacer 33 is made of, for example, a silicon oxide film. As shown in FIG. 1, the sidewall spacer 33 is provided on the N ⁻ layers 23 a and 25 a of the silicon substrate 1. When the maximum width of the sidewall spacer 33 is L1, L1 is about 0.13 [μm], for example. Further, when the length of the portion of the N ⁻ layer 25a that extends to below the gate electrode 13 is L2, L2 is, for example, 0.1 [μm].

As shown in FIG. 1, the high Vth region 27 is provided on the source 23 side of the channel region and is adjacent to the N ⁻ layer 23 a constituting the source 23. The high Vth region 27 contains mainly about 2E + 17 [/ cm ³ ] of boron, as in the case of the well diffusion layer 5, for example. The low Vth region 29 is provided on the drain 25 side of the channel region and is adjacent to the N ⁻ layer 25 a constituting the drain 25. The low Vth region 29 contains, for example, phosphorus in addition to boron at a level of E + 17 [/ cm ³ ]. The low Vth region 29 and the high Vth region 27 are adjacent to each other.

  Further, as shown in FIG. 1, when the length of the low Vth region 29 along the channel direction is L3, L3 is, for example, 0.15 [μm]. When the length of the high Vth region 27 along the channel direction is L4, L4 is, for example, 0.65 [μm]. In FIG. 1, the low Vth region 29 is shown larger than the high Vth region 27 for easy understanding of the low Vth region 29.

FIG. 3 shows the result of simulating the impurity concentration distribution of the MOS transistor 100 based on predetermined process parameters. The impurity concentration in silicon at the interface between the gate oxide film 15 and the silicon substrate 1 is changed from the source 23 to the drain 25. Is plotted along In this simulation, the process parameters were set as follows.
Gate length: 1 [μm]
Gate oxide film: 65 [Å]
Ion implantation conditions from the source side to the channel region: boron, 50 [kev], 1E + 13 [/ cm ² ], implantation angle (Tilt) 30 [°]

In FIG. 3, the horizontal axis indicates the distance [μm] from the center of the gate electrode 13 toward the source 23 and drain 25. The source 23 direction is negative and the drain 25 direction is positive. The vertical axis represents the common logarithm (log ₁₀ ) of the concentration [/ cm ³ ] of the conductive impurities contained in the silicon. As and P in FIG. 3 are the concentrations of arsenic and phosphorus, respectively. These As and P constitute a source 23 and a drain 25 having an LDD structure. B is the concentration of boron. Furthermore, Net (cancellation concentration) is the cancellation concentration of P-type impurities and N-type impurities.

In FIG. 3, the range of about 0.25 to 0.40 [μm] on the horizontal axis is the low Vth region 29. As can be seen from FIG. 3, in this range, boron (about 1E + 17 [/ cm ³ ]) in the well diffusion layer 5 and phosphorus (2E + 17 to 1E + 18 [/ cm] introduced into the silicon substrate 1 by oblique ion implantation described later. ³ ] and so on). As a result of this cancellation (offset), an N ⁻ / P ⁻⁻ layer of about 1E + 17 to 1E + 18 [/ cm ³ ] is formed. Here, the N ⁻⁻ / P ⁻⁻ layer means that a transition region between the N-type layer and the p-type layer is included.

Thus, according to the MOS transistor 100 according to the embodiment of the present invention, the phosphorus concentration on the drain 25 side of the channel region is higher than the phosphorus concentration on the source 23 side of the channel region. In particular, especially on the drain side 25 of the channel region, phosphorus and boron are electrically canceled to form an N ⁻ / P ⁻⁻ layer of about 1E + 17 to 1E + 18 [/ cm ³ ].

With such a configuration, the threshold voltage (Vth) on the drain 25 side of the channel region can be made lower than Vth on the source 23 side of the channel region. Accordingly, upon applying a drain voltage to the MOS transistor 100, the drain 25 side of the channel region, i.e., the low Vth region ^{(N - / P} - layer) 29 mostly can be depleted, and the pinch-off point Can be separated from the drain. Thereby, the potential fluctuation at the pinch-off point with respect to the fluctuation of the drain voltage can be suppressed, and the channel length modulation effect can be reduced. Therefore, the leak of the drain output analog signal to the source can be reduced, and the gain of the MOS transistor 100 can be increased.

Further, according to the MOS transistor 100 according to the embodiment of the present invention, since it is not necessary to adopt the cascode structure as shown in FIG. 6, it is possible to suppress the drain voltage drop. It can also contribute to miniaturization and high integration of CMOS analog circuits and the like.
Furthermore, according to the MOS transistor 100 according to the embodiment of the present invention, for example, N adjacent to the drain side of the channel region from the silicon substrate 1 immediately below the drain so as to be adjacent to the lower part of the N ⁻ layer 23 constituting the drain 25. ^- / ^{P -} is a layer. Thereby, the parasitic capacitance of the drain is reduced.

Next, a manufacturing method of the above-described MOS transistor 100 will be described.
2A to 2C are process diagrams showing a method for manufacturing the MOS transistor 100 according to the embodiment of the present invention. Here, a case where the NMOS transistor 100 is manufactured using a CMOS process having a minimum gate length of 0.35 [μm] will be described.
In FIG. 2A, a gate oxide film 15 is formed, then a gate electrode 13 is formed on the gate oxide film 15, and then phosphorus or the like is ion-implanted into the silicon substrate 1 using the gate electrode 13 as a mask. The process up to the formation of the N ⁻ layers 23a and 25a is the same as the normal CMOS formation process.

After the N ⁻ layers 23a and 25a are formed, the source side of the MOS transistor 100 is covered with a resist pattern 41 in a photolithography process as shown in FIG. Then, for example, phosphorus is ion-implanted into the silicon substrate 1 exposed from below the resist pattern 41 to form a low Vth region (N ⁻⁻ / P ⁻⁻ layer) 29. In this ion implantation step, phosphorus is ion-implanted from above the drain side of the silicon substrate 1 to form a low Vth region 29 at a position obliquely deeper from the end e point of the gate electrode 13 toward the source. By forming the low Vth region 29 at a position obliquely deeper in the source direction than the end e point of the gate electrode 13, “the function of suppressing the leak of the drain output analog signal to the source” of the low Vth region 29 is strongly strengthened. can do.

The ion implantation conditions are, for example, ion species: phosphorus (P), dose amount: 1E + 13 [/ cm ² ], implantation energy: 150 [kev], and implantation angle (Tilt): 30 °. Under such ion implantation conditions, a range from the point e of the gate electrode 13 on the surface of the silicon substrate 1 to a depth of about 350 [nm] (from the point e to the source direction along the surface of the silicon substrate 1 about 180 [nm] The low Vth region 29 is formed in the depth direction of the silicon substrate 1 in a range of about 300 [nm].

Here, since the boron concentration in the well diffusion layer 5 is about 2E + 17 [/ cm ³ ] as described above, the Net (cancellation concentration) in the low Vth region 29 is about 1E + 17 to 1E + 18 [/ cm ³ ] ( (See FIG. 3). The length of the low Vth region 29 along the channel direction on the surface of the silicon substrate 1 is about 0.15 [μm]. The low concentration of 1E + 17 to 1E + 18 [/ cm ³ ] in the low Vth region 29 and the length along the channel direction of 0.15 [μm] are important for improving the performance of the MOS transistor 100. That is, if the low Vth region 29 is smaller than 0.15 [μm], the effect as the drain voltage fluctuation absorbing layer is weakened. On the contrary, if it is larger than 0.15 [μm], the short channel effect is increased.

  Note that the source side of the channel region becomes the high Vth region 27 by the oblique ion implantation for forming the low Vth region 29. Further, the ion species implanted by this oblique ion implantation is not limited to phosphorus, and it is possible to select and use an impurity that lowers Vth by an absolute value. For example, other N-type impurities such as arsenic (As) other than phosphorus (P) may be selected and ion-implanted.

As shown in FIG. 2 (C), the low Vth region ^{(N - / P} - layer) 29 after the formation of the is the same as a normal CMOS fabrication process. That is, the side wall spacer 33 is formed on the side wall of the gate electrode 13. Next, N ⁺⁺ layers 23b and 25b are formed by ion-implanting N-type impurities such as arsenic into the silicon substrate 1 using the sidewall spacer 33 and the gate electrode 13 as a mask. Thereafter, an interlayer insulating film (not shown) and metal wiring are formed to complete the MOS transistor 100 shown in FIG.

  As described above, according to the method of manufacturing the MOS transistor 100 according to the embodiment of the present invention, in the process of forming the MOS transistor as in the conventional example shown in FIG. There is no need to implant boron ions obliquely toward the side. Therefore, variations in boron concentration can be suppressed in the high Vth region that determines the Vth of the MOS transistor.

  Further, as can be seen by comparing the simulation results shown in FIG. 3 and FIG. 8, the MOS transistor 100 according to the embodiment of the present invention can obtain a flat boron concentration and a Net (cancellation concentration). For example, the boron diffusion fluctuation can be suppressed against the fluctuation of the heat treatment temperature in the heat treatment step. Therefore, it is possible to contribute to stabilization of Vth of the MOS transistor.

  Furthermore, according to the method of manufacturing the MOS transistor 100 according to the embodiment of the present invention, when forming the low Vth region 29, oblique ion implantation conditions (for example, implantation energy, implantation angle, etc.) of N-type impurities such as phosphorus are formed. ) Is adjusted, the length (L3) along the channel direction of the low Vth region 29 can be adjusted within a certain range. Therefore, the low Vth region 29 having the same length can be formed between a plurality of types of MOS transistors 100 having different gate lengths, and the function of the low Vth region 29 as the “drain voltage fluctuation absorbing layer” is made uniform. be able to. Accordingly, when designing an analog circuit, a plurality of types of MOS transistors 100 having different gate lengths can be freely selected, which contributes to an improvement in the degree of freedom in circuit design.

In this embodiment, the N type corresponds to one conductivity type of the present invention, and the P type corresponds to the opposite conductivity type of the present invention. The silicon substrate 1 corresponds to the semiconductor substrate of the present invention, and the gate oxide film 15 corresponds to the gate insulating film of the present invention. Furthermore, the low Vth region ^{(N - / P} - layer) 29 corresponds to the impurity compensation layer of the present invention, MOS transistor 100 corresponds to the transistor of the MIS structure of the present invention. Further, phosphorus (P) contained in a large amount on the drain side of the channel region corresponds to one conductivity type impurity of the present invention.

  In this embodiment, the case where the MOS transistor 100 is formed using the CMOS process with the shortest gate length of 0.35 [μm] has been described. However, in the present invention, the gate length of the MOS transistor 100 is formed to be 1 [μm] or more, so that the gain can be sufficiently increased. This point will be described in [Verification] below.

In this embodiment, the case where the MOS transistor 100 is an NMOS has been described. However, the present invention is not limited to NMOS, and may be, for example, PMOS. In the case of PMOS, a low Vth region 29 is formed by obliquely ion implanting P-type impurities such as boron and indium (In) at the same depth and position as the NMOS (on the drain side of the channel region). For example, in the case of PMOS, ion implantation conditions for forming the low Vth region 29 are as follows: ion species: boron, implantation energy: 50 [kev], dose amount: 1E + 13 [/ cm ² ], implantation angle (tilt angle): 30 ° is good. Furthermore, the present invention can be applied to a CMOS process having a minimum gate length other than 0.35 [μm], and the same effect as that of a CMOS process having a 0.35 [μm] can be obtained.

[Verification]
FIG. 4 is a diagram showing the gate length dependence of the gain of the MOS transistor 100. In FIG. The horizontal axis of FIG. 4 is the gate length [μm] of the MOS transistor. The vertical axis represents gain [gm / gds]. The bias conditions for gain evaluation in this verification are Vds: 2 [V] and Vgs: 1.5 [V]. In addition, the four samples shown in FIG. 4 are different only in the formation process of the low Vth layer (or high Vth layer), and all of them are CMOS processes with the shortest gate length of 0.35 [μm]. It was created using. Details of each sample are as follows.

1) RefNL: Low Vth NMOS (Reference) with a symmetrical structure. The concentration of P-well is 2E + 17 [/ cm ³ ]. The symmetric structure means that the left / right source / drain impurity concentration profiles are mirror-symmetric with respect to the center line of the gate.
2) NoNL + S / B: Only the source side is an asymmetric boron ion implantation method, and boron ions are implanted from the source side. In order to obtain the same Vth as that of Reference with a gate length of 0.4 [μm], the concentration of P-well was set low as 1E + 16 [/ cm ³ ]. Asymmetric Boron ion implantation conditions: boron, 50 kev, 1E + 13 [/ cm ² ], Tilt 30 °. Asymmetry means that the left and right source / drain impurity concentration profiles are not mirror symmetric with respect to the center line of the gate.

3) NL + S / B: Asymmetric boron ion implantation method only on the source side. Further, boron was ion-implanted from the source side at the same P-well concentration as that of Reference. Asymmetric Boron ion implantation conditions: Boron, 50 kev, 1E + 13 [/ cm ² ], Tilt 30 °
4) NL + D / P: Same conditions as in the embodiment of the present invention. Same P-well concentration as Reference (2E + 17 [/ cm < ³ >]). Phosphorus ions were implanted from the drain side. Asymmetric phosphorus ion implantation conditions: phosphorus, 150 kev, 1E + 13 [/ cm ² ], Tilt 30 °
As shown in FIG. 4, the condition according to the embodiment of the present invention and “NL + D / P” having a gate length of 1 [μm] or more can obtain a gain of about twice that of the reference having the same gate length. We have demonstrated that we can do it.

FIG. 3 is a cross-sectional view showing a configuration example of a MOS transistor 100 according to the embodiment. FIG. 5 is a process diagram showing a method for manufacturing the MOS transistor 100. The figure which shows the result of having simulated the distribution of the impurity concentration of the MOS transistor. The figure which shows the gate length dependence of the gain of MOS transistor 100 (figure which shows the result of verification). The figure which shows the structural example (the 1) of the MOS transistor which concerns on a prior art example, and its Vd-Id characteristic. The figure which shows a cascode structure. The figure which shows the structural example (the 2) of the MOS transistor which concerns on a prior art example, and its manufacturing process. The figure which shows the result of having simulated the distribution of the impurity concentration of the MOS transistor.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Silicon substrate 3 Element isolation layer 5 Well diffused layer 13 Gate electrode 15 Gate oxide film 23 Source 25 Drain 23a, 25a N ⁻ layer 23b, 25b N ⁺⁺ layer 27 High Vth region 29 Low Vth region (N ⁻ / P ⁻⁻ layer)
33 Sidewall spacer 100 MOS transistor

Claims (5)

A semiconductor substrate;
A gate insulating film provided on the semiconductor substrate;
A gate electrode portion provided on the gate insulating film;
A source and drain of one conductivity type provided on a semiconductor substrate exposed from below the gate electrode portion;
An MIS-structure transistor comprising: an impurity canceling layer provided in a specific portion adjacent to the drain and not adjacent to the source in the channel region of opposite conductivity type sandwiched between the source and drain;
1. The semiconductor device according to claim 1, wherein the impurity canceling layer contains an impurity of one conductivity type at a higher concentration than other portions of the channel region.   2. The semiconductor device according to claim 1, wherein the impurity canceling layer is provided from the semiconductor substrate immediately below the drain to the specific portion so as to be adjacent to the lower portion of the drain. The drain is
A first impurity diffusion layer containing the impurity of one conductivity type;
A second impurity diffusion layer having an impurity concentration of one conductivity type lower than that of the first impurity diffusion layer;
3. The semiconductor device according to claim 1, wherein the impurity canceling layer is adjacent to the second impurity diffusion layer.   4. The length according to the channel direction of the impurity canceling layer is 0.10 [μm] or more and 0.20 [μm] or less. 5. Semiconductor device. A method for manufacturing the semiconductor device according to any one of claims 1 to 4,
After forming the gate electrode portion on the gate insulating film, by obliquely ion implanting one conductivity type impurity from above the semiconductor substrate on the drain side toward the specific portion of the semiconductor substrate, A method of manufacturing a semiconductor device, comprising forming an impurity canceling layer.

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