JP4917761B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device suitable for application to a CMOS analog circuit and a manufacturing method thereof.

Conventionally, CMOS analog circuits have been used as circuits for processing analog signals such as video and audio signals. Semiconductor devices are becoming finer and higher integrated year by year, but analog CMOS transistors used in such CMOS analog circuits (for example, analog circuits such as high-precision amplifiers) have a gate length of 1 (μm) or more. Most are things.
The reason is that there is a trade-off relationship between miniaturization of an analog CMOS transistor and mutual conductance Gm, output resistance Rout (= dVd / dId), 1 / f noise, threshold Vth matching, and the like. However, from the viewpoint of low voltage and low power consumption, the miniaturization of analog CMOS transistors is also in the right direction, and the development of an analog CMOS with a short gate length is required.

In a CMOS analog circuit, a pMOS transistor or an nMOS transistor generally operates and is used as an analog element in its saturation region. 13A to 13C are conceptual diagrams showing a configuration example of a general MOS transistor and its Vd-Id characteristics.
In the MOS transistor as shown in FIG. 13A, when the MOS transistor is used as an analog element in the saturation region operation as shown in FIG. 13C, the inversion is shown in FIG. 13B. The pinch-off point of the channel layer is inevitably formed in the vicinity of the high concentration drain end.

  In this state, when an analog signal is applied to the drain, fluctuations in the drain voltage (Vds) cause potential fluctuations at the nearest pinch-off point, and the pinch-off point fluctuates. Here, since the effective channel length of the MOS transistor is expressed by the distance between the source and the pinch-off point, the fluctuation of the pinch-off point causes a channel length modulation effect (CLM: Channel Length Modulation).

  That is, when the drain voltage is increased, the effective channel length is shortened and the drain current (Ids) easily flows, so that a slope is generated in the Vd-Id characteristic as illustrated in FIG. That is, the value of the output resistance Rout (= dVd / dId) becomes low. Such a slope means that the drain voltage becomes a drain current and escapes to the source. When the drain voltage becomes a drain current and escapes to the source, in other words, a part of the drain output analog signal escapes (leaks) to the source, leading to a decrease in the output voltage. This decrease in output voltage is a phenomenon that becomes a problem in the design of analog signal amplifier circuits and the like.

  Such a deterioration (decrease) in the output resistance Rout, that is, a deterioration (increase) in the drain conductance Gds (= 1 / Rout) becomes more remarkable by miniaturizing the process, but there are two causes. is there. The first cause is an increase in the threshold voltage Vth reduction phenomenon (DIBL) due to drain voltage induction on the source side of the transistor. The second reason is that the channel length modulation effect (CLM) increases at the pinch-off point.

In order to realize miniaturization (short gate length) of the analog CMOS transistor, it is necessary to suppress such increase of DIBL and CLM and to prevent the deterioration of the drain conductance Gds.
As a method for preventing the deterioration of the drain conductance Gds, a so-called asymmetric pocket implant only on the source side, in which an impurity having the same conductivity type as that of the substrate is ion-implanted only on the source side, has been conventionally known (for example, Patent Documents). 1. See Non-Patent Documents 1 to 4.)

According to such an asymmetric pocket implanter, the source-side threshold value Vth can be adjusted to a higher value, so that an increase in DIBL can be suppressed. The reason why the pocket implantation is not performed on the drain side is that the depletion layer between the drain and the channel is kept large, the electric field in the drain direction at the pinch-off point is relaxed, and the increase in CLM is suppressed (that is, CLM is improved). is there.
As another improvement example of CLM, there is a report example of a large drain structure suitable for high withstand voltage (for example, see Non-Patent Document 5). Furthermore, an asymmetric LDD structure having a metal silicide only in a region adjacent to the channel of the source region is known. (For example, refer to Patent Document 2).

JP 59-61185 A JP-A-4-245642 Hemant V. Deshpande et al., VLSI Symp. Tech. Dig., Pp87-88, 2001 Hemant V. Deshpande et al., Electron Devices Vol 49 No9 p1558 (2002) Baohong Cheng et al., VLSI Symp. Tech. Dig., Pp69-70, 1999 M. Miyamoto et al., Electron Devices Vol 46 No8 p1699 (1999) J. Mitros et al., Electron Devices Vol 48 p1751 (2001)

  According to the conventional example (hereinafter referred to as “conventional example 1”) having the pocket implantation layer only on the source side, it is possible to improve the value of the drain conductance Gds as compared with a normal analog CMOS transistor. However, when the MOS transistor according to the conventional example 1 is miniaturized until the gate length is close to 0.35 (μm), the value of the drain conductance Gds is at most 1 as compared with a normal analog CMOS transistor. It was about / 3 to 1/5 times, and it was difficult to say that the degree of improvement was sufficient (first problem).

Further, according to the conventional example of a large drain structure suitable for high breakdown voltage as disclosed in Non-Patent Document 5 (hereinafter referred to as “Conventional Example 2”), the CLM is improved as compared with a normal analog CMOS transistor. Although it is possible, there is a problem that the junction depth Xj of the drain is increased and it is difficult to use the fine CMOS (second problem).
By the way, the present inventor pays attention to the electric field reduction on the drain side as further improvement of low Gds, and finds that the drain conductance Gds of the transistor can be reduced by two orders of magnitude or more by combining the Ldd layer and the pocket implantation layer having an asymmetric structure. It was. In order to solve the above first and second problems, a semiconductor device having a structure including both an Ldd layer having an asymmetric structure and a pocket implant layer having an asymmetric structure has been filed (Japanese Patent Application No. 2004-196950, Hereinafter referred to as “prior application”).

  However, in the previous application, the effect that the drain conductance Gds can be reduced by two orders of magnitude or more can be obtained, while the impurity concentration of the channel layer is uniform from the source end to the drain end (hereinafter simply referred to as “uniform structure”). For example, the transistor in FIG. 5A) has a problem that the pinch-off voltage Vdsat becomes higher (third problem).

Here, the pinch-off voltage means that when a constant voltage (Vg) is applied to the gate electrode to form a channel layer and the drain voltage (Vd) is increased in this state, the drain current becomes substantially constant (that is, This is the drain voltage when saturated.
In other words, when a channel layer is formed by applying a constant voltage (Vg) to the gate electrode and the drain voltage (Vd) is increased in this state, the channel becomes equal when Vg−Vth = Vd. The inversion layer constituting is eliminated in the vicinity of the drain side. The drain voltage at this time is a pinch-off voltage. The pinch-off region occurs near the drain side and is also called a saturation region.

In analog CMOS, an amplifier circuit is designed using the high resistance performance in the saturation region. The last drain voltage that forms the pinch-off corresponds to the lower limit of the analog output voltage. When the pinch-off voltage is high, the amplified output range is narrowed, making it difficult to use at a low power supply voltage.
In the previous application, the channel implant concentration on the source side is increased (for example, 0.95 vol) by the pocket implant layer having an asymmetric structure (also referred to as an asymmetric channel structure), and the channel implantation concentration on the drain side is decreased (for example, 0.95 volt). , 0.35 vol), and the average of the entire channel is set to Vth 0.65 volt, for example.

According to this example, in the previous application, when Vg = 1 volt, the pinch-off voltage on the drain side is 0.65 volt (Vg−Vth = 1−0.35 = 0.65 volt). Since the pinch-off voltage of the uniform structure is 0.35 volt (Vg−Vth = 1−0.65 = 0.35 volt), the previous application has a pinch-off voltage of 0.3 volt higher than that of the uniform structure.
The present invention has been made in order to solve the above-described problems, and can achieve both miniaturization of a transistor having a MIS structure and reduction of leakage to the source of a drain output analog signal, and can further reduce a pinch-off voltage. An object of the present invention is to provide a semiconductor device and a manufacturing method thereof.

In order to achieve the above object, a semiconductor device according to one embodiment of the present invention includes a semiconductor substrate, a gate insulating film provided over the semiconductor substrate, a gate electrode portion provided over the gate insulating film, Of the one conductivity type source region and drain region provided on the semiconductor substrate exposed from below the gate electrode portion, and the opposite conductivity type channel region sandwiched between the source region and drain region, adjacent to the source region and An opposite conductivity type pocket implant layer provided at a specific portion not adjacent to the drain region, and an opposite conductivity type provided inside the semiconductor substrate and below the channel region, the source region, and the drain region. A retro-channel implantation region of the MIS structure transistor, and the source region has a high concentration of the one conductivity type impurity. A high-concentration source layer, and a low-concentration source layer that includes the one-conductivity type impurity at a low concentration and is provided from a lower portion of the high-concentration source layer to a side portion of the high-concentration source layer on the channel region side. The drain region includes a high-concentration drain layer containing the one-conductivity type impurity at a high concentration, and a low-concentration containing the one-conductivity type impurity from the lower portion of the high-concentration drain layer. A low-concentration drain layer provided on a side portion of the channel region side, wherein the low-concentration source layer contains the impurity of the one conductivity type at a higher concentration than the low-concentration drain layer, and channel implantation region viewed including the opposite conductivity type impurity than the channel region in a high concentration, and the pocket implantation layer is in a state adjacent to the lightly doped source layer, the low concentration source layer The retro-channel implantation region is provided at a predetermined depth from the surface of the semiconductor substrate so that the concentration value of the impurity of the opposite conductivity type peaks at a predetermined depth from the surface of the semiconductor substrate. And the retro-channel implant region is disposed in contact with the pocket implant layer and separated from the source region and the drain region .

In here, a source and a high-concentration source layer and the low concentration source layer, a drain and a high concentration drain layer and the low concentration drain layer is, for example, that of the source and the drain of the LDD structure. Further, the channel length modulation effect CLM by the drain voltage is expressed by the equation (i).
dΔL / dVds = {Esat × cosh (ΔL / ξ)} ⁻¹ (i)
ξ = (3 tox × Xj) ^1/2 : channel refinement parameter Esat: drain direction electric field at pinch-off point ΔL: distance from drain end to pinch-off point Vds: drain voltage

  It can be seen that an increase in ΔL is effective for reducing the channel length modulation effect (CLM) in addition to reducing the thickness of the gate oxide film tox. In the present invention, attention is focused on an increase in εΔL. If the concentration of LDD (lightly doped drain) is lowered, the depletion layer increases and ΔL increases. That is, it is possible to increase the effective ΔLeff = ΔL + Ln including the depletion layer by LDD. ΔLeff is an effective drain depletion layer width, and Ln is a depletion layer width in the drain low concentration LDD.

However, if the LDD implantation amount is simply reduced in order to reduce the concentration of LDD, the parasitic resistance between the source and the drain also increases. Therefore, the mutual conductance Gm and the drain current Idsat are reduced, and the fineness is reduced. It will detract from the attractiveness of the process. Here, the predetermined depth is, for example, about 0.2 (μm) .

According to the semiconductor device described above , the LDD has an asymmetric structure in order to avoid the side effect of increasing parasitic resistance even if the transistor is miniaturized. That is, the impurity concentration of the low-concentration drain layer is set low for the purpose of reducing Esat. Further, the impurity concentration of the low concentration source layer is set higher than that of the low concentration drain layer for the purpose of reducing parasitic resistance. Further, such an “asymmetric structure LDD” is combined with a “asymmetric structure pocket implant layer” that forms a pocket implant layer only on the source side.

  As a result, for example, in a 0.35 (μm) gate length transistor that is classified as a short channel as an analog CMOS, the drain voltage-induced Vth lowering phenomenon (DIBL) and the pinch-off point are hardly increased. The channel modulation effect (CLM) can be suppressed at the same time. Therefore, as compared with the prior art, the value of the drain conductance Gds can be reduced without significantly reducing the mutual conductance Gm and the saturation drain current Idsat, and the leakage of the drain output analog signal to the source can be reduced. it can.

Further, according to the above-described semiconductor device, the retro channel implantation region, an internal of the semiconductor substrate, a channel region, below the source region and the drain region (i.e., deep places of the semiconductor substrate) becomes higher impurity concentration Yes. When the impurity concentration in the deep part is high, when a bias is applied to the semiconductor substrate, the spread of the depletion layer in the semiconductor substrate becomes narrow, and the surface potential of the semiconductor substrate also becomes higher. As a result, the pinch-off voltage can be lowered.

A method of manufacturing a semiconductor device according to another aspect of the present invention is a method of manufacturing the semiconductor device described above , wherein the semiconductor on the source region side is formed after the gate electrode portion is formed on the gate insulating film. A method of manufacturing a semiconductor device, wherein the low-concentration source layer is formed by obliquely ion-implanting one conductivity type impurity from above the substrate toward the source region of the semiconductor substrate. Here, the oblique means an inclination in a range of, for example, 25 (°) to 35 (°) with respect to the vertical line direction on the surface of the semiconductor substrate.
According to the above method for manufacturing a semiconductor device, when one conductivity type impurity is ion-implanted into a portion to be the source region of the semiconductor substrate under the gate electrode portion, the drain region of the semiconductor substrate under the gate electrode portion is formed. It is possible to prevent impurities of one conductivity type from entering the part. Thereby, for example, the above-mentioned “LDD having an asymmetric structure” can be formed with good reproducibility.

A method of manufacturing a semiconductor device according to still another aspect of the present invention is a method of manufacturing the semiconductor device described above, wherein the gate electrode portion is formed on the gate insulating film, and then the source region side of the semiconductor device is manufactured. The pocket implantation layer is formed by ion-implanting impurities of opposite conductivity type obliquely from above the semiconductor substrate toward the specific portion of the semiconductor substrate.
According to the method for manufacturing a semiconductor device described above , when an impurity of an opposite conductivity type is ion-implanted into a specific portion of the semiconductor substrate under the gate electrode portion, it opposes the portion to be a drain region of the semiconductor substrate under the gate electrode portion. Conductive impurities can be prevented from entering. Thereby, for example, the “asymmetrical pocket implant layer” described above can be formed with good reproducibility.

A method for manufacturing a semiconductor device according to still another aspect of the present invention is a method for manufacturing the semiconductor device described above, wherein the gate electrode portion is formed on the gate insulating film, and then the drain region side of the semiconductor device is manufactured. The low-concentration drain layer is formed by ion-implanting an impurity of one conductivity type obliquely from above the semiconductor substrate toward a portion to be the drain region of the semiconductor substrate.
According to the above method for manufacturing a semiconductor device, when one conductivity type impurity is ion-implanted into a portion to be the drain region of the semiconductor substrate under the gate electrode portion, the source region of the semiconductor substrate under the gate electrode portion is formed. It is possible to prevent impurities of one conductivity type from entering the part. Thereby, for example, the above-mentioned “LDD having an asymmetric structure” can be formed with good reproducibility.

A method of manufacturing a semiconductor device according to still another aspect of the present invention is a method of manufacturing any one of the above semiconductor devices, the step of forming the gate electrode portion on the gate insulating film, and the source Forming the low-concentration source layer by obliquely ion-implanting one conductivity type impurity from above the semiconductor substrate on the region side toward the source region of the semiconductor substrate; and on the source region side Forming the pocket implant layer by obliquely implanting impurities of opposite conductivity type from above the semiconductor substrate toward the specific portion of the semiconductor substrate, and from above the semiconductor substrate on the drain region side The low-concentration drain layer is formed by ion-implanting one conductivity type impurity obliquely toward the portion to be the drain region of the semiconductor substrate. Extent and is characterized in that it comprises a.
According to the manufacturing method of the semiconductor device, for example, as "LDD asymmetric structure" described above can be formed with good reproducibility and a "pocket implantation layer of the asymmetric structure".

A method for manufacturing a semiconductor device according to still another aspect of the present invention is the method for manufacturing a semiconductor device described above , wherein the channel region, the source region, and the source region are formed before forming the gate insulating film on the semiconductor substrate. A step of forming a photoresist mask on the semiconductor substrate in which a portion serving as the drain region is opened; and an ion of an impurity of an opposite conductivity type is implanted into the semiconductor substrate on which the mask is formed to form the retro channel implantation region In the step of forming the retro channel implantation region, the ion implantation conditions are set so that the concentration value of the impurity of the opposite conductivity type reaches a peak at a predetermined depth from the surface of the semiconductor substrate. It is characterized by setting.
According to the above method for manufacturing a semiconductor device, the retro-channel implant region can be formed in a deep place in the semiconductor substrate.

According to the present invention, an LDD having an asymmetric structure in which a low concentration source layer has a higher impurity concentration than a low concentration drain layer, and an asymmetric structure in which an impurity having the same conductivity type as that of a semiconductor substrate is introduced only in a channel region on the source side. With both pocket implant layer. With such a configuration, the drain conductance Gds (= dId / dVd) can be made sufficiently small without significantly reducing the mutual conductance Gm.
In addition, according to the present invention, the impurity concentration in the deep part of the semiconductor substrate is increased by the retro channel implantation region. When the impurity concentration in the deep part is high, when a bias is applied to the semiconductor substrate, the spread of the depletion layer in the semiconductor substrate becomes narrow, and the surface potential of the semiconductor substrate also becomes higher. As a result, the pinch-off voltage can be lowered.

Hereinafter, a semiconductor device and a manufacturing method thereof according to embodiments of the present invention will be described with reference to the drawings.
(1) Structure of MOS Transistor 100 FIG. 1 is a cross-sectional view showing a configuration example of a MOS transistor 100 according to an embodiment of the present invention. The MOS transistor 100 is one element constituting, for example, a CMOS analog circuit.

  As shown in FIG. 1, the N-type MOS transistor 100 includes a silicon substrate 1, an element isolation layer 43 provided on the silicon substrate 1, and a silicon substrate 1 in a region isolated by the element isolation layer 43. P-type well diffusion layer (P-well) 5 provided on the gate diffusion film 5, a gate oxide film 15 provided on the well diffusion layer 5, a gate electrode 13 provided on the gate oxide film 15, and the gate The structure includes an N-type source 60 and drain 70 provided on the silicon substrate 1 exposed from below the electrode 13, a sidewall spacer 33, and a retro channel implantation region (layer) 20.

In FIG. 1, the element isolation layer 43 is made of, for example, a silicon oxide film, and is formed by, for example, the LOCOS method. The well diffusion layer 5 is formed, for example, by boron ion implantation and thermal diffusion. Furthermore, the gate oxide film 15 is a silicon oxide film formed by thermal oxidation, for example. The gate electrode 13 is made of polysilicon doped with a conductive impurity such as phosphorus. The gate length of the gate electrode 13 is, for example, 0.35 (μm). The impurity concentration near the surface of the silicon substrate 1 (P ⁻ ) under the gate electrode 13 is, for example, about 1E + 17 (/ cm ³ ).

As shown in FIG. 1, the source 60 and the drain 70 have a so-called LDD structure. The source 60 includes an N-type high concentration layer (N ⁺ layer) 61 and an N-type low concentration layer (N ⁻ layer) 63, and the N ⁻ layer 63 includes the N ⁺ layer 61 and a well diffusion layer. 5 is provided. The drain 70 has an N-type high-concentration layer (N ⁺ layer) 71, an N-type impurity concentration lower than that of the N ⁺ layer 71, and an N-type impurity concentration higher than that of the N ⁻ layer 63 on the source side. low low concentration layer ^- and an (N layer) 73. N ⁻ layer 73 is provided between N ⁺ layer 71 and well diffusion layer 5. The N ⁺ layers 61 and 71 are made of N-type impurities such as arsenic, for example. Further, the N ⁻ layer 63 and the N ⁻ layer 73 are made of an N-type impurity such as phosphorus.

Further, in the P-type channel region sandwiched between the source 60 and the drain 70, a P-type pocket implant layer (P ^{− is formed} at a specific portion adjacent to the N ⁻ layer 63 and not adjacent to the N ⁻ layer 73. Layer) 80 is provided. The P ⁻ layer 80 is made of a P-type impurity such as boron.
Further, as shown in FIG. 1, the retro channel implantation region 20 is located inside the silicon substrate 1 and is continuous below the channel region including the P ⁻ layers 80 and P ⁻ , the source 60 and the drain 70. Is provided. The retro channel implantation region 20 is made of, for example, a P-type impurity such as boron, and the impurity concentration is about 1E + 18 (/ cm ³ ) at a depth of about 0.2 (μm) from the surface of the silicon substrate 1. It has become a peak. Channel region (P ^-) whereas it is low-density layer of about ^{1E + 17 (/ cm 3)} , retro channel implantation region 20 is an impurity concentration at the peak position of about ^{1E + 18 (/ cm 3)} , It is a high concentration layer.

FIG. 2 is a cross-sectional view showing the length of the P ⁻ layer 80, the N ⁻ layer 63, and the N ⁻ layer 73 extending in the channel direction. As shown in FIG. 2, when the length of the portion of the N ⁻ layer 63 extending to the bottom of the gate electrode 13 is L1, L1 is about 250 (Å), for example. Further, when the length of the portion of the P ⁻ layer 80 that extends from the channel side end of the N ⁻ layer 63 to below the gate electrode 13 is L2, L2 is about 1000 (例 え ば), for example. Further, N ^- when the length of the overhanging portion to the bottom gate electrode 13 of the layer 73 was set to L3, L3 is, for example, about 250 (Å).

As shown in FIG. 2, in this MOS transistor 100, since the P ⁻ layer 80 extends from the channel side end of the N ⁻ layer 63 to below the gate electrode 13, the threshold value Vth of the MOS transistor 100 is the source side even in the same channel region. Unlike the drain region, the source-side channel region (that is, the P ⁻ layer 80) has a higher threshold value Vth than the drain-side channel region (that is, the P-well 5).

As shown in FIG. 2, when the length of the retro channel implantation region 20 in the depth direction is d4, d4 is about 3000 (Å), for example.
Returning to FIG. 1, the sidewall spacer 33 is made of, for example, a silicon oxide film. As shown in FIG. 1, the sidewall spacers 33 are provided on the N ⁻ layer 63 and the N ⁻ layer 73 provided on the silicon substrate 1.

(2) Manufacturing Method of MOS Transistor 100 Next, a manufacturing method of the MOS transistor 100 will be described.
FIGS. 3A to 4C are process diagrams showing a method for manufacturing the MOS transistor 100. Here, a case where the NMOS transistor 100 is manufactured using a CMOS process with a minimum gate length of 0.35 (μm) will be described.
As shown in FIG. 3A, after the element isolation layer 43 and the well diffusion layer 5 are formed on the silicon substrate 1, a resist pattern 21 for forming the retro-channel implant region 20 is formed on the silicon substrate 1, The region other than the transistor region (that is, the element region) is covered.

Next, boron (B) is ion-implanted into the silicon substrate 1 at a low concentration using the resist pattern 21 as a mask, and P ⁻ for adjusting the threshold Vth is formed in the vicinity of the surface (that is, in a shallow place). Further, boron or the like is ion-implanted into the silicon substrate 1 using the resist pattern 21 as a mask, and a retro channel implantation region 20 is formed at a deep location. The ion implantation conditions for forming the retro channel implantation region 20 are, for example, ion species: boron (B), dose amount: 1.2E + 14 (/ cm ² ), implantation energy: 150 (kev), implantation angle (Tilt). : 7 °. Under such ion implantation conditions, the peak position of the retro-channel implant region 20 is at a depth of about 0.2 (μm) from the surface of the silicon substrate 1.

After the ion implantation for threshold adjustment and the retro channel implantation are completed, the silicon substrate 1 is subjected to an ashing process, and the resist pattern 21 is removed.
Next, as shown in FIG. 3B, a gate oxide film 15 is formed on the surface of the silicon substrate 1 to a thickness of, for example, about 65 (nm). Subsequently, as shown in FIG. 3C, a polysilicon film 13 ′ is formed on the gate oxide film 15. Then, the polysilicon film 13 ′ is patterned to form the gate electrode 13. The length of the gate electrode 13 (that is, the gate length) is, for example, about 0.35 (μm).

Next, as shown in FIG. 4A, a resist pattern 45 that covers the element isolation region and exposes the element region is formed on the silicon substrate 1. Then, using this resist pattern 45 and the gate electrode 13 as a mask, phosphorus or the like is ion-implanted into the silicon substrate 1 to form an N ⁻ layer 63 on the silicon substrate 1 in the source region. In this ion implantation step, phosphorus is ion-implanted from above the source side of the silicon substrate 1 to form the N ⁻ layer 63 from the source side end of the gate electrode 13 to a position obliquely entering the drain direction. .

The ion implantation conditions for forming the N ⁻ layer 63 are, for example, ion species: phosphorus (P), dose amount: 2E + 13 (/ cm ² ), implantation energy: 30 (kev), implantation angle (Tilt): 30 °. It is. Under such ion implantation conditions, the N ⁻ layer 63 is formed so that the depth from the surface of the silicon substrate 1 is d1 and the length of the protruding portion below the gate electrode 13 is L1. d1 is, for example, 500 (Å). Further, by this ion implantation, as shown in FIG. 4A, an N ⁻ layer 63 is also formed in a region which becomes the drain of the silicon substrate 1 and is separated from the bottom of the gate electrode 13.

Next, as shown in FIG. 4B, boron or the like is ion-implanted into the silicon substrate 1 using the gate electrode 13 as a mask to form a P ⁻ layer 80. In this ion implantation step, boron is ion-implanted with an inclination from above the source side of the silicon substrate 1, and the P ⁻ layer 80 is formed from the source side end of the gate electrode 13 to a position obliquely deep in the drain direction. . The ion implantation conditions for forming the P ⁻ layer 80 are, for example, ion species: boron (B), dose: 6E + 12 (/ cm ² ), implantation energy: 50 (kev), implantation angle (Tilt): 30 °. It is.

Under such ion implantation conditions, the depth from the surface of the silicon substrate 1 is d2, and the length of the protruding portion from the drain side end of the N ⁻ layer 63 to the bottom of the gate electrode 13 is L2. ^- forming a layer 80. For example, d2 is 2500 (Å). Further, by this ion implantation, as shown in FIG. 4B, a P ⁻ layer 80 is also formed below the region to be the drain of the silicon substrate 1 and in a portion separated from the bottom of the gate electrode 13. .

After forming the N ⁻ layer 63 and the P ⁻ layer 80, as shown in FIG. 4C, phosphorus or the like is ion-implanted into the silicon substrate 1 using the gate electrode 13 as a mask, and the silicon substrate in the region to be the drain 1, an N 2 ⁻ layer 73 is formed. In this ion implantation step, phosphorus is ion-implanted with a slope from the drain side above the silicon substrate 1, N from the drain side end portion of the gate electrode 13 to a position entered obliquely to the source direction ^- form a layer 73 To do.

The ion implantation conditions for forming the N 2 ⁻ layer 73 are, for example, ion species: phosphorus (P), dose: 5E + 12 (/ cm ² ), implantation energy: 30 (kev), implantation angle (Tilt): 30 °. Under such ion implantation conditions, the N ⁻ layer 73 is formed so that the depth from the surface of the silicon substrate 1 is d3 and the length of the protruding portion below the gate electrode 13 is L3. For example, d3 is 500 (Å). In addition, by this ion implantation, as shown in FIG. 4C, an N ⁻ layer 73 is also formed in a region which becomes a source of the silicon substrate 1 and is separated from the bottom of the gate electrode 13.

In FIG. 4 (C), N ^- after forming the layer 73 is the same as a normal CMOS fabrication process. That is, sidewall spacers 33 (see FIG. 1) are formed of SiN on the side walls of the gate electrode 13. Next, N-type impurities such as arsenic are ion-implanted into the silicon substrate 1 using the resist pattern 47 that covers the element isolation region and exposes the element region, the sidewall spacer 33, and the gate electrode 13 as a mask.

Then, the silicon substrate 1 into which N-type impurities such as arsenic have been ion-implanted is annealed at 950 (° C.) for 2 minutes in an N ₂ atmosphere to form N ⁺ layers 61 and 71 (see FIG. 1). Thereafter, Ti salicide is formed on the surfaces of the source and drain and the surface of the gate electrode 13. Further, an interlayer insulating film (not shown) and a metal wiring are formed to complete the MOS transistor 100 shown in FIG.

(3) Comparison between Conventional Example and Previous Application (Japanese Patent Application No. 2004-196950) and the Present Invention FIGS. 5A to 5B are diagrams schematically showing cross-sectional structures of various NMOS transistors. FIG. 5A shows a normal NMOS (that is, uniform structure, conventional) in which the source and the drain are symmetric with respect to the channel region, and FIG. 5B shows a conventional example disclosed in Non-Patent Documents 1 to 4 above. 1. FIG. 5C shows an NMOS according to the previous application (Japanese Patent Application No. 2004-196950), and FIG. 5D shows an NMOS according to the present invention.

  The transistor of FIG. 5A has a large drain conductance Gds and a small pinch-off voltage shift amount Vx as characteristics. Here, the shift amount of the pinch-off voltage is a deviation from the theoretical value. The theoretical pinch-off voltage is Vdsat = Vgs−Vth. The Vth in this case is the channel average Vth. By forming a bias in the impurity concentration for the purpose of reducing Gds, Vth at the pinch-off point near the drain decreases, effective Vgs−Vth increases, and the pinch-off point increases and shifts. In addition, the transistor of FIG. 5B has medium characteristics of Gds and a large Vx. The characteristics of the transistor in FIG. 5C are small in Gds and large in Vx. The transistor (the present invention) in FIG. 5D has small Gds and small Vx as characteristics. The reason why Gds can be reduced and Vx can be reduced in the present invention will be described below. 6, 7, 11, and 12, the characteristic data indicated by the transistors in FIGS. 5A to 5D are respectively illustrated as (A) to (D).

FIG. 6 is a diagram showing the Ids-Vds characteristics actually measured in each of the transistors in FIGS. The horizontal axis in FIG. 6 is the drain voltage Vds (volt), and the vertical axis is the drain current (A). Further, here, each transistor is set to have a gate size (W / L) = 15 / 0.35 (μm), Vgs−Vth = 0.3 (volt), and Vth≈0.68 (volt).
As shown in FIG. 6, each of the transistors in FIGS. 5B and 5C has a flat characteristic with a small increase in Ids with respect to an increase in Vds.

  FIG. 7 shows the characteristic of the differential value Gds (= dIds / dVds) between Ids and Vds and Vds in FIG. The horizontal axis of FIG. 7 is the drain voltage Vds (volt), and the vertical axis is the drain conductance Gds (A / volt). The setting of each transistor is the same as in FIG. As shown in FIG. 6, the transistor shown in FIG. 5C shows lower Gds (high gain) than the transistor shown in FIG. 5B. Note that Vx in FIG. 7 is a value indicating the shift amount of the pinch-off voltage in question.

  FIG. 8 is a diagram illustrating a trade-off relationship between Vx and Gds. The horizontal axis of FIG. 8 is the drain voltage Vds (volt), and the vertical axis is the drain conductance Gds (A / volt). In the previous application (that is, the transistor of FIG. 5C), the shift amount (Vx) of the pinch-off voltage is increased (one-dot chain line) instead of decreasing Gds. As a target for solving this problem, the present inventor aimed to achieve both low Gds and low Vx (broken line).

FIG. 9 is a diagram for explaining a trade-off mechanism.
At the pinch-off point shown in FIG. 9, since the impurity doping concentration is low, Vth decreases and the pinch-off voltage increases (= shift amount Vx large). That is, if the implantation amount (pocket implantation amount) of the pocket implantation layer indicated by P in FIG. 9 is reduced, the average Vth from the source to the drain is maintained, so that the doping concentration at the pinch-off point can be increased and the pinch-off voltage can be reduced. However, since the pocket implanter has an important role in securing low Gds characteristics (suppression of DIBL: Drain Induced Barrier Lowering Effect), a decrease in the amount of pocket implant causes an adverse effect of an increase in Gds.

The following equations (ii) to (iV) are equations for deriving a method for reducing the pinch-off voltage shift amount (Vx).
Vdsat = (Vgs−Vth) / (1 + δ) (ii)
δ = γ / (2√ (φb + Vsb) (iii)
γ = (2 · ε · q · Na) / Cox (iV)
In the above formula, Vdsat: pinch-off voltage
δ: coefficient indicating the degree of increase in surface potential
φb: Built-in potential at PN junction
Vsb: substrate bias voltage (in this case, the difference between Vd and WELL potential)
γ: Substrate effect
ε: Dielectric constant of silicon
q: Electron charge
Na: impurity concentration in the depletion layer under the channel
Cox: Capacitance of gate oxide film

  As shown in FIG. 10, when impurity doping (boron in NMOS, phosphorus, arsenic in PMOS) is performed at a position deeper than the surface with a retro-channel implanter, the substrate surface concentration does not change, so that it affects the Vth of inversion layer formation. Impurity boron can be concentrated only in small and deep areas. The deep impurity concentration affects the spread of the depletion layer in the substrate due to the substrate effect γ (see equation (iV)) when a bias is applied to the substrate (PWELL in NMOS). The higher the impurity concentration, the narrower the depletion layer spreads and the higher the surface potential. A coefficient indicating the degree of increase of the surface potential is δ in the formula (iii). When δ increases, even if the numerator (Vgs−Vth) in the formula (ii) is large, δ of the denominator is large, and as a result, the pinch-off voltage Vdsat decreases.

  FIG. 11 is a diagram illustrating a simulation result of Ids-Vds characteristics in each of the transistors in FIGS. 5A, 5C, and 5D. The horizontal axis of FIG. 11 is the drain voltage Vds (volt), and the vertical axis is the drain current (A). Here, the gate dimensions (W / L) = 1 / 0.35 (μm), Vgs−Vth = 0.3 (volt), and Vth≈0.68 (volt) were set for each transistor.

FIG. 12 is a diagram showing a simulation result of Gds-Vds characteristics in each of the transistors in FIGS. 5A, 5C, and 5D. The horizontal axis in FIG. 12 is the drain voltage Vds (volt), and the vertical axis is the drain conductance Gds (A / volt). In FIG. 12, the setting of each transistor is the same as in FIG.
As shown in FIG. 11, the Ids of the transistor of FIG. 5D (the present invention) is slightly lower than that of each of the transistors shown in FIGS. However, as shown in FIG. 12, compared with the transistor of FIG. 5C (previous application), it has almost the same low Gds performance, and the shift amount Vx of the pinch-off voltage in question is reduced by about 0.15 (volt). is made of. This characteristic is advantageous for future circuit configurations at low voltages.

(4) Summary As described above, according to the MOS transistor 100 according to the embodiment of the present invention, in order not to increase the parasitic resistance between the source 60 and the drain 70 even if the MOS transistor 100 is miniaturized, the source 60 And the drain 70 is an LDD having an asymmetric structure. That is, as shown in FIG. 1, N ^- impurity concentration of the layer 73 is kept low in order to reduce the Esat. Further, the impurity concentration of the N ⁻ layer 63 is made higher than that of the N ⁻ layer 73 for the purpose of reducing parasitic resistance. Further, an asymmetrical pocket implant layer that forms the P ⁻ layer 80 only on the source side is combined with this asymmetrical LDD.

  As a result, in a 0.35 (μm) gate length transistor that is classified as a short channel as an analog CMOS transistor, the threshold voltage Vth reduction phenomenon (DIBL) induced by the drain voltage is hardly increased. And the channel modulation effect (CLM) at the pinch-off point can be suppressed at the same time. Therefore, as compared with the prior art, the value of the drain conductance Gds can be reduced without significantly reducing the mutual conductance Gm and the saturation drain current Idsat, and the leakage of the drain output analog signal to the source can be reduced. it can.

Further, according to the MOS transistor 100, the retro channel implantation region 20 causes the impurity concentration inside the silicon substrate 1 to be below the channel region, the source 60 and the drain 70 (that is, deep in the silicon substrate 1). It is high. When the impurity concentration in the deep part is high, when a bias is applied to the silicon substrate 1, the spread of the depletion layer in the silicon substrate 1 becomes narrow, and the surface potential of the silicon substrate 1 becomes higher. As a result, the pinch-off voltage Vdsat (that is, the shift amount Vx) can be lowered.
That is, the trade-off relationship between the drain conductance Gds and the pinch-off voltage Vdsat can be reduced as compared with the previous application (Japanese Patent Application No. 2004-196950).

In this embodiment, the N type corresponds to one conductivity type of the present invention, and the P type corresponds to the opposite conductivity type of the present invention. The silicon substrate 1 corresponds to the semiconductor substrate of the present invention, and the gate oxide film 15 corresponds to the gate insulating film of the present invention. Further, the gate electrode 13 corresponds to the gate electrode portion of the present invention, and the MOS transistor 100 corresponds to the MIS structure transistor of the present invention. The P ⁻ layer 80 corresponds to the pocket implant layer of the present invention, and the N ⁻ layer 63 corresponds to the low concentration source layer of the present invention. The N 2 ⁻ layer 73 corresponds to the low concentration drain layer of the present invention.

In this embodiment, the case where the MOS transistor 100 is an NMOS has been described. However, the present invention is not limited to an NMOS, and may be, for example, a PMOS. In the case of PMOS, the P type corresponds to the “one conductivity type” of the present invention, and the N type corresponds to the “opposite conductivity type” of the present invention.
The present invention can also be applied to a CMOS process having a minimum gate length other than 0.35 (μm), and the same effect as in the case of a CMOS process with 0.35 (μm) can be obtained.

1 is a cross-sectional view illustrating a configuration example of a MOS transistor 100 according to an embodiment. FIG. 5 is a cross-sectional view showing the overhang length in the channel direction of a P ⁻ layer 80, an N ⁻ layer 63, and an N ⁻ layer 73. FIG. 6 is a process diagram (part 1) illustrating the method for manufacturing the MOS transistor 100; FIG. 6 is a process diagram (part 2) illustrating the method for manufacturing the MOS transistor 100; It is a figure which shows typically the cross-sectional structure of various NMOS transistors. It is a figure which shows the measured value of an Ids-Vds characteristic. It is a figure which shows the actual value of a Gds-Vds characteristic. It is a figure which shows the relationship of the trade-off of Vx and Gds. It is a figure explaining the mechanism of trade-off. It is a schematic diagram which shows the structure of the board | substrate effect (gamma) large by retro channel implantation. It is a figure which shows the simulation result of an Ids-Vds characteristic. It is a figure which shows the simulation result of a Gds-Vds characteristic. It is a conceptual diagram which shows the structural example of a general MOS transistor, and its Vd-Id characteristic.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Silicon substrate 5 Well diffused layer 13 Gate electrode 13 'Polysilicon film 15 Gate oxide film 20 Retro channel implantation regions 21, 45, 47 Resist pattern 33 Side wall spacer 43 Element isolation layer 60 Source 61 N ⁺ layer (high concentration source layer )
63 N ⁻ layer (low concentration source layer)
70 drain 71 N ⁺ layer (high concentration drain layer)
73 N ^- layer (low concentration source layer)
80 P ^- layer (pocket implantation layer)
100 MOS transistor

Claims (6)

A semiconductor substrate;
A gate insulating film provided on the semiconductor substrate;
A gate electrode portion provided on the gate insulating film;
A source region and a drain region of one conductivity type provided in a semiconductor substrate exposed from below the gate electrode portion;
Of the opposite conductivity type channel region sandwiched between the source region and the drain region, the opposite conductivity type pocket implant layer provided in a specific portion adjacent to the source region and not adjacent to the drain region;
A retro-channel implant region of an opposite conductivity type provided inside the semiconductor substrate and continuously provided below the channel region, the source region, and the drain region;
MIS structure transistor consisting of
The source region includes a high-concentration source layer containing the one-conductivity type impurity at a high concentration and a low-concentration source containing the one-conductivity type impurity from the lower portion of the high-concentration source layer. A low-concentration source layer provided over the region side,
The drain region includes a high-concentration drain layer containing the one-conductivity type impurity in a high concentration and a low-concentration impurity containing the one-conductivity type impurity from the lower portion of the high-concentration drain layer to the channel of the high-concentration drain layer. A low-concentration drain layer provided over the region side,
The low-concentration source layer contains the impurity of the one conductivity type at a higher concentration than the low-concentration drain layer; and
The retro channel implantation region viewed contains a high concentration of the opposite conductivity type impurity than the channel region, and said pocket implantation layer, the state adjacent to the lightly doped source layer, the low concentration source layer below the the semiconductor substrate is provided over the said specific sites and said retro channel implantation region,
The density value of said opposite conductivity type impurity on the surface from a predetermined depth of the semiconductor substrate have a impurity concentration distribution becomes a peak, and
The retro channel implantation region is
A semiconductor device, wherein the semiconductor device is in contact with the pocket implant layer and is separated from the source region and the drain region . A method of manufacturing the semiconductor device according to claim 1 ,
After the gate electrode portion is formed on the gate insulating film, one conductivity type impurity is obliquely ion-implanted from above the semiconductor substrate on the source region side toward the source region of the semiconductor substrate. Thus, the low concentration source layer is formed. A method of manufacturing the semiconductor device according to claim 1 ,
After forming the gate electrode portion on the gate insulating film, ion implantation of impurities of opposite conductivity type obliquely from above the semiconductor substrate on the source region side toward the specific portion of the semiconductor substrate, A method of manufacturing a semiconductor device, wherein the pocket implant layer is formed. A method of manufacturing the semiconductor device according to claim 1 ,
After the gate electrode portion is formed on the gate insulating film, one conductivity type impurity is obliquely ion-implanted from above the semiconductor substrate on the drain region side toward a portion to be the drain region of the semiconductor substrate. Thus, the method of manufacturing a semiconductor device, wherein the low-concentration drain layer is formed. A method of manufacturing the semiconductor device according to claim 1 ,
Forming the gate electrode portion on the gate insulating film;
Forming the low-concentration source layer by obliquely ion-implanting one conductivity type impurity from above the semiconductor substrate on the source region side toward the source region of the semiconductor substrate;
Forming the pocket implant layer by obliquely implanting ions of opposite conductivity type from above the semiconductor substrate on the source region side toward the specific portion of the semiconductor substrate;
Forming the low-concentration drain layer by obliquely ion-implanting one conductivity type impurity from above the semiconductor substrate on the drain region side toward a portion to be the drain region of the semiconductor substrate. A method for manufacturing a semiconductor device. Before forming the gate insulating film on the semiconductor substrate,
Forming a photoresist mask on the semiconductor substrate in which the channel region, the source region, and the drain region are opened; and
A step of ion-implanting an impurity of an opposite conductivity type into the semiconductor substrate on which the mask is formed to form the retro-channel implant region,
In the step of forming the retro channel implantation region,
One of claims 2 5, characterized in that to keep the concentration value of said opposite conductivity type impurity on the surface from a predetermined depth of the semiconductor substrate is set the ion implantation conditions such that the peak A method for manufacturing a semiconductor device according to one item.

Images