JP2005217576A5 - - Google Patents
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- JP2005217576A5 JP2005217576A5 JP2004019449A JP2004019449A JP2005217576A5 JP 2005217576 A5 JP2005217576 A5 JP 2005217576A5 JP 2004019449 A JP2004019449 A JP 2004019449A JP 2004019449 A JP2004019449 A JP 2004019449A JP 2005217576 A5 JP2005217576 A5 JP 2005217576A5
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- JP
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- Prior art keywords
- transistor
- signal
- signal input
- collector
- input transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Claims (6)
前記電圧−電流変換部が、
前記第1の信号入力トランジスタにダーリントン接続されるとともに前記入力信号の相補信号をベースに入力する第5のトランジスタと、
前記第2の信号入力トランジスタにダーリントン接続されるとともに前記入力信号をベースに入力する第6のトランジスタと、
前記第3の信号入力トランジスタにダーリントン接続されるとともに前記入力信号をベースに入力する第7のトランジスタと、
前記第4の信号入力トランジスタにダーリントン接続されるとともに前記入力信号の相補信号をベースに入力する第8のトランジスタと
を備えることを特徴とする分周器。 An input signal which is a voltage signal having a first signal input transistor and a second signal input transistor constituting a differential pair, and a third signal input transistor and a fourth signal input transistor constituting a differential pair, and voltage for converting the complementary signal into a current signal - a current converter, the voltage - frequency divider phase with each other by using the current signal output from the current conversion unit is provided with a latch unit for generating a 90 over two different signals In
The voltage-current converter is
A fifth transistor that is Darlington connected to the first signal input transistor and that inputs a complementary signal of the input signal as a base;
A sixth transistor that is Darlington connected to the second signal input transistor and that inputs the input signal as a base;
A seventh transistor that is Darlington connected to the third signal input transistor and that inputs the input signal as a base;
Divider, characterized in that it comprises an eighth transistor for inputting a complementary signal of the input signal to the base while being Darlington-connected to said fourth signal input transistors.
前記第1の信号入力トランジスタ及び前記第2の信号入力トランジスタによって構成される差動対と前記第3の信号入力トランジスタ及び前記第4の信号入力トランジスタによって構成される差動対それぞれにデジェネレーション抵抗を設けることを特徴とする分周器。 An input signal which is a voltage signal having a first signal input transistor and a second signal input transistor constituting a differential pair, and a third signal input transistor and a fourth signal input transistor constituting a differential pair, and A 90-degree shift provided with a voltage-current converter that converts a complementary signal into a current signal and a latch that generates two signals that are 90 ° out of phase using the current signal output from the voltage-current converter. In the phaser,
A degeneration resistor is provided for each of the differential pair constituted by the first signal input transistor and the second signal input transistor and the differential pair constituted by the third signal input transistor and the fourth signal input transistor. A frequency divider is provided .
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004019449A JP4416523B2 (en) | 2004-01-28 | 2004-01-28 | Divider |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004019449A JP4416523B2 (en) | 2004-01-28 | 2004-01-28 | Divider |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2005217576A JP2005217576A (en) | 2005-08-11 |
JP2005217576A5 true JP2005217576A5 (en) | 2006-10-12 |
JP4416523B2 JP4416523B2 (en) | 2010-02-17 |
Family
ID=34903655
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2004019449A Expired - Fee Related JP4416523B2 (en) | 2004-01-28 | 2004-01-28 | Divider |
Country Status (1)
Country | Link |
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JP (1) | JP4416523B2 (en) |
-
2004
- 2004-01-28 JP JP2004019449A patent/JP4416523B2/en not_active Expired - Fee Related
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