JP2005217163A - Semiconductor storage device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor storage device capable of stably reading information stored in memory cells configuring the semiconductor storage device. <P>SOLUTION: The semiconductor storage device is provided, which includes a load transistor and drive transistors (L1-D1, L2-D2) connected in series to form an inverter, a transfer transistor T1 connected between an output of the inverter (N1-B1) and a bit line, and a transfer transistor T2 connected between an output of the inverter (N2-B2) and the bit line. The transistors have source/drain diffusion regions 26, 27, 28, 29 on a silicon substrate, first channel regions 16 among the spread regions, and conductor layers 24 via first insulation layers 22 on the first channel region. A strained silicon layer forming the first channel region has a grating constant different from that of its background layer. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention generally relates to the technical field of semiconductor memory devices, and more particularly to a semiconductor memory device capable of stably reading information stored in a memory cell and a method for manufacturing the same.

  In this type of technical field, miniaturization of elements has been increasingly advanced from the viewpoint of high integration and high performance of memories. As miniaturization progresses, adverse effects such as short channel effects, gate leakage, and random variations due to impurities in the channel region become more prominent. In particular, in a static random access memory (SRAM) of a type composed of six transistors, it is known that data cannot be correctly read from a memory cell or operation is slow due to these adverse effects. It has been.

  FIG. 1 shows an equivalent circuit of an SRAM memory cell (SRAM cell) comprising six transistors. As shown in the figure, the SRAM cell includes a pair of CMOS inverters connected between two reference potentials Vdd and GND, and between the output nodes and bit lines of each CMOS inverter (N1-B1, N2-B2). ) Are respectively connected to transfer transistors T1 and T2. The gates of the transfer transistors T1 and T2 are connected to the word line W. Each of the CMOS inverters includes a load transistor L1 (L2) and a driver transistor D1 (D2) connected in series with each other.

  When reading the stored contents of the SRAM cell, the word line W and the bit lines B1, B2 are set to the reference potential Vdd, the transfer transistors T1, T2 are turned on, and the output level from each CMOS inverter is set to the bit lines B1, B2. The stored contents are read based on the voltage change of one bit line. However, as described above, with the miniaturization of elements, it becomes difficult to appropriately read out the stored contents, which may cause a problem that the reading operation becomes unstable. The stability (instability) of the read operation can be evaluated by a voltage parameter called a static noise margin (SNM), and the stability is increased as the SNM increases. The SNM can be expressed using a read characteristic diagram (input / output characteristic diagram) of the SRAM cell.

FIG. 2 shows a read characteristic diagram of the SRAM cell. The vertical axis represents the voltage at the output node N1 (FIG. 1), and the horizontal axis represents the voltage at the output node N2. A curve indicated by reference sign V _N1 indicates a voltage change of the node N1 with respect to a voltage change of the output node N2. Similarly, the curve indicated by reference sign V _N2 shows the voltage change at node N2 with respect to the voltage change at output node N1. The length of one side of the largest square inscribed in the two curves V _N1 and V _N2 is defined as a static noise margin (SNM). In the example shown, the SNM is 0.214 volts.

One technique for increasing the SNM is to increase the β ratio. The β ratio is a ratio (P _D / P _T ) between the driving capability (P _D ) of the driving transistor and the driving capability (P _T ) of the transfer transistor. In general, the driving capability P of a transistor is
P = (W / L) · C G · μ eff ··· (1)
Which is also referred to as a gain factor. Here, W is represents the gate width of the transistor, L represents a gate length, C _G represents a capacitance per unit area of the gate insulating layer, mu _eff is the electron effective mobility (electron mobility) Represent. _CG further
C _G = ε / t = ε _r · ε ₀ / t (2)
Where ε represents the dielectric constant of the insulating layer, ε _r represents the relative dielectric constant of the insulating layer, ε ₀ represents the dielectric constant of vacuum, and t represents the film thickness of the insulating layer. Represent.

As described above, since the β ratio is expressed by P _D / P _T , if the drive capability P _D of the drive transistor can be increased or the drive capability P _T of the transfer transistor can be reduced, the β ratio is increased. be able to. This β ratio is an amount that determines the gradient (dV _out / dV _in ) of the graph in the readout characteristic diagram: (dV _out / dV _in ) =
_{- [(W D / L D} · C D · μ D) / (W T / L T · C T · μ T)] 1/2
Here, the subscript D represents the amount on the drive transistor side, and T represents the amount on the transfer transistor side.

In the invention described in Patent Document 1 described below, the gate insulating layer of the driving transistor, the use of high dielectric constant materials (silicon nitride), is trying to improve the gate capacitance C _G and thus drivability P _D .
JP-A-6-295999

However, as in the invention described in Patent Document 1, when a high dielectric material is used for the gate insulating layer, the threshold voltage of the driving transistor changes. The drive transistor is generally formed of an NMOS transistor. For example, if hafnium oxide (HfO ₂ ) is used for the gate insulating layer, the mobility is degraded by using a high dielectric constant material. As a result, it becomes difficult to sufficiently increase the driving capability (P _D ) of the driving transistor. As shown in equation (1), driving capability, because also proportional to the electron mobility mu _eff well gate capacitance C _G. Therefore, there is a possibility that the β ratio is not improved as intended and the reading operation is not sufficiently stabilized.

On the other hand, in order to increase the β ratio, it is conceivable to decrease the drive capability (P _T ) of the transfer transistor. The read current at the time of reading is transmitted through the transfer transistors T1 and T2. Therefore, if the drive capability (P _T ) of the transfer transistor is reduced, the read current is also reduced, and the read speed may be reduced.

  In product applications in which miniaturization of elements is not so important, the degree of freedom in layout design is relatively large, and it is possible to maintain the driving capability and the like at desired values by appropriately adjusting the gate width and length. However, as the miniaturization progresses, the degree of freedom of such layout design (particularly the degree of freedom directly related to the area) becomes smaller. Therefore, there is a possibility that the above-described problems are particularly noticeable in a highly integrated device that must be considered for miniaturization.

  The present invention has been made to address at least one of the above-described problems, and an object of the present invention is to provide a semiconductor capable of stably reading information stored in a memory cell constituting a semiconductor memory device. To provide a storage device and a manufacturing method thereof.

According to the present invention,
A semiconductor memory device having a cell structure comprising a load transistor and a drive transistor connected in series so as to form an inverter, and a transfer transistor connected between an output of the inverter and a bit line, wherein the drive Transistor is
A silicon substrate has two diffusion regions having a predetermined conductivity and a first channel region between the two diffusion regions, and is further conductive on the first channel region via a first insulating layer. Has a layer,
A strained silicon layer forming the first channel region has a lattice constant different from that of the underlying layer. A semiconductor memory device is provided.

  According to the semiconductor memory device of the present invention, information stored in the memory cell can be read stably.

  Hereinafter, an SRAM cell and a manufacturing method thereof according to an embodiment of the present invention will be described with reference to the drawings. 3 to 10 are for explaining main manufacturing steps particularly related to the present invention.

In the structure prepared in the process shown in FIG. 3, a buffer layer 12, a siligel layer 14, and a strained silicon layer 16 are formed in this order on a semiconductor substrate 10 made of silicon (Si). Has been. The buffer layer 12 is made of silicon and germanium, and the composition in the layer has a structure that gradually changes like Si _(1-x) Ge _x (x = 0 to 2) along the film thickness direction. The siligel layer 14 has a structure represented by Si _0.8 Ge _0.2 and is a lattice-relaxed siligel layer (relaxed SiGe layer). The strained silicon layer 16 is formed on the siligel layer 14 to a thickness of, for example, 25 nm using, for example, UHVCVD. The number of atoms in the strained silicon layer 16 is, for example, 2 × 10 ¹⁷ cm ⁻³ . Due to the difference in lattice constant between the strained silicon layer 16 and the siligel layer 14 as the underlying layer, the mobility of the electrons μ _eff in the in-plane direction of the layer increases in the strained silicon layer 16. The strained silicon layer 16 is formed to have a thickness smaller than a critical thickness. The critical film thickness is a critical film thickness that, when thicker than the film thickness, impairs the effect of increasing electron mobility due to lattice defects or the like.

In the process shown in FIG. 4, after the process such as element isolation and well implantation, the antioxidant film 18 is formed on the entire surface. In this embodiment, silicon nitride (Si ₃ N ₄ ) is used as the antioxidant film 18, but it is naturally possible to use another material layer. However, from the viewpoint of the ease of the manufacturing process, it is desirable to use a silicon nitride film forming process well known in the art.

  In the process shown in FIG. 5, a part of the antioxidant film 18 is removed by, for example, photolithography and etching (right side diagram). The region where the antioxidant film 18 is left is a driver region where the drive transistors D1, D2 (FIG. 1) are formed, and the region where the antioxidant film 18 is removed is the transfer transistors T1, T2 or the load transistors L1, L2. This is a transfer / load area formed.

In the step shown in FIG. 6, an oxide film (SiO ₂ ) is formed on the exposed strained silicon layer to a film thickness of 41 nm, for example. By forming the oxide film, the thickness of the strained silicon layer is reduced from, for example, 25 nm to 7 nm. In this example, the thickness of the oxide film to be formed is calculated as (thickness of the strained silicon layer to be thinned) multiplied by 1 / 0.44: 41 nm = 18 (= 25 -7) nm × 1 / 0.44. However, it is naturally possible to set the oxide film thickness from another viewpoint. The degree of thinning of the strained silicon layer is determined depending on how much the mobility of electrons in the strained silicon layer 17 is lower than the mobility in the strained silicon layer 16. In general, in a strained silicon layer thinner than the critical film thickness, the film thickness affects the intra-layer electron mobility. In general, the thicker the film thickness, the higher the mobility, and the smaller the film thickness.

In the process shown in FIG. 7, the antioxidant film (Si ₃ N ₄ ) in the driver region is removed, and the oxide film 20 in the transfer / load region is thinned to a film thickness of 18 nm, for example. This step may be performed by a mechanical polishing step or a chemical etching step. It is desirable that the surface of the strained silicon layer 16 exposed in the driver region and the surface of the oxide film 20 in the transfer / load region have the same height from the viewpoint of ease of subsequent manufacturing processes. In particular, there may be a step.

In the step shown in FIG. 8, a high dielectric layer 22 made of a material having a dielectric constant higher than that of silicon dioxide (about 3.7) is formed to a thickness of 3 nm, for example. Examples of such a material include Si ₃ N ₄ , HfO ₂ , Al ₂ O ₃ , HfAlO, and the like.

  In the process shown in FIG. 9, a conductive film 24 made of polysilicon is formed on the entire surface with a thickness of 150 nm, for example, and is defined in the shape of the gate electrode of each transistor by, for example, photolithography and etching. Although the dimension of the gate electrode can take various values, in this embodiment, the gate width and length are about 0.1 μm.

  10, source and drain regions 26, 28; 27, 29 are formed using the gate electrode 24 as a mask, and a drive transistor, a load transistor, and a transfer transistor are formed through an annealing process, a wiring process, and the like. In this embodiment, since the driving transistors D1 and D2 and the transfer transistors T1 and T2 are N-type MOS transistors, dopants such as arsenic (As) and phosphorus (P) are implanted into the source and drain regions. Since the load transistors L1 and L2 are P-type MOS transistors, a dopant such as boron (B) is implanted. In this way, a new transistor structure is formed in the driver region and the transfer / load region.

In the driving transistors D1 and D2 (transistors formed in the driver region) in the present embodiment, a high dielectric layer 22 having a high dielectric constant is provided between the gate electrode 24 and the channel region (strained silicon layer) 16. . Therefore, contributes to the gate capacitance C _G per unit area is increased to increase the driving capability. At the same time, the electron mobility may be reduced, but in this embodiment, since the strained silicon layer 16 having a higher electron mobility than usual forms a channel region, the deterioration of the electron mobility is compensated. be able to. By providing not only the high dielectric layer 22 but also the strained silicon layer 16, it becomes possible to increase the driving capability of the transistor, that is, to increase the β ratio and to stabilize the reading operation. On the characteristic diagram as shown in FIG. 2, it is possible to increase the square regarding the static noise margin (SNM) by making the slope of the curve (dV _out / dV _in ) steep.

From the viewpoint of increasing the β ratio, the drive capability of the drive transistors D1 and D2 is improved as described above, and the transfer transistors T1 and T2 (the currents flowing through the load transistors L1 and L2 are small and are ignored for the sake of simplicity). It can be a normal MOS transistor. A normal MOS transistor structure includes a gate insulating layer made of SiO ₂ , a channel layer having a lower electron mobility than that of a strained silicon layer, etc., but also includes a high dielectric layer 22 and a strained silicon layer 17. There is no structure. Even if such a normal MOS transistor structure is adopted for the transfer transistors T1 and T2, it is sufficient if a sufficient read speed is obtained. However, as described above, if the read current passing through the transfer transistor is small, the read speed is slow. There is concern about becoming. Therefore, it is desirable that the transfer transistors T1 and T2 also have a larger driving capability than a normal MOS transistor.

In the above embodiment, the electron mobility is improved by using the strained silicon layer 17 in the channel region between the source and drain regions in the transfer / load region. However, the thickness of the strained silicon layer 17 is smaller than the thickness of the strained silicon layer 16 of the driving transistor. Therefore, the electron mobility mu _eff of the transfer transistors T1, T2 is smaller than the electron mobility mu _eff of the driving transistor D1, D2, greater than the electron mobility mu _eff normal MOS transistor. Further, in the above embodiment, only the high dielectric layer 22 is interposed between the gate electrode 24 of the driving transistor and the channel region (strained silicon layer) 16. A high dielectric layer 22 and a silicon dioxide layer 20 are interposed between the regions (strained silicon layers) 17. Therefore, the gate capacitance _{C G} of the driving transistor D1, D2 is larger than the gate capacitance _{C G} of the transfer transistors T1, T2. When the dielectric constant of the high dielectric layer 22 is ε _High (≈10) and the dielectric constant of the oxide film 20 is ε _OX (≈3.7), the dielectric constant on the drive transistor side is ε _High (≈10). The (synthetic) dielectric constant on the transfer transistor side is (ε _High ⁻¹ + ε _OX ⁻¹ ) ⁻¹ (≈2.7) (for simplicity, parameters such as film thickness are set to 1). Therefore, the same magnitude relationship is generated in the gate capacitance proportional to the dielectric constant. As shown in equation (1), the driving capability of the transistor is proportional to the gate capacitance _{C G} and the electron mobility mu _eff, the transfer transistors T1, T2 of the driving capability _{(P T),} the drive transistor D1, Although it is smaller than the drive capability (P _D ) of D2, it can be made larger than the drive capability (P _ref ) of a normal MOS transistor: P _D > P _T > P _ref . Since P _D > P _T is established, it is possible to increase the β ratio, and P _T > P _ref is established, so that it is possible to prevent the read current from becoming excessively small.

  For convenience of explanation, the drive transistors D1 and D2 are provided with a high dielectric layer 22 on the strained silicon layer 16. However, from the viewpoint of smoothing the interface with the strained silicon layer 16 and promoting the improvement of electron mobility, a thin silicon dioxide layer having a thickness of, for example, 0.8 nm is formed between the high dielectric layer 22 and the strained silicon layer 16. It is advantageous to provide it.

  In the above embodiment, the high dielectric layer 22 is also provided on the transfer transistor side, but this layer is not essential. This is because the insulating layer under the gate electrode 24 of the transfer transistors T1 and T2 only needs to have a dielectric constant smaller than that of the insulating layer under the gate electrode 24 of the driving transistor.

FIG. 11 is a characteristic diagram showing the relationship between static noise margin (SNM) or standardized read current and relative dielectric constant. In the figure, the vertical axis on the left represents SNM (volts), and the vertical axis on the right represents the read current. The current values normalized with the read current related to a normal MOS transistor as a standard value are shown. In the figure, the horizontal axis represents the value of the relative dielectric constant. The graph indicated by the reference symbol “V _SNM ” shows a static noise margin when a transistor (SRAM cell) is formed using materials having various relative dielectric constants. The leftmost point in the graph indicates that the relative dielectric constant is about 3.7 (SiO ₂ ) and the SNM is 0.214 V (see FIG. 2). This point on the graph shows the situation when an SRAM cell is configured by a normal MOS transistor. The second point from the left is that when silicon nitride (Si ₃ N ₄ ) is used as the dielectric material and the relative dielectric constant is about 7.5, the SNM rapidly increases to about 0.32 V (about 1.5 times). Indicates to do. Even if the relative dielectric constant is increased to 10,15, the SNM remains at about 0.33V. On the contrary, when the relative dielectric constant is increased to 20,25, the SNM decreases to about 0,31V, 0.28V.

The graph indicated by the reference symbol “I _read ” shows a normalized read current when a transistor (SRAM cell) is formed using materials having various relative dielectric constants. The leftmost point in the graph indicates that the relative dielectric constant is about 3.7 (SiO ₂ ) and the normalized current is 1. That is, this point is a reference point. The second point from the left is that when silicon nitride (Si ₃ N ₄ ) is used as a dielectric material and the relative dielectric constant is about 7.5, the normalized current is about 1.45 (about 1.5 times). Shows a surge. Unlike the _SNM graph _VSNM , even if the relative permittivity is increased to 10, 15, 20, 25, the normalized current remains at about 1.5.

  Thus, by providing a high dielectric layer and a strained silicon layer in the transistor constituting the SRAM cell (particularly on the driving transistor side), it is possible to improve both the SNM and the read current. Therefore, the SRAM according to this embodiment can stably read the information stored in the SRAM cell and can operate at high speed.

  Hereinafter, the means taught by the present invention will be listed as an example.

(Appendix 1)
A semiconductor memory device having a cell structure comprising a load transistor and a drive transistor connected in series so as to form an inverter, and a transfer transistor connected between an output of the inverter and a bit line, wherein the drive Transistor is
A silicon substrate has two diffusion regions having a predetermined conductivity and a first channel region between the two diffusion regions, and is further conductive on the first channel region via a first insulating layer. Has a layer,
The strained silicon layer forming the first channel region has a lattice constant different from the lattice constant of the underlying layer.

(Appendix 2)
The transfer transistor or the load transistor has two diffusion regions having predetermined conductivity on the silicon substrate, and a second channel region between the two diffusion regions, and further on the second channel region. Having a conductive layer through the second insulating layer;
2. The semiconductor memory device according to claim 1, wherein the strained silicon layer forming the second channel region has a lattice constant different from that of the underlying layer.

(Appendix 3)
The semiconductor memory device according to appendix 2, wherein a film thickness of the first strained silicon region is larger than a film thickness of the second strained silicon region.

(Appendix 4)
The semiconductor memory device according to appendix 2, wherein a dielectric constant of the first insulating layer is higher than a dielectric constant of the second insulating layer.

(Appendix 5)
3. The semiconductor memory device according to claim 2, wherein the underlying layer of the first or second channel region is made of silicon and germanium and forms a lattice-relaxed siligel layer.

(Appendix 6)
The semiconductor memory device according to appendix 2, wherein each of the first and second insulating layers includes a silicon dioxide layer and a high dielectric layer having a dielectric constant higher than that of silicon dioxide.

(Appendix 7)
3. The semiconductor memory device according to claim 2, wherein the thickness of the silicon dioxide layer included in the first insulating layer is smaller than the thickness of the silicon dioxide layer included in the second insulating layer.

(Appendix 8)
A method of manufacturing a semiconductor memory device having a cell structure comprising a load transistor and a drive transistor connected in series so as to form an inverter, and a transfer transistor connected between an output of the inverter and a bit line. ,
Providing a silicon substrate with a strained silicon layer having a lattice constant different from the lattice constant of the underlying layer;
Depositing an antioxidant film on the strained silicon layer;
Removing at least a portion of the antioxidant film belonging to the second region other than the first region for forming the driving transistor;
Depositing a silicon dioxide layer in the region where the antioxidant film has been removed;
Depositing a high dielectric layer having a dielectric constant higher than that of silicon dioxide on the first region and the silicon dioxide layer;
Depositing a conductive layer on the high dielectric layer;
Patterning the conductive film to form a gate electrode, and forming the driving transistor in the first region, and forming the load transistor and the transfer transistor in the second region. Manufacturing method.

(Appendix 9)
The manufacturing method according to claim 8, wherein the antioxidant film is made of a silicon nitride film.

(Appendix 10)
The step of depositing the silicon dioxide layer is performed until the thickness of the strained silicon layer belonging to the second region is smaller than the thickness of the strained silicon layer belonging to the first region. The manufacturing method as described.

(Appendix 11)
The manufacturing method according to appendix 8, wherein the silicon dioxide layer is a thermal oxide film.

(Appendix 12)
The manufacturing method according to claim 8, wherein the step of thinning the strained silicon layer is performed by dry etching and annealing of the strained silicon layer belonging to the second region.

An equivalent circuit diagram of the SRAM cell at the time of reading is shown. The read characteristic figure of a SRAM cell is shown. It is a figure which shows the manufacturing process of SRAM by one Example of this invention. It is a figure which shows the manufacturing process of SRAM by one Example of this invention. It is a figure which shows the manufacturing process of SRAM by one Example of this invention. It is a figure which shows the manufacturing process of SRAM by one Example of this invention. It is a figure which shows the manufacturing process of SRAM by one Example of this invention. It is a figure which shows the manufacturing process of SRAM by one Example of this invention. It is a figure which shows the manufacturing process of SRAM by one Example of this invention. It is a figure which shows the manufacturing process of SRAM by one Example of this invention. FIG. 6 is a characteristic diagram showing a relationship between a noise margin or a normalized read current and a relative dielectric constant.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Silicon substrate 12 Buffer layer 14 Lattice relaxed siligel layer 16, 17 Strained silicon layer 18 Antioxidation film 20 Oxide film 22 High dielectric layer 24 Conductive layer 26, 27 Source region 28, 29 Drain region

Claims (5)

A semiconductor memory device having a cell structure including a load transistor, a drive transistor, and a transfer transistor, wherein the drive transistor includes:
A silicon substrate has two diffusion regions having a predetermined conductivity and a first channel region between the two diffusion regions, and is further conductive on the first channel region via a first insulating layer. Has a layer,
The semiconductor memory device, wherein the first channel region includes a base layer and a strained silicon layer having a lattice constant different from the lattice constant of the base layer. The transfer transistor or the load transistor has two diffusion regions having predetermined conductivity on the silicon substrate, and a second channel region between the two diffusion regions, and further on the second channel region. Having a conductive layer through the second insulating layer;
2. The semiconductor memory device according to claim 1, wherein the strained silicon layer forming the second channel region has a lattice constant different from a lattice constant of the underlying layer.   3. The semiconductor memory device according to claim 2, wherein a film thickness of the first strained silicon region is larger than a film thickness of the second strained silicon region.   The semiconductor memory device according to claim 2, wherein a dielectric constant of the first insulating layer is higher than a dielectric constant of the second insulating layer. A method of manufacturing a semiconductor memory device having a cell structure comprising a load transistor and a drive transistor connected in series so as to form an inverter, and a transfer transistor connected between an output of the inverter and a bit line. ,
Providing a silicon substrate with a strained silicon layer having a lattice constant different from the lattice constant of the underlying layer;
Depositing an antioxidant film on the strained silicon layer;
Removing at least a portion of the antioxidant film belonging to the second region other than the first region for forming the driving transistor;
Depositing a silicon dioxide layer in the region where the antioxidant film has been removed;
Depositing a high dielectric layer having a dielectric constant higher than that of silicon dioxide on the first region and the silicon dioxide layer;
Depositing a conductive layer on the high dielectric layer;
Patterning the conductive layer to form a gate electrode, and forming the drive transistor in the first region and forming the load transistor and the transfer transistor in the second region. Manufacturing method.

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