JP2005216934A - Manufacturing method for semiconductor thin-film, semiconductor device and manufacturing method for thin-film transistor, thin-film transistor and liquid-crystal display and manufacturing method for driver-circuit integral type liquid-crystal display - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a silicon thin-film being composed of a crystal having a large grain size corresponding to a device size and having the small irregularities of the surface of the crystal. <P>SOLUTION: An amorphous silicon thin-film 12a is deposited on an insulating layer 11 formed on a substrate 10. A first laser annealing is carried out to the amorphous silicon thin-film 12a, and a polysilicon thin-film 12b having a crystal-grain size of 0.2 μm or more is formed. A second laser annealing is carried out to the polysilicon thin-film 12b, crystal grains are grown in the parallel direction to the surface of the substrate 10 and the polysilicon thin-film 12c having a size of 4 μm or more in the growth direction of the crystal grains is formed. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a semiconductor thin film, a method for manufacturing a thin film transistor, a thin film transistor, and a liquid crystal display device used in a manufacturing process of a thin film transistor, for example.

  Thin film semiconductor technology is an important technology for forming semiconductor elements such as thin film transistors (TFTs), contact sensors, and photoelectric conversion elements on an insulating substrate. A thin film transistor is a field effect transistor having a MOS (MIS) structure, and is widely applied to a flat panel display such as a liquid crystal display device.

  Liquid crystal display devices are generally thin, lightweight, have low power consumption, and are easy to display color, and are widely used as displays for personal computers or various portable information terminals. When the liquid crystal display device is an active matrix type, a thin film transistor is used as a pixel switching element.

  The active layer (carrier transport layer) of this thin film transistor is made of, for example, a silicon thin film. Silicon thin films are classified into amorphous silicon (amorphous silicon: a-Si) and polycrystalline silicon having a crystalline phase (non-single crystalline crystalline silicon). Polycrystalline silicon is mainly polycrystalline silicon (Poly-Si), and microcrystalline silicon (μc-Si) is also known as polycrystalline silicon. Examples of the semiconductor thin film material other than silicon include SiGe, SiO, CdSe, Te, and CdS.

  The carrier mobility of polycrystalline silicon is about 10 to 100 times larger than the carrier mobility of amorphous silicon. This characteristic is very excellent as a semiconductor thin film material for a switching element. In recent years, a thin film transistor using polycrystalline silicon as an active layer has attracted attention as a switching element capable of forming various logic circuits such as a domino circuit and a CMOS transmission gate because of its high-speed operation. Yes. This logic circuit is required when configuring a driving circuit, a multiplexer, an EPROM, an EEPROM, a CCD, a RAM, and the like for a liquid crystal display device and an electroluminescence display device.

Here, a conventional typical process for forming a polycrystalline silicon thin film will be described below. In this process, an insulating substrate such as glass is used, and a silicon oxide film (SiO ₂ ), for example, is first deposited thereon as an undercoat layer (or buffer layer). Next, an amorphous silicon film (a-Si) is deposited thereon as a semiconductor thin film with a thickness of about 50 nm. Thereafter, a dehydrogenation process is performed to reduce the hydrogen concentration in the amorphous silicon film. Subsequently, melt recrystallization of the amorphous silicon film is performed by an excimer laser crystallization method or the like. Specifically, an excimer laser is irradiated to the amorphous silicon film, thereby changing the amorphous silicon into polycrystalline silicon.

At present, the polycrystalline silicon thin film thus obtained is used as an active layer of an n-channel or p-channel thin film transistor. In this case, the field effect mobility (electron or hole mobility due to the field effect) of the thin film transistor is about 100 to 150 cm ² / (V · sec) in the n-channel type, and 100 cm ² / (V · sec) in the p-channel type. sec). When such a thin film transistor is used, a display device integrated with a drive circuit, that is, a display device in which drive circuits such as a signal line drive circuit and a scan line drive circuit are formed on the same substrate as the pixel switching element is manufactured. be able to. This makes it possible to reduce the manufacturing cost of the display device.

By the way, the current electrical characteristics of thin film transistors can be integrated on a substrate of a display device with a DA converter that converts digital video data into an analog video signal and a signal processing circuit such as a gate array that processes the digital video data. Not as good as it is. In such a case, the current driving capability of the thin film transistor is required to be about 3 to 5 times the current. Thin film transistors are required to have a field effect mobility of about 300 cm ² / (V · sec).

  In order to increase the functionality and added value of a display device, it is necessary to further improve the electrical characteristics of the thin film transistor. When a static memory composed of a thin film transistor is added to each pixel, for example, to have a memory function, the thin film transistor is required to have the same electrical characteristics as when a single crystal semiconductor is used. For these reasons, research is being actively conducted to bring the crystallinity of a silicon thin film closer to a single crystal.

  In recent years, with regard to crystallization of a silicon thin film using laser annealing, the device size can be increased by performing so-called lateral growth in a direction parallel to the substrate surface by some method from the conventional growth in the film thickness direction. Attempts have been made to produce silicon thin films of particle size.

  For example, Matsumura et al. Irradiate non-single crystal Si thin film through excimer laser light through a phase shifter and spatially modulate the intensity of the laser light to perform lateral growth from a low intensity place to a high place. (Non-Patent Document 1). Moreover, the group of Im et al. Reported a process of crystal growth in the moving direction by gradually moving a uniform excimer laser (Non-Patent Document 2, Non-Patent Document 3). Furthermore, in mass production, there is a demand for a method for manufacturing a semiconductor thin film with a high yield that can manufacture a crystallized region having a size sufficient for forming a thin film transistor in each circuit formation portion of a large-area substrate with a high yield.

  In addition, when amorphous silicon is used as the initial film, a phenomenon occurs in which the volume increases when a crystallization process with a large grain size is performed. This is because crystalline silicon has a diamond structure, so that silicon atoms are not packed in the lattice at a high density, and the density is lower than that of amorphous silicon. In the case of amorphous silicon, the density is about 10% higher even in the case of hydrogenated amorphous silicon (a-Si: H) obtained by low-temperature CVD. For this reason, when the lateral growth is performed, the crystal is not crystallized at the same time although there is a slight time difference.

Such unevenness becomes a serious problem in the processes after the crystallization process, particularly in the gate insulating film process necessary for manufacturing the coplanar transistor. That is, it is necessary to set the film thickness of the gate insulating film so that a sufficient distance is ensured between the apex of the convex portion generated on the surface of the active layer and the lower surface of the gate electrode. Can not be thinned. As a result, in the thin film transistor manufactured by the conventional method, the quality of the silicon crystal is improved, and the current drive capability of the transistor is improved, for example, the width of the gate electrode in the source / drain direction (ie, the gate length) is shortened. However, there is a problem in that sufficient improvement in characteristics cannot be obtained even if measures are taken.
Matsumura, Surface Science: vol.21, No.5, p.278-287, 2000 Electronic materials: December 2002, p. 80-84 Tsutsuda, Im: 12th FPD Seminar, Electronic Journal (September 30, 2002)

  The present invention has been made in view of the above-mentioned problems in crystallization of a silicon thin film by laser annealing, and an object of the present invention is to form crystal grains having a large grain size corresponding to the device size with a high yield. An object of the present invention is to provide a method for manufacturing a semiconductor thin film, a method for manufacturing a semiconductor device and a thin film transistor, a method for manufacturing a thin film transistor and a liquid crystal display device, and a liquid crystal display device integrated with a driving circuit.

The method for producing a semiconductor thin film of the present invention comprises:
Forming a non-single crystal semiconductor thin film having a crystal grain size of 0.2 μm or more on a substrate;
Performing laser annealing on the semiconductor thin film to grow crystal grains in a direction parallel to the substrate surface, and forming a semiconductor thin film having a dimension in the crystal grain growth direction of 4 μm or more;
It is provided with.

  When growing crystal grains of a semiconductor thin film in a direction parallel to the substrate surface, there is a strong correlation between the crystal grain size before crystal growth and the crystal grain growth distance. Therefore, by setting the crystal grain size of the semiconductor thin film before crystal growth to a certain level or more (0.2 μm or more), it is possible to grow the crystal grains to a size corresponding to the device size. Thereby, a semiconductor thin film having high mobility can be formed.

  Here, the crystal grain size is a value obtained by integrating the area of each grain from a two-dimensional SEM photograph and calculating the diameter assuming a circle.

  When the crystal grains of the semiconductor thin film are grown in a direction parallel to the substrate surface, the phase of the laser beam is modulated using a phase shifter and irradiated onto the substrate surface, so that the laser beam on the substrate surface is irradiated. It is possible to employ a method in which the intensity is spatially changed, and thereby the crystal grains are grown in the direction of the gradient of the intensity of the laser beam.

  Alternatively, when the crystal grains of the semiconductor thin film are grown in a direction parallel to the substrate surface, the crystal grains are moved in the scan direction by scanning a line-shaped laser in the width direction while overlapping a part thereof. A growing method can also be adopted.

  For example, for the semiconductor thin film having a crystal grain size of 0.2 μm or more, an amorphous semiconductor thin film is formed on the insulating layer formed on the substrate, and this amorphous semiconductor thin film is subjected to laser annealing. Can be formed.

  Thus, by changing the amorphous thin film into a polycrystalline thin film, and then growing the crystal grains of the polycrystalline thin film in a direction parallel to the substrate surface, the amorphous thin film is converted into a polycrystalline thin film. Unevenness on the surface of the polycrystalline thin film due to the volume change at the time of change can be reduced.

  If necessary, a small amount of impurity ions may be implanted into the amorphous thin film before (first) laser annealing to control the threshold value.

  Also, as a polycrystalline thin film before crystal grain growth, it is deposited directly on the insulating layer instead of the polycrystalline thin film obtained by subjecting the amorphous thin film to the (first) laser annealing as described above. It is also possible to use a polycrystalline thin film. In that case, for example, if a polysilicon thin film is deposited by using the CVD method, a sufficient growth distance can be secured in the subsequent (second) laser annealing.

Moreover, the manufacturing method of the thin film transistor of the present invention in which the manufacturing method of the semiconductor thin film described above is incorporated,
Forming a gate insulating film on the resulting semiconductor thin film; and
Forming an electrode layer on the gate insulating film;
Forming a source region and a drain region on both sides of the gate electrode;
Is provided.

In addition, the manufacturing method of the drive circuit integrated liquid crystal display device of the present invention includes:
A driver circuit integrated type in which an n-channel thin film transistor serving as a switching element of a pixel and p-channel and n-channel thin film transistors constituting a driver circuit disposed around the pixel region are formed on a common substrate. In the manufacturing method of the liquid crystal display device,
Depositing an amorphous silicon thin film on an insulating layer formed on a substrate;
Applying a first laser annealing to the amorphous silicon thin film to form a polysilicon thin film having a crystal grain size of 0.2 μm or more;
Applying a second laser annealing to the polysilicon thin film to grow crystal grains in a direction parallel to the substrate surface, and forming a polysilicon thin film having a dimension in the crystal grain growth direction of 4 μm or more;
Patterning the resulting polysilicon thin film into islands,
Depositing a gate insulating film on the patterned polysilicon thin film;
Depositing an electrode layer on the gate insulating film and then patterning the electrode layer to form a gate electrode;
Using this gate electrode as a mask, donor ions are implanted into an island-shaped polysilicon thin film on which an n-channel thin film transistor is to be formed later, and an acceptor is formed on the island-shaped polysilicon thin film on which a p-channel thin film transistor is to be formed later. A step of implanting ions;
Annealing the polysilicon thin film to form source and drain regions on both sides of the gate electrode;
Depositing an interlayer insulating film on the gate electrode and the gate insulating film;
Forming contact holes in the interlayer insulating film and the gate insulating film, and then connecting electrode wirings to the gate electrode, the source region, and the drain region through these contact holes, and
It is provided with.

  In this case, in order to form two types of thin film transistors of n channel type and p channel type on a common substrate, before performing the first laser annealing on the amorphous silicon thin film, A small amount of donor ions is implanted into a region where a p-channel thin film transistor is formed later.

  Alternatively, before the first laser annealing is performed on the amorphous silicon thin film, a small amount of acceptor ions are implanted into a region where an n-channel thin film transistor is formed later in the amorphous silicon thin film.

  Alternatively, before the first laser annealing is performed on the amorphous silicon thin film, a small amount of donor ions are implanted into a region in the amorphous silicon thin film where a p-channel thin film transistor is to be formed later, followed by an n-channel thin film transistor. A small amount of acceptor ions is implanted into the region where the is formed.

  According to the method of the present invention, a crystallized region having a predetermined size can be formed with a high yield. Unevenness on the surface of the semiconductor thin film after the crystallization step can be suppressed to a small level.

  Therefore, according to the method of the present invention, the thickness of the gate insulating film formed on the semiconductor thin film after the crystallization step can be reduced to a desired thickness. As a result, the load of the subsequent process is reduced, the reliability of the manufactured thin film semiconductor device is improved, and the current driving capability can be increased.

  Moreover, according to the method of the present invention, it is possible to form a semiconductor thin film having high mobility. Therefore, by using such a semiconductor thin film, a thin film semiconductor element having a high speed and a high current driving capability can be manufactured. As a result, on the common substrate, in addition to the n-channel thin film transistor used for pixel switching, the p-channel and n-channel thin film transistors that form the drive circuit arranged around the pixel region can be formed. It becomes possible. Furthermore, a static memory for displaying a still image can be provided in each pixel by using a CMOS inverter constituted by such p-channel and n-channel thin film transistors.

  In order to grow a crystallized region laterally by laser annealing a semiconductor thin film and stably form a crystallized region of 4 μm or more with a high yield, the grain size of the seed crystal is I found it an important element. This embodiment is an example of a crystallization method for obtaining crystal grains having a lateral growth distance of 4 μm or more when crystal grains having a grain diameter of 0.2 μm or more are used as seed crystals. Furthermore, this embodiment is an example in which high-speed switching is enabled by forming a thin film transistor in a region crystallized by a crystallization method and constructing a liquid crystal display device integrated with a drive circuit using this thin film transistor. .

  As a result of laser annealing with crystal grains having a grain size of 0.2 μm or more as a seed crystal, the unevenness generated on the surface of the crystallized region with a large grain size is greatly reduced, and the gate insulating film is made thinner. The effect of was obtained. Although the causal relationship of the decrease in the unevenness of the surface of the crystallized region is not clear, since the crystal grains of 0.2 μm or more are used as seed crystals, in the crystallization process, it is greatly compared with the amorphous semiconductor film. It is considered that the volume change is small and the surface strain is reduced. This embodiment is an example obtained by laser annealing an amorphous semiconductor film as means for obtaining crystal grains having a grain size of 0.2 μm or more as seed crystals.

(Example 1)
First, an outline of a manufacturing process of a thin film transistor (TFT) to which the laser annealing method according to the present invention is applied will be described. FIG. 1 to FIG. 21 show an example of the manufacturing process of such a TFT. This thin film transistor is used to constitute a display device, for example, a pixel switching element array of an active matrix liquid crystal display device, a drive circuit, and a DA converter.

In the process shown in FIG. 1, an undercoat layer (insulating layer) 11 is deposited on an insulating substrate 10 made of quartz (or non-alkali glass or the like). In this example, the undercoat layer 11 is a silicon oxide film (SiO ₂ ) and is deposited using a plasma CVD method. The thickness of the undercoat layer 11 is 80 nm, and the conditions for plasma CVD are a substrate temperature of 330 ° C. and a deposition time of 5 minutes.

  Next, an example of a process for forming a non-single crystal semiconductor thin film having a crystal grain size of 0.2 μm or more will be described. In the step shown in FIG. 2, a non-single crystal semiconductor thin film such as a silicon thin film 12 a (amorphous silicon thin film) is deposited on the undercoat layer 11. In this example, the silicon thin film 12a is deposited using the plasma CVD method, and the film thickness is 50 nm.

  In this example, a small amount of doping for controlling the threshold value is not employed, but it may be performed as necessary. When a small amount of doping is performed, a doping gas such as diborane is mixed with the source gas during deposition of the silicon thin film, or ion doping is performed after deposition of the silicon thin film.

  At this point, the silicon thin film 12a is amorphous silicon. In the method of the present invention as means for forming crystal grains having a crystal grain size of 0.2 μm or more, as will be described below, this amorphous silicon thin film is subjected to laser annealing to be changed to a polycrystalline silicon thin film. Next, for crystallization, the polycrystalline silicon thin film is further subjected to laser annealing to promote crystal lateral growth (growth in a direction parallel to the substrate surface) to form crystal grains corresponding to the device size.

  FIG. 3 shows a first laser annealing step as means for forming crystal grains having a crystal grain size of 0.2 μm or more. During the laser annealing, the crystal grain size of the polycrystalline silicon thin film can be controlled by changing the irradiation energy. The process conditions for polycrystallization will be further described later.

  Next, a crystallization process is performed using a crystal grain having a crystal grain size of 0.2 μm or more as a seed crystal. This crystallization step is a step of forming a semiconductor thin film having crystal grains having a crystal grain growth dimension of 4 μm or more. FIG. 4 shows a second laser annealing step for crystallization. The details of this laser annealing step are described in Non-Patent Document 1 mentioned above. During this laser annealing, the distribution of the laser intensity is spatially changed, so that fine crystal grains of the silicon thin film 12b (polycrystalline silicon thin film) are grown in the lateral direction and changed into large crystal grains corresponding to the device size. be able to.

This step is performed using a light source that outputs energy light for melting the silicon thin film 12a, for example, a KrF excimer laser as energy light. The KrF excimer laser is irradiated with a silicon thin film 12b through a phase shifter 13, as shown in FIG. 4, after the light intensity is homogenized by a homogenizer (not shown). As a result, the silicon thin film 12b is heated. . By passing through the phase shifter 13, the laser intensity can be spatially modulated, the light intensity distribution R can be modulated in an inverse peak shape, and lateral growth from a point where the laser intensity is weak to a strong point can be realized. . As a result, crystal grains can be grown in a direction parallel to the surface of the substrate 10 to form a silicon thin film 12b having a crystal grain growth direction dimension of 4 μm or more. The energy density of the KrF excimer laser is, for example, 350 mJ / cm ² . In the thus heated silicon thin film 12b, fine polycrystalline silicon grows and changes to polycrystalline silicon having a large grain size. The process conditions for this lateral growth will be further described later. Thus, a feature of the present invention is that laser annealing for crystallization is performed on a non-single-crystal semiconductor thin film having a crystal grain size of 0.2 μm or more. As a result, a crystallized region having a predetermined size can be formed with a high yield. If laser annealing for crystallization is performed on a simple non-single crystal semiconductor thin film, a crystallized region of a predetermined size cannot be formed with a high yield. By forming an insulating film (not shown) on the silicon thin film 12b before the crystallization step, it is effective to form a larger crystallization region due to the heat storage effect of the insulating film during the crystallization step.

  In the step shown in FIG. 5, a resist is applied on the silicon thin film 12c (polycrystalline silicon thin film after lateral growth). The resist film 14 is selectively exposed using a photomask and then selectively removed. By this step, a resist pattern 14 corresponding to the region where the TFT is formed is formed.

In the step shown in FIG. 6, a dry etching process is performed using the resist pattern 14 as a mask, and the silicon thin film 12c is patterned. In this dry etching process, for example, CF ₄ and O ₂ are used as an etching gas.

  In the step shown in FIG. 7, the resist pattern 14 on the silicon thin film 12c is removed.

  In the step shown in FIG. 8, the gate insulating film 15 is formed on the silicon thin film 12c. In this example, the gate insulating film 15 is a silicon oxide film and is deposited by the LP-CVD method. The thickness of the gate insulating film 15 is 80 nm, and the LP-CVD conditions are that the substrate temperature is 500 ° C. and the deposition time is 45 minutes.

  In the step shown in FIG. 9, the electrode layer 16 is formed on the gate insulating film 15. In this example, the electrode layer 16 is aluminum and is deposited by sputtering. The thickness of the electrode layer 16 is 100 nm, and the sputtering conditions are a substrate temperature of 100 ° C. and a deposition time of 10 minutes.

  In the step shown in FIG. 10, a resist is applied on the electrode layer 16. This resist film is selectively exposed using a photomask and then removed. As a result, a resist pattern 17 corresponding to the gate electrode region is formed.

In the step shown in FIG. 11, a dry etching process is performed using the resist pattern 17 as a mask, and the electrode layer 16 is patterned. As a result, the electrode layer 16 is removed leaving a region corresponding to the gate electrode 18. In this dry etching process, for example, BCl ₃ and CH ₄ are used as an etching gas.

  In the step shown in FIG. 12, the resist pattern 17 on the gate electrode 18 is removed.

  In the step shown in FIG. 13, an impurity is added to the silicon thin film 12c using the gate electrode 18 as a mask. When the polysilicon TFT is an n-channel type, phosphorus is ion-implanted into the silicon thin film 12c. On the other hand, when the polysilicon TFT is a p-channel type, boron is ion-implanted into the silicon thin film 12c. For example, a logic circuit such as a CMOS inverter is composed of a combination of an n-channel polysilicon TFT and a p-channel polysilicon TFT. For this reason, the ion implantation of one of the n-channel type polysilicon TFT and the p-channel type polysilicon TFT is performed in a state where the silicon thin film 12c of the other polysilicon TFT is covered with a mask such as a resist that prevents undesired ion implantation. Done.

  After ion implantation for each of the n-channel polysilicon TFT and the p-channel polysilicon TFT, an annealing process is performed to activate the silicon thin film 12. In this example, the annealing process is performed in a nitrogen atmosphere at a substrate temperature of 600 ° C. for 3 hours. As a result, a source region 19 and a drain region 20 having a high impurity concentration are formed in the silicon thin film 12 c on both sides of the gate electrode 18.

  In the step shown in FIG. 14, an interlayer insulating film 21 is formed on the gate insulating film 15 and the gate electrode 18. In this example, the interlayer insulating film 21 is a silicon oxide film and is deposited by a plasma CVD method. The thickness of the interlayer insulating film 21 is 500 nm, and the conditions for plasma CVD are that the substrate temperature is 500 ° C. and the deposition time is 20 minutes.

  In the step shown in FIG. 15, a resist is applied on the interlayer insulating film 21. This resist film is selectively exposed using a photomask and then removed. As a result, a resist pattern 22 corresponding to each contact hole for the gate electrode, the source electrode, and the drain electrode is formed.

In the step shown in FIG. 16, dry etching is performed using the resist pattern 22 as a mask, and the interlayer insulating film 21 and the gate insulating film 15 are patterned. As a result, contact holes for partially exposing the gate electrode 18, the source region 19 and the drain region 20 are formed. In this dry etching process, for example, CHF ₃ is used as an etching gas.

  In the step shown in FIG. 17, the resist pattern 22 on the interlayer insulating film 21 is removed.

  In the step shown in FIG. 18, the electrode layer 23 is formed on the interlayer insulating film 21. The electrode layer 23 is connected to the gate electrode 18, the source region 19, and the drain region 20 through contact holes. In this example, the electrode layer 23 is an aluminum layer and is deposited by sputtering. The thickness of the interlayer insulating film 21 is 100 nm, and the sputtering conditions are a substrate temperature of 100 ° C. and a deposition time of 10 minutes.

  In the step shown in FIG. 19, a resist is applied on the electrode layer 23. This resist film is selectively exposed using a photomask and then removed. As a result, a resist pattern 24 corresponding to the upper gate electrode, the source electrode, and the drain electrode is formed.

In the step shown in FIG. 20, a dry etching process using the resist pattern 24 as a mask is performed, and the electrode layer 23 is patterned. Thereby, the upper gate electrode 18A, the source electrode 25, and the drain electrode 26 are formed on the interlayer insulating film 21. In this dry etching process, for example, BCl ₃ and CH ₄ are used as an etching gas.

  In the step shown in FIG. 21, the resist pattern on the upper gate electrode 18A, the source electrode 25, and the drain electrode 26 is removed.

  Through the above steps, a thin film transistor in which a semiconductor active layer is formed of silicon crystals corresponding to the device size is completed.

  Here, the first laser annealing process shown in FIG. 3 and the second laser annealing process shown in FIG. 4 will be further described. As described above, in the method of the present invention, first, this amorphous silicon is subjected to normal laser annealing to be changed to polycrystalline silicon, and then this polycrystalline silicon is further subjected to laser annealing to obtain a crystallization region. The crystal grain size corresponding to the device size is formed.

FIG. 22 shows the relationship between the fluence of laser irradiated when polycrystallizing an amorphous silicon thin film and the crystal grain size of the resulting polycrystalline silicon thin film. In this example, the thickness of the amorphous silicon thin film (silicon initial film) before laser irradiation is 50 nm, the irradiation fluence of the laser is changed, and the relationship between the irradiation fluence and the crystal grain size of the obtained polycrystalline silicon. Seeking. According to this example, it is understood that an irradiation fluence of about 320 mJ / cm ² or more is required to obtain a value of 0.2 μm or more as the crystal grain size of polycrystalline silicon.

  Here, the crystal grain size was specifically measured using Image-Pro Plus manufactured by Planetron Co., Ltd. This apparatus uses an image processing technique to determine the area of each crystal grain, and based on this, calculates the value of the diameter assuming a circle.

  The surface of the silicon thin film (12b: FIG. 3) is a surface on which an element such as a coplanar polysilicon TFT is formed, and the gate electrode (18: FIG. 12) of the polysilicon TFT is gate-insulated above it. It is formed through a film (15: FIG. 12) and faces a part of a silicon thin film (12c: FIG. 12) which becomes an active layer. Most of the electrons or holes which are carriers move mainly in the surface region near the gate insulating film in the active layer. In this case, if the number of so-called grain boundaries between the crystals in the active layer of the TFT is large, the electrical characteristics deteriorate accordingly. Therefore, in order to reduce the number of crystal grain boundaries with the same device size, it is necessary to enlarge each crystal grain.

  In the above embodiment, the inventors have found that when the polycrystalline silicon thin film is subjected to laser annealing to grow crystal grains in the lateral direction, the crystal of the polycrystalline silicon thin film before the second laser annealing is obtained. It was found that there is a correlation between the grain size and the crystal grain size after the second laser annealing. This relationship is shown in FIG.

  In the above embodiment, FIG. 23 shows the crystal grain size (horizontal axis) of the polycrystalline silicon thin film before laser annealing (before lateral growth) and the crystal grain growth distance (vertical axis) after the second laser annealing. The relationship is shown. Although the polycrystalline silicon thin film before the second laser annealing is considered to have almost melted, the influence of the crystal grain size before the second laser annealing appears remarkably in the lateral growth distance. Yes. According to this example, when the crystal grain size before the second laser annealing is 0.2 μm or more, a lateral growth distance of 4 μm or more is obtained after the second laser annealing. Assuming that the gate length is about 1.5 μm, if the crystal grain size is about 4 μm, it is possible to manufacture a MOS transistor having no crystal grain boundary across the carrier moving direction in the semiconductor active layer. That is, it can be seen that the numerical value of 4 μm corresponds to the minimum crystal grain size that can satisfy the above requirements. Furthermore, if the crystal grain size before the second laser annealing is 0.3 μm, a lateral growth distance of 5 μm or more can be obtained.

  FIG. 24 shows the relationship between the field effect mobility of the TFT manufactured using the above method and the crystal grain size of the polycrystalline silicon thin film before laser annealing. It can be seen that the larger the crystal grain size before laser annealing, the larger the crystal grain size after lateral growth by laser annealing, and accordingly, the field effect mobility of the manufactured TFT is improved.

(Example 2)
In the above example, the crystal is obtained by spatially changing the laser light intensity distribution using the phase shifter 13 during the laser annealing of the polycrystalline silicon thin film (the process shown in FIG. 4). Although the grains are grown in the lateral direction, the crystal grains can be grown in the lateral direction by other methods.

  For example, as shown in FIG. 25, by scanning a line-shaped laser having a laser spot width of several μm, for example, while overlapping each other by 50%, the crystal generated in the first laser shot is continuously in the scanning direction. The crystal grains can be grown in the lateral direction. The details of this laser annealing process are described in Non-Patent Documents 2 and 3.

  FIG. 26 shows the relationship between the field effect mobility of the TFT manufactured using the above method and the crystal grain size of the polycrystalline silicon thin film before annealing. Although there is no difference as in the previous examples, it can be seen that as the crystal grain size before annealing increases, the crystal grain size after lateral growth increases, and as a result, field effect mobility is improved. .

(Example 3)
Next, an example in which the thin film transistor obtained by the above method is applied to an active matrix liquid crystal display device will be described. This liquid crystal display device has a normal display mode and a still image display mode.

  27 shows a schematic circuit configuration of the liquid crystal display device, FIG. 28 shows a schematic cross-sectional structure of the liquid crystal display device, and FIG. 29 shows an equivalent circuit around the display pixel shown in FIG.

  The liquid crystal display device includes a liquid crystal display panel 100 and a liquid crystal controller 102 that controls the liquid crystal display panel 100. The liquid crystal display panel 100 has a structure in which, for example, a liquid crystal layer LQ is held between the array substrate AR and the counter substrate CT, and the liquid crystal controller 102 is disposed on a drive circuit substrate independent of the liquid crystal display panel 100.

  The array substrate AR includes a plurality of pixel electrodes PE arranged in a matrix in the display region DS on the glass substrate, a plurality of scanning lines Y (Y1 to Ym) formed along a row of the plurality of pixel electrodes PE, and a plurality of pixels. Of the plurality of signal lines X (X1 to Xn), the signal lines X1 to Xn, and the scanning lines Y1 to Ym formed along the column of the pixel electrodes PE, respectively. In response to the scanning signal, the pixel switching element 111 that takes in the video signal Vpix from the corresponding signal line X and applies it to the corresponding pixel electrode PE, the scanning line driving circuit 3 that drives the scanning lines Y1 to Ym, and the signal lines X1 to Xn. A signal line driving circuit 4 is provided.

  Each pixel switching element 111 is composed of, for example, an n-channel polysilicon thin film transistor, and is formed on the array substrate AR using the method described above. The scanning line driving circuit 103 and the signal line driving circuit 104 are composed of a plurality of polysilicon thin film transistors, and are integrally formed on the array substrate AR together with the thin film transistors of the pixel switching elements 111 using the method described above. The

  The counter substrate CT includes a single counter electrode CE that is arranged to face the plurality of pixel electrodes PE and is set to the common potential Vcom, a color filter (not shown), and the like.

  The liquid crystal controller 102 receives, for example, a video signal and a synchronization signal supplied from the outside, and generates a video signal Vpix, a vertical scanning control signal YCT, and a horizontal scanning control signal XCT in the normal display mode. The vertical scanning control signal YCT includes, for example, a vertical start pulse, a vertical clock signal, an output enable signal ENAB, and the like, and is supplied to the scanning line driving circuit 103. The horizontal scanning control signal XCT includes a horizontal start pulse, a horizontal clock signal, a polarity inversion signal, and the like, and is supplied to the signal line driving circuit 104 together with the video signal Vpix.

  The scanning line driving circuit 103 includes a shift register, and is controlled by the vertical scanning control signal YCT so as to sequentially supply a scanning signal for conducting the pixel switching element 111 to the scanning lines Y1 to Ym every one vertical scanning (frame) period. Is done. The shift register selects one of the plurality of scanning lines Y1 to Ym by shifting the vertical start pulse supplied every vertical scanning period in synchronization with the vertical clock signal, and outputs the output enable signal ENAB. The scanning signal is output to the selected scanning line with reference. The output enable signal ENAB is maintained at a high level during the effective scanning period of the vertical scanning (frame) period in order to permit the output of the scanning signal, and vertical blanking excluding the effective scanning period from the vertical scanning period. In the period, it is maintained at a low level in order to inhibit the output of the scanning signal.

  The signal line driving circuit 104 includes a shift register and a sampling output circuit, and in the one horizontal scanning period (1H) in which each scanning line Y is driven by the scanning signal, the input video signal is subjected to serial-parallel conversion to display a pixel. The analog video signal Vpix sampled as a signal is controlled by the horizontal scanning control signal XCT so as to be supplied to the signal lines X1 to Xn, respectively.

  The counter electrode CE is set to the common potential Vcom as shown in FIG. In the normal display mode, the common potential Vcom is inverted in level from one of 0 V and 5 V every horizontal scanning period (H) to the other, and in the still image display mode, one of 0 V and 5 V is generated every frame period (F). The level is inverted from one to the other. In the normal display mode, instead of inverting the level of the common potential Vcom every horizontal scanning period (H) as in this example, the level of the common potential Vcom is set every 2H or every frame period (F), for example. You can invert it.

  The polarity inversion signal is supplied to the signal line drive circuit 4 in synchronization with the level inversion of the common potential Vcom. In the normal display mode, the signal line driving circuit 104 inverts the level of the video signal Vpix having an amplitude of 0 V to 5 V in response to the polarity inversion signal so as to have the opposite polarity with respect to the common potential Vcom. In the still image display mode, the operation is stopped after outputting the gradation-controlled video signal for the still image.

  The liquid crystal layer LQ of the liquid crystal display panel 100 is normally white which performs black display by applying a video signal Vpix of 5V to the pixel electrode PE with respect to a common potential Vcom of 0V set to the counter electrode CE, for example. Yes, as described above, in the normal display mode, the H common inversion drive is employed in which the potential relationship between the video signal Vpix and the common potential Vcom is alternately inverted every horizontal scanning period (H), and in the still image display mode. Frame inversion driving is employed in which the frames are alternately inverted every frame.

  The display screen is composed of a plurality of display pixels PX. Each display pixel PX includes a pixel electrode PE, a counter electrode CE, and a liquid crystal material of a liquid crystal layer LQ sandwiched therebetween. Furthermore, a plurality of static memory units 113 and a plurality of connection control units 114 are provided for the plurality of display pixels PX, respectively. As shown in FIG. 29, the pixel electrode PE is connected to a pixel switching element 111 that selectively takes in the video signal Vpix on the signal line X, and is further set to a potential Vcs equal to the common potential Vcom of the counter electrode CE, for example. Capacitively coupled to the auxiliary capacitance line. The pixel electrode PE and the counter electrode CE constitute a liquid crystal capacitance via a liquid crystal material, and the pixel electrode PE and the auxiliary capacitance line constitute an auxiliary capacitance 112 parallel to the liquid crystal capacitance without passing through the liquid crystal material.

  When the pixel switching element 111 is driven by a scanning signal from the scanning line Y, the pixel switching element 111 applies the video signal Vpix on the signal line X to the display pixel PX. The auxiliary capacitor 112 has a capacitance value sufficiently larger than the liquid crystal capacitor, and is charged / discharged by the video signal Vpix applied to the display pixel PX. When the auxiliary capacitor 112 holds the video signal Vpix by this charging / discharging, the video signal Vpix compensates for the fluctuation of the potential held in the liquid crystal capacitor when the pixel switching element 111 becomes non-conductive, and thereby the pixel electrode The potential difference between the PE and the counter electrode CE is maintained.

  Further, each static memory portion 113 includes p-channel polysilicon thin film transistors Q1, Q3, Q5 and n-channel polysilicon thin film transistors Q2, Q4, which are formed based on the method described above. Each static memory unit 113 holds the video signal Vsig applied from the pixel switching element 111 to the display pixel PX. Each connection control unit 114 includes n-channel polysilicon thin film transistors Q6 and Q7, and not only controls the electrical connection between the display pixel PX and the static memory unit 113 but also the video held in the static memory unit 113. Also serves as a polarity control circuit that controls the output polarity of the signal.

  The thin film transistors Q1 and Q2 of the static memory unit 113 constitute a first inverter circuit INV1 that operates with a power supply voltage between the power supply terminal Vdd (= 5V) and the power supply terminal Vss (= 0V), and the thin film transistors Q3 and Q4 are power supply terminals. A second inverter INV2 that operates with a power supply voltage between Vdd and Vss is configured. The output terminal of the first inverter circuit INV1 is connected to the input terminal of the second inverter circuit INV2 via the thin film transistor Q5 controlled via the scanning line Y, and the output terminal of the second inverter circuit INV2 is connected to the first inverter circuit. Connected to the input terminal of INV1. The thin film transistor Q5 is not turned on in the frame period in which the pixel switching element 111 is turned on by the rise of the scanning signal from the scanning line Y, and is turned on in the next frame period of this frame. As a result, the thin film transistor Q5 is maintained in the non-conductive state at least until the pixel switching element 111 takes in the video signal Vpix.

  In the still image display mode, the thin film transistors Q6 and Q7 are controlled by polarity control signals POL1 and POL2, which are alternately set to a high level every frame, for example. The thin film transistor Q6 is connected between the pixel electrode PE and the input terminal of the second inverter circuit INV2 and the output terminal of the first inverter circuit INV1 via the thin film transistor Q5. The thin film transistor Q7 is connected to the pixel electrode PE and the first inverter circuit. It is connected between the input terminal of INV1 and the output terminal of the second inverter circuit INV2.

  This liquid crystal display device is a drive circuit integrated type in which the scanning line driving circuit 103, the signal line driving circuit 104, the static memory unit 113, and the connection control unit 114 are arranged on the same array substrate AR as the pixel switching element 111. Yes. Here, the scanning line driving circuit 103, the signal line driving circuit 104, the static memory unit 113, and the connection control unit 114 are formed using the process described above together with the pixel switching element 111. Therefore, productivity can be improved together with the performance of the liquid crystal display device.

  In addition, as in the example illustrated in FIG. 29, by providing the static memory unit 113, a function of holding a video signal supplied to the display pixel PX can be obtained. In the still image display mode, the video signal is supplied from the static memory unit 113 to the display pixel PX. In this state, the scanning line driving circuit 103 and the signal line driving circuit 104 are suspended to reduce the power consumption of the entire display device. It is possible to reduce.

  In addition, this invention is not limited to the above-mentioned embodiment, It can deform | transform variously in the range which does not deviate from the summary. For example, in the above example, a KrF excimer laser (λ = 248 nm) is used as energy light, but other examples include XeCl (λ = 308 nm), XeF (λ = 351 nm), and ArF (λ = 193 nm). Is available. In this case, the energy used can be optimized and used according to the absorption coefficient and thickness of the initial film.

  Further, in the above-described embodiment, an example in which laser annealing is performed as a step of forming a semiconductor thin film having a crystal grain size of 0.2 μm or more has been described. However, the crystal grain size is 0.2 μm or more by other means. A semiconductor thin film may be formed, for example, an amorphous semiconductor film may be formed in a high temperature atmosphere.

It is sectional drawing which shows an example of the manufacturing process of the thin-film transistor based on this invention, Comprising: The figure which shows the state which deposited the undercoat layer on the glass substrate. Sectional drawing which shows the process of depositing an amorphous silicon thin film. Sectional drawing which shows the process of performing the 1st laser annealing to the silicon thin film which consists of amorphous silicon. Sectional drawing which shows the process of performing the 2nd laser annealing to the silicon thin film which consists of polysilicon. Sectional drawing which shows the state which apply | coated the resist on the silicon thin film which the process of the horizontal growth was complete | finished. Sectional drawing which shows the process of patterning a silicon thin film using a resist pattern. Sectional drawing which shows the state which removed the resist pattern from the silicon thin film patterned. Sectional drawing which shows the process of depositing a gate insulating film on a silicon thin film. Sectional drawing which shows the process of depositing an electrode layer on a gate insulating film. Sectional drawing which shows the process of forming a resist pattern on an electrode layer. Sectional drawing which shows the process of patterning an electrode layer using a resist pattern. Sectional drawing which shows the state which removed the resist pattern from the patterned gate electrode. 10 is a cross-sectional view illustrating a step of implanting impurities into a source region and a drain region using a gate electrode as a mask. FIG. Sectional drawing which shows the process of depositing an interlayer insulation film on a gate electrode. Sectional drawing which shows the process of forming a resist pattern on an interlayer insulation film. Sectional drawing which shows the process of forming a contact hole in an interlayer insulation film and a gate insulating film using a resist pattern. Sectional drawing which shows the state in which the contact hole was formed in the interlayer insulation film and the gate insulation film. Sectional drawing which shows the process of depositing an electrode layer on an interlayer insulation film. Sectional drawing which shows the process of forming a resist pattern on an electrode layer. Sectional drawing which shows the process of patterning an electrode layer using a resist pattern. FIG. 4 is a cross-sectional view illustrating a state where a resist pattern is removed from above a patterned source electrode, drain electrode, and upper gate electrode to complete a thin film transistor. Sectional drawing which shows the relationship between the irradiation fluence of the laser irradiated to an amorphous silicon thin film, and the crystal grain diameter of the polysilicon thin film obtained as a result. Sectional drawing which shows the relationship between the crystal grain diameter of the polysilicon thin film before lateral growth, and lateral growth distance. The figure which shows the relationship between the crystal grain diameter of the polysilicon thin film before lateral growth, and the field effect mobility of TFT manufactured through the process of lateral growth. The figure which shows the other example of the process for growing the crystal grain of a polysilicon thin film to a horizontal direction. The figure which shows the relationship between the crystal grain diameter of the polysilicon thin film before lateral growth, and the field effect mobility of TFT manufactured through the process of lateral growth. FIG. 22 is a diagram showing a schematic circuit configuration of an active matrix liquid crystal display device using a thin film transistor formed in the steps shown in FIGS. FIG. 28 is a diagram illustrating a schematic cross-sectional structure of the liquid crystal display device illustrated in FIG. 27. FIG. 28 is a diagram showing an equivalent circuit around the display pixel shown in FIG. 27.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Insulating substrate, 11 ... Undercoat layer (insulating layer), 12a ... Silicon thin film (amorphous silicon), 12b ... Silicon thin film (polysilicon), 12c ... Silicon thin film (lateral direction) Polysilicon after growth), 13... Phase shifter, 14, 17, 22... Resist pattern (resist film), 15... Gate insulating film, 16. , 18A ... upper gate electrode, 19 ... source region, 20 ... drain region, 100 ... liquid crystal display panel, 102 ... liquid crystal controller, 103 ... scanning line drive circuit, 104 ... Signal line drive circuit, 111... Pixel switching element, 112... Auxiliary capacitor, 113... Static memory unit, 114.

Claims (8)

Forming a non-single crystal semiconductor thin film having a crystal grain size of 0.2 μm or more on a substrate;
Performing laser annealing on the semiconductor thin film to grow crystal grains in a direction parallel to the substrate surface, and forming a semiconductor thin film having a dimension in the crystal grain growth direction of 4 μm or more;
A method for producing a semiconductor thin film, comprising:   2. The laser annealing according to claim 1, wherein the crystal grains are grown in a gradient direction of the intensity of the laser beam by irradiating the surface of the semiconductor thin film substrate with the phase modulation of the laser beam using a phase shifter. The manufacturing method of the semiconductor thin film of description.   The semiconductor thin film having a crystal grain size of 0.2 μm or more was formed by forming an amorphous semiconductor thin film on the insulating layer formed on the substrate, and laser annealing the amorphous semiconductor thin film. The method for producing a semiconductor thin film according to claim 1, wherein the method is a thin film.   A semiconductor device comprising a thin film transistor circuit formed on crystal grains of a semiconductor thin film manufactured by the method for manufacturing a semiconductor thin film according to claim 1. Forming a non-single crystal semiconductor thin film having a crystal grain size of 0.2 μm or more on an insulating layer formed on a substrate;
Applying laser annealing to the non-single crystal semiconductor thin film to grow crystal grains in a direction parallel to the substrate surface, and forming a semiconductor thin film having a dimension in the crystal grain growth direction of 4 μm or more;
Forming a gate insulating film on the resulting semiconductor thin film; and
Forming an electrode layer on the gate insulating film;
Forming a source region and a drain region on both sides of the gate electrode;
The manufacturing method of the thin-film transistor provided with.   A thin film transistor manufactured by the method for manufacturing a thin film transistor according to claim 5.   A liquid crystal display device using a thin film transistor manufactured by the method for manufacturing a thin film transistor according to claim 5 as a pixel switching element. A drive circuit integrated type in which an n-channel thin film transistor serving as a switching element of a pixel and p-channel and n-channel thin film transistors constituting a drive circuit disposed around the pixel region are formed on a common substrate. In the manufacturing method of the liquid crystal display device,
Depositing an amorphous silicon thin film on an insulating layer formed on a substrate;
Applying a first laser annealing to the amorphous silicon thin film to form a polysilicon thin film having a crystal grain size of 0.2 μm or more;
Subjecting the polysilicon thin film to a second laser annealing, growing crystal grains in a direction parallel to the substrate surface, and forming a polysilicon thin film having a dimension in the crystal grain growth direction of 4 μm or more;
Patterning the resulting polysilicon thin film into islands,
Depositing a gate insulating film on the patterned polysilicon thin film;
Depositing an electrode layer on the gate insulating film and then patterning the electrode layer to form a gate electrode;
Using this gate electrode as a mask, donor ions are implanted into an island-shaped polysilicon thin film on which an n-channel thin film transistor is to be formed later, and an acceptor is formed on the island-shaped polysilicon thin film on which a p-channel thin film transistor is to be formed later. A step of implanting ions;
Annealing the polysilicon thin film to form source and drain regions on both sides of the gate electrode;
Depositing an interlayer insulating film on the gate electrode and the gate insulating film;
Forming contact holes in the interlayer insulating film and the gate insulating film, and then connecting electrode wirings to the gate electrode, the source region, and the drain region through these contact holes, and
A method for manufacturing a liquid crystal display device integrated with a drive circuit.

Images