JP2005215722A - Disk array device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data transfer method to a high-speed host device in a disk array device with a large-capacity cache memory. <P>SOLUTION: Data stored in respective cache memories within host adaptor parts 20 and 30 and disk adaptor parts 40 and 50 are also stored in a cache memory part 10. When writing of data is requested from host devices 100 and 101, the host adaptor part 20 stores the data concerned to the own cache memory, and transfers them to the host adaptor part 40. When data are requested from the host devices 100 and 101, the host adaptor part 20 returns, if the data concerned are cached, the cached content to the host device of the requester. When the data are not cached, the data is transmitted to, in the order corresponding to, a disk device 200 (or 201), the disk adaptor part 40, the host adaptor part 20, the host device of the request source. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a disk array device, and more particularly to a disk array device having cache memories distributed therein.

  Disk array devices are required to have high performance and enhanced reliability. For this reason, the disk array device has a high-speed interface part with the host device and the disk device, a high-speed common data transfer path inside the disk array device, a redundant disk device, and a double data transfer path and cache memory. Has been made.

  FIG. 9 is a block diagram showing the configuration of a conventional disk array apparatus. As shown in FIG. 9, FIG. 9 is obtained by removing the selector unit and the cache memory unit from FIG.

  The disk array device 1 includes a control unit 2 and disk devices 200 and 201. The control unit 2 includes cache memory units 10a and 10b, host adapter units 20 and 30, and disk adapter units 40 and 50.

  The host device 100 is connected to the host adapter unit 20, the host device 101 is connected to the host adapter unit 30, the disk device 200 is connected to the disk adapter unit 40, and the disk device 201 is connected to the disk adapter unit 50 via a high-speed serial bus. ing. The host adapter units 20 and 30 and the disk adapter units 40 and 50 and the cache memory units 10a and 10b are connected by a high-speed parallel bus or a high-speed serial bus. The host adapter units 20 and 30 and the disk adapter units 40 and 50 share the memory included in the cache memory units 10a and 10b.

  For example, when there is a disk data read request from the host device 100 and the requested data is stored in the cache memory units 10a and 10b (at the time of a cache hit), the disk device 200 or 201 is accessed. The data is sent from the cache memory to the host device 100 without performing the above. By transmitting data in this way, high speed access is realized.

Further, data is stored twice between the cache memory units 10a and 10b. Therefore, even if a failure occurs in any part of the data transfer path, the data transfer is not stopped by switching the access path, and the data is not lost in at least one of the cache memory units 10a and 10b. ing. With such a configuration, the reliability of the disk array device is enhanced.
JP 2000-99281 A (page 5, FIG. 1)

  In the configuration of the cache memory (hereinafter referred to as a shared cache type), the host adapter units 20 and 30 and the disk adapter units 40 and 50 share the cache memory units 10a and 10b. For this reason, in the cache memory units 10a and 10b, access requests from the host devices 100 and 101 and access requests to the disk devices 200 and 201 are concentrated. As a result, access of data transfer requests from the host devices 100 and 101 is performed. There was a problem that performance deteriorated.

  The present invention has been made in view of the above problems, and in response to a disk access request from a host device, while realizing the high-speed access performance of a distributed cache type (that is, a configuration including individual caches), a shared cache An object of the present invention is to provide a disk array device capable of maintaining the high reliability of a mold.

A disk array device according to a first aspect of the present invention includes:
Multiple disk units;
A disk-side adapter unit comprising an individual cache memory and accessible to the plurality of disk devices;
A host-side adapter unit that includes an individual cache memory and is connected to a host device via a data transfer path;
A shared cache memory that stores data that is accessed from the disk-side adapter unit and the host-side adapter unit, and that is stored in individual cache memories included in each of the disk-side adapter unit and the host-side adapter unit. A disk array device,
The host-side adapter unit is
When data to be written to the disk device is received from the host device, the data is written to the shared cache memory and the individual cache memory provided therein, and the disk side adapter unit is requested to write the data to the disk device. And write to any disk unit,
When a request to read data from the disk device is received from the host device, it is determined whether or not the data is stored in the individual cache memory provided by the host device. The data stored in the individual cache memory is transmitted to the requesting host device, and when it is determined that the data is not stored, the data is read from the disk device and transmitted to the requesting host device.

  According to the present invention, the cache data is duplicated by the individual cache memory provided in the host adapter unit and the shared cache memory. This increases the reliability of the cache data. When data is requested from the host device (reading), if the requested data is stored in the individual cache memory, the data is transmitted to the requesting host device. For this reason, the data access performance at the time of a cache hit is improved as compared with the case where only the shared cache memory is used.

In the above disk array device,
When data is read from the disk device, the disk-side adapter unit can write the data to the shared cache memory and the individual cache memory included in the disk-side adapter unit.
In this case, when the host-side adapter unit receives a request to read data from the disk device, the host-side adapter unit determines whether or not the data is stored in the individual cache memory provided by itself. Is determined, the request is transferred to the disk side adapter unit,
When the disk-side adapter unit further receives a request for reading data from the disk device from the host-side adapter unit, the disk-side adapter unit determines whether or not the data is stored in the individual cache memory provided by itself. When it is determined that the data is stored, the data stored in the individual cache memory is transmitted to the requesting host device, and when it is determined that the data is not stored, the data is read from the disk device, Sent to the requesting host device.

In the above disk array device,
The disk array device preferably includes the plurality of disk devices so as to have redundancy.
In this case, the host-side adapter unit is
When data to be written to the disk device is received from the host device, redundant data is created based on the data, and the data and the redundant data are transferred to the individual cache memory and the shared cache memory included in the self device. Write, request the disk side adapter unit to write the data to the disk device, write to any disk device,
When a request for reading data from the disk device is received from the host device, the individual cache memory provided by itself, the individual cache memory provided by the disk-side adapter unit, the shared cache memory, and the disk device, Based on the data read from one of the data, data to be transmitted to the host device is generated and transmitted to the requesting host device.

  According to the present invention, the redundancy of data to be written to the disk device is increased. For example, even if one of the plurality of disk devices becomes inaccessible, the data can be recovered. Therefore, the reliability of data is increased.

In the above disk array device,
It is desirable that the host side adapter unit and the disk side adapter unit are multiplexed.
in this case,
Each host side adapter unit is connected to at least one disk side adapter unit,
Each disk-side adapter unit is connected to at least one host-side adapter unit.

  According to the present invention, the redundancy inside the disk array device is increased and the reliability is improved.

  According to the present invention, the data transfer performance at the time of a cache hit is improved as compared with the conventional disk array device while having the same reliability as the shared cache memory.

  Next, the best mode for carrying out the invention will be described in detail with reference to the drawings. FIG. 1 is a diagram showing an example in which a disk array device according to an embodiment of the present invention is connected to two host devices. In FIG. 1 and FIG. 9, the same components are assigned the same numbers.

  As shown in the figure, a disk array device 1 according to an embodiment of the present invention includes disk devices 200 and 201 and a control unit 2, and a host device 100 and host data transfer via a host data transfer path 190. It is connected to the host 101 via the path 191. The disk array device 1 receives a data write request from the host devices 100 and 101 and temporarily stores the data in a cache memory provided in the control unit 2. In response to a data read request from the host devices 100 and 101, the requested data is read from the cache memory or the disk devices 200 and 201 provided in the control unit 2, and the read data is transmitted to the requesting host device. . Data is read from the cache memory when a cache hit occurs, and from the disk devices 200 and 201 when a cache miss occurs.

  The host devices 100 and 101 are information processing devices such as a super computer, mainframe, server device, and personal computer, and execute application programs and output the results. The host device 100 is connected to the host adapter units 20 and 30 of the disk array device 1 via the host data transfer path 190. Similarly, the host device 101 is connected to the host adapter units 20 and 30 of the disk array device 1 via the host data transfer path 191. The host devices 100 and 101 read and write various data stored in the disk array device 1 when executing application programs. In the present embodiment, the host data transfer paths 190 and 191 are, for example, high-speed serial buses.

  The disk devices 200 and 201 are storage devices such as magnetic disks, for example. The disk device 200 is connected to the disk adapter units 40 and 50 inside the control unit 2 via a disk data transfer path 290. Similarly, the disk device 201 is connected to the disk adapter units 40 and 50 in the control unit 2 via a disk data transfer path 291.

  The control unit 2 includes a cache memory, receives data from the host devices 100 and 101, writes the data to the disk devices 200 and 201, and caches the data. In the present embodiment, the cache is duplicated. In response to an instruction from the host devices 100 and 101, the requested data is read from the disk devices 200 and 201, or the cached data is read and transmitted to the requesting host device.

  As shown in FIG. 1, the control unit 2 includes a cache memory unit 10, host adapter units 20 and 30, and disk adapter units 40 and 50 (hereinafter collectively referred to as each adapter unit). . Each adapter unit and the cache memory unit 10 are connected via the inter-cache memory transfer path 300. The host adapter unit 20 and the disk adapter unit 40 are connected via an inter-adapter transfer path 301, and the host adapter unit 30 and the disk adapter unit 50 are connected via an inter-adapter transfer path 302. In this embodiment, the cache memory transfer path 300 and the adapter transfer paths 301 and 302 use a parallel bus or a serial bus capable of high-speed transfer.

  The host adapter units 20 and 30 and the disk adapter units 40 and 50 have the same configuration and function. Therefore, the function and configuration of each part of the host adapter unit 20 and the disk adapter unit 40 will be described below.

  The cache memory unit 10 caches data stored in memories provided in the host adapter units 20 and 30 and the disk adapter units 40 and 50, respectively. The configuration of such a cache memory unit 10 is shown in FIG.

  As shown in the figure, the cache memory unit 10 includes a cache memory control unit 11 and a shared cache memory unit 12. Further, the cache memory control unit 11 includes a crossbar switch 111 and a memory control unit 112, and the shared cache memory unit 12 includes a plurality of blocks of memories 13, 14, 15, and 16.

  The cache memory control unit 11 is connected to the host adapter units 20 and 30 and the disk adapter units 40 and 50 via the inter-cache memory transfer path 300. The cache memory control unit 11 transmits / receives data to / from each of these adapter units, and controls reading / writing of the memory inside the shared cache memory unit 12.

  The crossbar switch 111 is connected to the host adapter units 20 and 30, the disk adapter units 40 and 50, and the memory control unit 112, and controls data exchange between these units.

  The memory control unit 112 receives data from the host adapter units 20 and 30 and the disk adapter units 40 and 50 via the crossbar switch 111, and writes the data to a memory (module) inside the shared cache memory unit 12. Further, the data is read from the memory (module) inside the shared cache memory unit 12 and the data is transmitted to the requesting host adapter units 20 and 30 and the disk adapter units 40 and 50 via the crossbar switch 111.

  The shared cache memory unit 12 includes a plurality of memories 13, 14, 15, 16, and the like, and is recognized as one storage device (cache memory) from the outside (for example, the host adapter unit 20). The shared cache memory unit 12 stores at least the same data as the data stored in the cache memories provided in the host adapter units 20 and 30 and the disk adapter units 40 and 50, respectively.

  Each of the memories 13, 14, 15, and 16 is, for example, a storage device such as a RAM (Random Access Memory) or a memory module that is an aggregate thereof. The memories 13, 14, 15, and 16 can be accessed as one memory from the outside of the shared cache memory unit 12. In the present embodiment, the total storage capacity of the memories 13, 14, 15, 16 is equal to or greater than the total storage capacity of the cache memory provided by the host adapter units 20, 30 and the disk adapter units 40, 50, respectively. And In addition, there is no particular restriction on the use area of the memories 13, 14, 15, and 16, which can be accessed from all the host adapter units and the disk adapter units, and is stored in the cache memory provided in each of these adapter units. Any configuration is possible as long as all data is stored.

  Returning to FIG. 1, the host adapter unit 20 includes, for example, a microprocessor (Micro Processing Unit, MPU), a memory, and the like, and connects the host devices 100 and 101, the disk adapter unit 40, and the cache memory unit 10. . The configuration of such a host adapter unit 20 is shown in FIG. As shown in the figure, the host adapter unit 20 includes a bridge 21, an individual cache memory 22 (hereinafter simply referred to as a memory 22), and an adapter control unit 23.

  The bridge 21 is configured by a crossbar switch or the like, and controls data exchange among the host devices 100 and 101, the cache memory unit 10, the disk adapter unit 40, the memory 22, and the adapter control unit 23. As illustrated, the bridge 21 includes interface controllers 211 and 214, a crossbar switch 212, a memory controller 213, and a DMA (Direct Memory Access) controller 215.

  The interface control unit 211 controls data transfer among the adapter control unit 23, the host devices 100 and 101, the DMA control unit 215, and the crossbar switch 212, and write requests transmitted from the host devices 100 and 101 It manages processing such as read requests.

  The crossbar switch 212 is connected to the interface control units 211 and 214, the memory control unit 213, and the DMA control unit 215, and controls data exchange between these units.

  The memory control unit 213 controls writing of data transmitted from the crossbar switch 212 to the memory 22 and reading of data from the memory 22.

  The interface control unit 214 controls data transfer among the disk adapter unit 40, the cache memory unit 10, and the crossbar switch 212.

  The DMA control unit 215 manages DMA transfer between the memory control unit 213 and the interface control unit 211.

  The memory 22 is composed of a memory module that is an aggregate such as a RAM. The memory 22 caches write data to the disk devices 200 and 201 transmitted from the host devices 100 and 101. In contrast to the shared cache memory unit 12, the memory 22 is an individual cache memory.

  The adapter control unit 23 includes an MPU, a RAM serving as a work area, a ROM (Read Only Memory), and the like, and controls the operation of the entire host adapter unit 20.

  Returning to FIG. 1, the disk adapter unit 40 includes, for example, an MPU, a memory, and the like, and connects the disk devices 200 and 201, the host adapter unit 20, and the cache memory unit 10. The configuration of such a disk adapter unit 40 is shown in FIG. As shown, the disk adapter unit 40 includes a bridge 41, an individual cache memory 42 (hereinafter simply referred to as a memory 42), and an adapter control unit 43. The disk device 200 is connected to the disk data transfer path 290 and the disk device 201 is connected to the disk data transfer path 291. In this embodiment, it is assumed that the disk data transfer paths 290 and 291 are parallel buses or serial buses capable of high-speed transfer.

  The bridge 41 is configured by a crossbar switch or the like, and controls data exchange among the disk devices 200 and 201, the cache memory unit 10, the host adapter unit 20, the memory 42, and the adapter control unit 43. The internal configuration and function of the bridge 41 are the same as those of the bridge 21.

  The memory 42 is composed of a memory module that is an aggregate such as a RAM. The memory 42 caches data read from the disk devices 200 and 201. In contrast to the shared cache memory unit 12, the memory 42 is an individual cache memory.

  The adapter control unit 43 includes an MPU, a RAM, a ROM serving as a work area, and the like, and controls the operation of the entire disk adapter unit 40.

  Next, embodiments of the present invention will be described with reference to the drawings. In this embodiment, a case where the host device 100 attempts to read / write data stored in the disk device 200 will be described. Here, the host adapter unit 20 and the disk adapter unit 40 are the primary system, and the host adapter unit 30 and the disk adapter unit 50 are the secondary system.

  First, a writing process from the host device 100 to the disk device will be described. FIG. 5 is a flowchart for explaining the writing process of the host adapter unit 20 in the writing process.

  When there is a data write request to the disk device from the host device 100 to the host adapter unit 20 via the host data transfer path 190, the host adapter unit 20 starts a write process.

  When the interface control unit 211 of the host adapter unit 20 receives a data write request from the host device 100 to the disk device (step S101), the interface control unit 211 transmits a request to the adapter control unit 23. When the adapter control unit 23 recognizes that there is a write request, the adapter control unit 23 acquires data to be written transmitted from the host device 100 from the interface control unit 211. Then, this data is transmitted to the crossbar switch 212 via the DMA control unit 215. The crossbar switch 212 transfers the received data to the memory control unit 213 and the interface control unit 214. Further, the memory control unit 213 writes this data in the memory 22. Further, the interface control unit 214 transfers this data to the cache memory unit 10 via the inter-cache memory transfer path 300. The cache memory unit 10 (cache memory control unit 11) writes data to the memories 13, 14, 15 and 16 in the shared cache memory unit 12 (step S102). That is, in step S102, the same data is written in the memory 22 and the shared cache memory unit 12.

  Next, the interface control unit 211 transmits information indicating that the writing has been completed to the host device 100 (step S103). Finally, the interface control unit 211 transfers the write request to the disk adapter unit 40 via the inter-adapter transfer path 301 (step S104), and ends the write process.

  When the memory control unit 112 in the cache memory unit 10 receives write data from the host adapter unit 20 via the crossbar switch 111, the memory control unit 112 writes the data to any of the memories 13, 14, 15, and 16.

  On the other hand, when the disk adapter unit 40 receives a write request from the host adapter unit 20 via the inter-adapter transfer path 301, the disk adapter unit 40 starts a write process. This writing process will be described with reference to FIG.

  As shown in the figure, when the bridge 41 receives a write request from the host adapter unit 20 (step S201), the bridge 41 reads cached data to be written from the memory 22 (step S202). Then, the bridge 41 transfers the write request and data to be written to the disk device 200 requested as the write destination (step S203). Then, the disk device 200 writes the data. Then, the disk adapter unit 40 ends the writing process.

  Next, the reading process will be described with reference to FIGS. FIG. 7 is a flowchart for explaining the read processing of the host adapter unit 20 and FIG. 8 is the disk adapter unit 40, respectively. When a data read request is transmitted from the host device 100 to the host adapter unit 20, the host adapter unit 20 starts a read process.

  When the interface control unit 211 of the host adapter unit 20 receives a data read request from the disk device from the host device 100, the interface control unit 211 transmits a request to the adapter control unit 23. The adapter control unit 23 determines whether the requested data is cached in the memory 22 (FIG. 7, step S301). More specifically, the adapter control unit 23 causes the memory control unit 213 to determine whether data is cached in the memory 22.

  When the interface control unit 211 determines that the requested data is stored (cached) in the memory 22 (step S301: YES), the DMA control unit 215 performs the memory 22 via the memory control unit 213. Read the requested data from. Then, the read data is transmitted to the requesting host apparatus 100 via the crossbar switch 212 and the host data transfer path 190 (step S302), and the read process is terminated.

  On the other hand, if it is determined that the requested data is not stored in the memory 22 (step S301: NO), the read request is transferred to the disk adapter unit 40 (step S303), and the host adapter unit 20 Waiting or other data processing (reading, writing, etc.) is executed until information indicating completion of reading is transmitted from the unit 40.

  Thereafter, when the host adapter unit 20 receives information indicating the completion of reading from the disk adapter unit 40 (step S304), the bridge 21 reads the data from the memory 42 and transmits it to the requesting host apparatus 100 ( Step S305), the reading process is terminated.

  On the other hand, when the disk adapter unit 40 receives a read request from the host adapter unit 20, the disk adapter unit 40 starts a read process. First, the bridge 41 determines whether or not the requested data is cached in the memory 42 (FIG. 8, step 401).

  When the bridge 41 determines that the requested data is cached in the memory 42 (step S401: YES), the information indicating that the reading is completed is transmitted to the requesting host adapter unit 20 (step S402). ), The reading process is terminated.

  On the other hand, if the bridge 41 determines that the requested data is not stored in the memory 42 (step S401: NO), the read request is transferred to the disk device 200 and the requested data is read from the disk device ( Step S403). Next, the bridge 41 stores the read data in the memory 42 (step S404) and transmits it to the cache memory unit 10 (step S405). Finally, information indicating that the reading has been completed is transmitted to the requesting host adapter unit 20 (step S406), and the reading process is terminated.

  According to the above-described operation, data is cached in the host adapter unit 20 and the cache memory unit 10 when data is written, and data is cached in the disk adapter unit 40 and the cache memory unit 10 when data is read from the disk device. And the cache is duplicated. At the time of reading data, the host adapter unit 20 and the disk adapter unit 40 determine whether the data is cached. If the data is cached, the cached data is transmitted to the requesting host device. Therefore, the load on the cache memory unit 10 is reduced as compared with the conventional configuration.

  In the above-described embodiment, even if the combination of the requesting host device and the requesting disk device is changed, the operations of the host adapter unit 20 and the disk adapter unit 40 do not change. In the above-described embodiment, for example, when data is read and written between the host device and the disk device via the host adapter unit 20 and the disk adapter unit 50, the data is transferred via the cache memory unit 10. Forward.

  In the configuration of FIG. 1, when the host adapter unit 20 is in an operation stop state due to a failure, the host devices 100 and 101 can continue to access the disk via the host adapter unit 30. . In addition, even when the host adapter unit 20 is in an operation stop state after the host adapter unit 20 requests the disk adapter unit 40 to read data from the disk, the data is read from the cache memory unit 10 via the host adapter unit 30. Data transfer is possible. The same can be realized even when one of the disk adapter units 40 and 50 is stopped.

  Further, even when the cache memory unit 10 becomes inoperable due to a failure, the disk can be continuously accessed via the inter-adapter transfer paths 301 and 302.

  In addition, this invention is not limited to the said embodiment, A various deformation | transformation and application are possible.

  For example, data to be written to the disk device may be composed of a data body and redundant data that is a parity or error correction code for detecting and correcting an error in the data. For example, in this case, in step S102 described above, the interface control unit 211 transfers the data to the adapter control unit 23, and the adapter control unit 23 generates a parity and an error correction code for the data. The interface control unit 211 writes data in the memory 22, the cache memory unit 10, the disk device 200, and the like. In steps S302 and S305, redundant data is removed from the data read from the memory 22, the disk adapter unit 40 (memory 42), or the disk devices 200 and 201, and transmitted to the requesting host device. As a redundant data generation method, a generation method used in other known RAID (blueundant Arrays of Inexpensive Disks) can be used.

  Further, as a method of writing to the cache memory, the case of the write-through method has been described in the above embodiment, but a known method such as a write-back method may be adopted. For example, in the case of the write back method, data is written to the disk devices 200 and 201 when the cached data is swept from the shared cache memory unit 10 and the memory 22. In this case, step S104 in FIG. 5 and each step in FIG. 6 are executed as processes independent of the processes from step S101 to step S103 in FIG.

  Further, in step S202 and step S305, data stored in the shared cache memory unit 12 may be read.

  Further, in the above embodiment, the determination is made as to whether or not the requested data is cached for only the memory of each adapter unit. However, even if this determination is performed in the cache memory unit 10. Good.

  In FIG. 1, the host adapter unit 20 and the disk adapter unit 50 and the host adapter unit 30 and the disk adapter unit 40 may be connected by a data transfer path equivalent to the inter-adapter transfer paths 301 and 302. By connecting in this way, even when the cache memory unit 10 becomes inoperable due to a failure, the transfer path can be performed without being limited to the inter-adapter transfer paths 301 and 302.

  When the inter-cache memory transfer path 300 and the inter-adapter transfer paths 301 and 302 are parallel buses capable of high-speed transfer, the inter-cache memory transfer path 300 in FIG. 1 is realized by a shared bus to which all adapters are connected. May be. The inter-adapter transfer paths 301 and 302 in FIG. 1 may also be realized by a shared bus to which all adapters are connected.

  Although the host adapter unit 20 and the disk adapter unit 50 and the host adapter unit 30 and the disk adapter unit 40 are not connected in FIG. 1, they may be connected. In FIG. 1, only one cache memory unit 10 is mounted. However, a plurality of cache memory units 10 may be mounted and multiplexed.

  In the above embodiment, the number of host adapter units and the number of disk adapter units are two, but the number may be more than that. In this case, each host adapter unit is connected to one or more disk adapter units via an inter-adapter transfer path. The disk adapter unit is also connected to one or more host adapter units.

  In addition, the adapter control units 23 and 43 may be multiplexed. The same applies to the memories 22, 42 and the like.

1 is a block diagram of a disk array device according to an embodiment of the present invention. FIG. 2 is a block diagram illustrating an internal configuration of a cache memory unit in FIG. 1. It is a block diagram which shows the internal structure of the host adapter part of FIG. It is a block diagram which shows the internal structure of the disk adapter part of FIG. It is a flowchart for demonstrating the write processing of the host adapter part concerning the operation example of this invention. It is a flowchart for demonstrating the write processing of the disk adapter part concerning the operation example of this invention. It is a flowchart for demonstrating the read processing of the host adapter part concerning the operation example of this invention. It is a flowchart for demonstrating the read process of the disk adapter part concerning the operation example of this invention. It is a block diagram of a conventional disk array device.

Explanation of symbols

1 disk array device 2 control unit 10, 10a, 10b cache memory unit 11, 11a, 11b cache memory control unit 111 crossbar switch 112 memory control unit 12 shared cache memory unit 13, 14, 15, 16 memory 20, 30 host adapter unit 21, 41 Bridge 211 Interface control unit 212 Crossbar switch 213 Memory control unit 214 Interface control unit 215 DMA control unit 22, 42 Memory (individual cache memory)
23, 43 Adapter control unit 40, 50 Disk adapter unit 100, 101 Host device 190, 191 Host data transfer path 200, 201 Disk device 290, 291 Disk data transfer path 300 Cache memory transfer path 301, 302 Adapter transfer path

Claims (4)

Multiple disk units;
A disk-side adapter unit comprising an individual cache memory and accessible to the plurality of disk devices;
A host-side adapter unit that includes an individual cache memory and is connected to a host device via a data transfer path;
A shared cache memory that stores data that is accessed from the disk-side adapter unit and the host-side adapter unit, and that is stored in individual cache memories included in each of the disk-side adapter unit and the host-side adapter unit. A disk array device,
The host-side adapter unit is
When data to be written to the disk device is received from the host device, the data is written to the shared cache memory and the individual cache memory provided therein, and the disk side adapter unit is requested to write the data to the disk device. And write to any disk unit,
When a request to read data from the disk device is received from the host device, it is determined whether or not the data is stored in the individual cache memory provided by the host device. The data stored in the individual cache memory is transmitted to the requesting host device, and when it is determined that the data is not stored, the data is read from the disk device and transmitted to the requesting host device. There is,
A disk array device characterized by the above. The disk-side adapter unit writes the data to the shared cache memory and the individual cache memory provided by itself when data is read from the disk device;
When the host-side adapter unit receives a request to read data from the disk device, the host-side adapter unit determines whether or not the data is stored in the individual cache memory provided by itself, and determines that the data is not stored. The request is transferred to the disk side adapter unit,
When the disk-side adapter unit further receives a request from the host-side adapter unit to read data from the disk device, the disk-side adapter unit determines whether the data is stored in the individual cache memory included in the disk-side adapter unit. When it is determined that the data is stored, the data stored in the individual cache memory is transmitted to the requesting host device. When it is determined that the data is not stored, the data is read from the disk device. To be sent to the requesting host device,
The disk array device according to claim 1. The disk array device comprises the plurality of disk devices so as to have redundancy,
The host-side adapter unit is
When data to be written to the disk device is received from the host device, redundant data is created based on the data, and the data and the redundant data are transferred to the individual cache memory and the shared cache memory included in the self device. Write, request the disk side adapter unit to write the data to the disk device, write to any disk device,
When a request for reading data from the disk device is received from the host device, the individual cache memory provided by itself, the individual cache memory provided by the disk-side adapter unit, the shared cache memory, and the disk device, Generating data to be transmitted to the host device based on the data read from one of the data, and transmitting the data to the requesting host device;
The disk array device according to claim 1, wherein: The host side adapter unit and the disk side adapter unit are multiplexed,
Each host side adapter unit is connected to at least one disk side adapter unit,
Each disk side adapter part is connected to at least one host side adapter part,
4. The disk array device according to claim 1, 2, or 3.

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