JP2005210567A - Bus control method and bus control apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a bus control method and bus control apparatus, with which data transfer efficiency can be further improved, with regard to the bus control method, and to provide bus control apparatus for controlling a plurality of bus masters to use a bus, based on a timetable composed of a plurality of time slots. <P>SOLUTION: Priorities are given to a plurality of bus masters, and a plurality of time slots are assigned to the bus masters according to the priorities. Furthermore, if a bus master to which a time slot is assigned, does not request the use of a bus, a bus master, other than the bus master and having the highest priority, is made to use the bus, and the priority of the bus master which did not request the use of the bus, is improved. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a bus control method and a bus control device for sharing a bus connected to a plurality of bus masters in a time-sharing manner.

Conventionally, in a bus in which a plurality of bus masters are connected, when each bus master performs data transfer while time-sharing the bus, the bus master is connected to each bus master at predetermined intervals based on the time slot of the timer module provided in the bus arbitration circuit A bus control method is known in which use permission is switched and data transfer of a permitted bus master is executed (see, for example, Patent Document 1).
Special table 2001-516100 gazette

  However, when the bus masters that are permitted to use the bus based on time slots are sequentially switched every predetermined time, data transfer with different importance and priority is executed uniformly, which is important. Data may be divided and transferred, or low-priority data transfer may be executed in the middle of high-priority data transfer, which may reduce the efficiency of data transfer.

  Therefore, in the bus control method of the present invention, in the bus control method for controlling the use of buses by a plurality of bus masters with priorities based on a time table composed of a plurality of time slots, a plurality of time slots are assigned priority levels. The number of bus masters is assigned according to the number.

Furthermore, the following points are also characteristic. That is,
(1) When the bus master to which the time slot is assigned does not request the use of the bus, the bus master other than the bus master and having the highest priority uses the bus and does not request the use of the bus. Raise the priority of the bus master.
(2) When a bus master whose priority has been raised subsequently uses the bus, the priority of the bus master is lowered.
(3) Update the time table based on the bus usage history by the bus master.

  Further, in the bus control device of the present invention, in the bus control device having a bus arbitration circuit that controls the use of the bus by the plurality of bus masters with priorities based on a time table composed of a plurality of time slots, The bus arbitration circuit is configured to allocate the slots to the bus masters in the number corresponding to the priority order.

  According to the first aspect of the present invention, in the bus control method for controlling the use of a bus by a plurality of bus masters with priorities based on a time table composed of a plurality of time slots, the plurality of time slots are assigned priority levels. By assigning the number of bus masters according to the number of bus masters, it is possible to improve the data transfer efficiency by improving the bus usage time by the bus master with higher priority. In some cases, time slots are continuously assigned to one bus master. As a result, a variable-length time slot can be obtained, so that the efficiency of data transfer can be further improved.

  According to the second aspect of the present invention, when the bus master to which the time slot is allocated does not request the use of the bus, the bus master other than the bus master and using the bus master having the highest priority uses the bus. The efficiency of data transfer can be improved by improving the bus use efficiency. In addition, by raising the priority of the bus master that has not requested the use of the bus, it is possible to easily obtain the next opportunity to use the bus.

  In particular, bus masters that may not require bus use even though bus use is assigned in time slots are less frequently assigned bus use due to their relatively low priority. Therefore, in such a low-priority bus master, there is a possibility that the bus cannot be used for a long time. However, for a bus master that does not require the use of the bus, the bus master can be relatively quickly increased by increasing its priority. Since the opportunity of using the bus can be given, the possibility that data transfer will not be performed for a long time can be solved.

  According to the third aspect of the present invention, when a bus master whose priority is raised subsequently uses the bus, the bus master having a lower priority is given a higher priority by lowering the priority of the bus master. It is possible to improve the efficiency of data transfer by suppressing the occurrence of a problem caused by leaving, that is, the problem of reducing the bus use opportunity by the bus master whose priority is lowered as the priority is changed.

  According to the invention described in claim 4, by updating the time table based on the bus use history by the bus master, it is possible to automatically generate a time table capable of performing data transfer more efficiently. In particular, since a time table corresponding to the occurrence of substantial processing of each bus master can be generated, the efficiency of data transfer can be further improved.

  According to the fifth aspect of the present invention, in the bus control device having the bus arbitration circuit that controls the use of the buses by the plurality of prioritized bus masters based on the time table including a plurality of time slots, Since the bus arbitration circuit is configured to allocate the slots to the bus masters in the number corresponding to the priority order, the bus use time by the bus master having the high priority order is improved to transfer the data as in the first aspect of the invention. In some cases, by assigning time slots consecutively to one bus master, variable time slots can be obtained, so that further improvement in data transfer efficiency can be achieved.

  A bus control method and a bus control device according to the present invention are a bus control method and a bus control device for controlling the use of one bus by a plurality of bus masters based on a time table composed of a plurality of time slots. Each is prioritized and is assigned to a plurality of time slots by a number corresponding to this priority.

  That is, a bus master with a higher priority increases the number of appearances of the time slot assigned to the bus master, while a bus master with a lower priority reduces the number of appearances of the time slot assigned to the bus master in the time table. Thus, the efficiency of data transfer is improved by increasing the bus use opportunities by the bus master having a high priority.

  In particular, if the number of time slots to which high priority bus masters are assigned in the time table is increased, variable time slots can be created by assigning the same bus master to consecutive time slots. When performing data transfer that is not desired to be performed, the data transfer can be performed without being divided, and the efficiency of data transfer can be further improved.

  When the bus master to which the time slot is assigned does not request the use of the bus, the bus master other than the bus master and having the highest priority is made to use the bus.

  Therefore, it is possible to suppress the occurrence of a situation where the bus is not used, and it is possible to improve the bus usage efficiency and improve the data transfer efficiency.

  In addition, when the bus master to which the time slot is assigned does not request the use of the bus, the priority order of the bus master is increased.

  Therefore, it is possible to easily obtain a bus use opportunity for a bus master that has caused another bus master to use the bus when there is no request for data transfer when the bus can be used.

  In particular, when the bus can be used based on the time table in this way, there is no request for data transfer, so the priority is relatively low, so the time until the next time slot is assigned to that bus master is compared. Therefore, by increasing the priority of the bus master that did not require the use of the bus in this way, it is possible to give the bus master an opportunity to use the bus relatively quickly. The possibility of not being implemented can be eliminated.

  Further, when the bus master whose priority is thus increased uses the bus thereafter, the priority of the bus master is decreased. That is, a bus master whose priority is relatively lowered by raising the priority of the bus master is basically higher in priority than a bus master whose priority is raised. After the data transfer is executed, the bus can be used frequently by increasing the priority of the bus master whose priority is lowered, and the efficiency of data transfer can be improved.

  In this way, bus use is not performed uniformly based on the timetable, but bus deadlocks are prevented by permitting use based on priority for requests from each bus master. And the required data transfer can be completed within the required time.

  Further, when the history of the bus master that is actually permitted to use the bus in each time slot is stored in an appropriate storage means, and the time table is updated sequentially by the time table update means based on the stored use history information In addition, a timetable capable of more efficiently performing data transfer can be automatically generated.

  Hereinafter, an embodiment of a bus control device will be described with reference to the drawings. FIG. 1 is a block diagram of the bus control device of this embodiment. In this embodiment, there are four bus masters: a first bus master MA, a second bus master MB, a third bus master MC, and a fourth bus master MD. Assume that the bus B is used by being connected to the bus B. The number of bus masters is not limited to four, and may be more or less.

  In this embodiment, it is assumed that a plurality of slaves S1, S2, S3, S4, and S5 are connected to the bus B, and data transfer is performed between different slaves based on instructions from each bus master.

  Each bus master is connected to the bus arbitration circuit A, and each bus master outputs a use request signal R for the bus B to the bus arbitration circuit A, and the bus arbitration circuit A selectively uses any one bus master. The permission signal G is output.

  The bus arbitration circuit A is provided with a main control unit A-10, a timer module unit A-20, and a control module unit A-30, and the main control unit A-10 has transmitted from each bus master. The use request signal R is received, the time table provided in the timer module unit A-20 is referred to, and the use of the bus B is permitted with reference to the priority table provided in the control module unit A-30. A bus master is selected, and a use permission signal G is output to the bus master.

  In the present embodiment, the timer module unit A-20 is provided with a free-run counter A-21 and a programmable compare match register group A-22 to form a time table.

  The control module unit A-30 is provided with storage means such as a priority information memory A-31 storing a priority table and a bus right acquisition history storage memory A-32.

  The bus arbitration circuit A determines the priority order of each bus master by inputting a command from a program stored in a ROM (Read Only Memory) (not shown) or the like, or an instruction from other software. A priority table composed of priority information is generated and stored in the priority information memory A-31.

  Hereinafter, the control by the bus arbitration circuit A will be described based on the flowchart of FIG. In the present embodiment, for convenience of explanation, it is assumed that the first bus master M-A, the second bus master M-B, the third bus master M-C, and the fourth bus master M-D have higher priorities.

  At the start of processing, the bus arbitration circuit A generates a priority table that specifies the priority of each bus master based on the above-described software and the like, and stores it in the priority information memory A-31 (step S1). T1).

  Next, the bus arbitration circuit A assigns a plurality of time slots to the bus master in the number corresponding to the priority order with respect to the time table including the required number of time slots based on the set priority order table, A table is generated (step T2).

  That is, this time table assigns bus masters that are permitted to use the bus with the highest priority. In particular, as shown in the time table of FIG. 3, a bus master having a higher priority has more time slots. The bus master with a low priority is assigned with a small number of time slots.

  Accordingly, it is possible to increase the use opportunity of the bus B by the bus master having a high priority, and it is possible to improve the efficiency of data transfer.

  Here, the number of time slots in the time table is N. In FIG. 3, “<A>” indicates that the first bus master MA is the highest priority bus master in the time slot, and “<B>” indicates that the second bus master MB is the highest priority bus master in the time slot. “<C>” indicates that the third bus master MC is the highest priority bus master in the time slot, and “<D>” indicates that the fourth bus master MD is the highest in the time slot. Indicates that the bus is a priority bus master.

  In FIG. 3, below the time table, bus masters are arranged in descending order of priority in each time slot. “MA” is the first bus master MA, “MB” is the second bus master MB, and “MC”. Indicates the third bus master MC, and “MD” indicates the fourth bus master MD. In particular, “(MA)”, “(MB)”, “(MC)”, and “(MD)” are used by the first bus master MA, the second bus master MB, the third bus master MC, and the fourth bus master MD, respectively. “MC” and “MD” indicate that the third bus master MC and the fourth bus master MD do not output the use request signal R, respectively. In the present embodiment, for convenience of explanation, the first bus master MA and the second bus master MB always output the use request signal R, and the third bus master MC and the fourth bus master MD are used when the bus B needs to be used. The request signal R is output.

  First, the bus arbitration circuit A sets the value of the counter that counts the time slot to “1” (step T3), confirms the highest priority bus master assigned to the first time slot (step T4), and the highest priority bus master. To check whether the use request signal R for the bus B is output from the terminal (step T5).

  In FIG. 3, when the first bus master MA is the highest priority bus master in the first time slot and the bus B use request signal R is output from the first bus master MA, the bus arbitration circuit A is the first bus master. The use permission signal G is output to the MA (step T6), and the first bus master MA which is the highest priority bus master is caused to execute data transfer. In addition, the bus master usage history using the bus B is sequentially stored in the bus right acquisition history storage memory A-32 (step T7).

  Next, the bus arbitration circuit A determines whether or not the time slot has reached the final end of the time table (step T8), and if the time slot has not reached the final end of the time table, a counter that counts the time slot Is incremented (step T9), the highest priority bus master assigned to the next time slot is confirmed (step T4), and it is sequentially determined whether or not the use request signal R is output to the highest priority bus master. Go.

  On the other hand, if the highest priority bus master does not output the use request signal R for the bus B in step T5, the bus arbitration circuit A selects a bus master that is a bus master other than the highest priority bus master and has the next highest priority. Confirmation is made and whether or not the bus B use request signal R is output from the bus master (step T10).

  If the bus master outputs the use request signal R for the bus B, the bus arbitration circuit A outputs the use permission signal G to the bus master (step T11), and uses the bus B for the bus master. The bus master use history using the bus B is sequentially stored in the bus right acquisition history storage memory A-32 (step T12).

  As described above, when the highest priority bus master does not use the bus B, by causing the other bus master to use the bus B, it is possible to suppress the occurrence of the situation in which the bus B is not used. Can improve the efficiency of data transfer.

  Further, the bus arbitration circuit A changes the priority table by performing a process of raising the priority of the bus master that has been regarded as the highest priority bus master (step T13).

  More specifically, referring to FIG. 3, in the eighth time slot, the fourth bus master MD sends a use request signal R to the bus arbitration circuit A even though the fourth bus master MD is the highest priority bus master. Therefore, the bus arbitration circuit A outputs the use permission signal G to the first bus master MA that is outputting the use request signal R in the eighth time slot, and uses the bus B. I am trying to use it.

  Therefore, it is the first bus master M-A that substantially uses the bus B in the eighth time slot. The bus right acquisition history storage memory A-32 stores that the first bus master MA used the bus B in the eighth time slot.

  Further, the bus arbitration circuit A raises the priority of the fourth bus master MD when the fourth bus master MD can preferentially use the bus B but does not use the bus B. . In this embodiment, the priority of the fourth bus master MD is increased by one, and instead the priority of the third bus master MC is decreased by one, and the information is stored in the priority information memory A-31. ing. In FIG. 3, the fourth bus master M-D whose priority has been raised is displayed as “m-d”. In the present embodiment, the priority is incremented by one, but the highest priority may be set, or the priority may be incremented by two.

  In this way, the priority of the bus master whose right to use the bus B has been transferred to another bus master because the use request signal R is not output even though the opportunity to use the bus B is given. By raising the priority, the priority of the bus master can be made relatively high, and the possibility of being given the opportunity to use the bus B can be improved.

  In the case of FIG. 3, after the priority order of the fourth bus master MD is increased, if the first bus master MA and the second bus master MB do not use the bus B, the fourth bus master MD preferentially uses the bus B. Can be used.

  Therefore, the bus master that gives the right to use the bus B to another bus master by not outputting the use request signal R even though the opportunity to use the bus B is usually given priority. Due to the low order, the number of time slots allocated to the bus master is also small, and there is a possibility that the bus B may be in a standby state for a long time when the use of the bus B becomes necessary. When the right is handed over to another bus master, the priority of the bus master is raised, so that the time for waiting to use the bus B can be shortened.

  In this way, a bus master whose priority has been raised is such that when the bus master uses the bus B, the priority is lowered.

  More specifically, referring to FIG. 3, first, the fourth bus master MD starts outputting the use request signal R in the tenth time slot, and the fourth bus master MD becomes the highest priority bus master in the thirteenth time slot. As a result, the fourth bus master MD can use the bus B.

  When the fourth bus master MD uses the bus B in this way, the bus arbitration circuit A lowers the priority of the fourth bus master MD by one, and instead increases the priority of the third bus master MC by one to restore the original priority. Return to the ranking.

  In the case of lowering the priority of the bus master that has been raised once, for example, raising the priority may be raised in two steps, and the lowering may be carried out in two steps one by one. Also, a method of lowering may be used.

  In this way, for a bus master whose priority has been raised, by lowering the priority after using bus B by that bus master, by raising the priority of the bus master that has been lowered as the priority is raised. Basically, it is possible to increase the use opportunity of the bus B by a bus master having a high priority, and to improve the efficiency of data transfer.

  As described above, when the bus B is sequentially used by a predetermined bus master based on each time slot and the processing by the time slot at the end of the time table is completed (step T8), the bus arbitration circuit A receives priority information The time table is updated based on the memory A-31 and the bus right acquisition history storage memory A-32 (step T14).

  If the process is continued after the time table is updated, the process returns to step T3 to continue the process based on the updated time table (step T15).

  In this way, by updating the time table based on the priority order information memory A-31 and the bus right acquisition history storage memory A-32, a time table that can perform data transfer more efficiently is automatically generated. can do.

  FIG. 3 shows an example of updating based on the bus right acquisition history storage memory A-32 as a simple example of updating the time table. In the eighth time slot, the first bus master MA is designated as the highest priority bus master. In the 13th time slot, the fourth bus master MD is updated as the highest priority bus master, and in the 17th time slot, the first bus master MA is updated as the highest priority bus master.

It is a schematic explanatory drawing of the bus control apparatus concerning this invention. It is a flowchart explaining the bus control method concerning this invention. It is explanatory drawing of a priority change.

Explanation of symbols

A bus arbitration circuit
A-10 Main control unit
A-20 Timer module
A-30 Control module
A-21 Free run counter
A-22 Compare match registers
A-31 Priority information memory
A-32 Bus acquisition history storage memory B bus
MA 1st bus master
MB 2nd bus master
MC 3rd bus master
MD 4th bus master
S1 slave
S2 slave
S3 slave
S4 slave
S5 Slave R Use request signal G Use enable signal

Claims (5)

In a bus control method for controlling the use of a bus by a plurality of prioritized bus masters based on a time table composed of a plurality of time slots,
A bus control method characterized by allocating the plurality of time slots to the bus master in a number corresponding to the priority.   If the bus master to which the time slot is assigned does not request the use of the bus, the bus master other than the bus master, which has the highest priority, uses the bus and does not request the use of the bus. 2. The bus control method according to claim 1, wherein the priority order of the bus masters is increased.   3. The bus control method according to claim 2, wherein, when the bus master having raised the priority order uses the bus thereafter, the priority order of the bus master is lowered.   4. The bus control method according to claim 2, wherein the time table is updated based on a use history of the bus by the bus master. In a bus control device having a bus arbitration circuit that controls the use of a bus by a plurality of bus masters with priorities based on a time table composed of a plurality of time slots.
The bus control device, wherein the bus arbitration circuit is configured to allocate the plurality of time slots to the bus master in a number corresponding to the priority.

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