JP2005209310A - Deinterleave method and circuit, and information reproducing device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an error correction method and circuit which can develop the lost pointers quickly and in a small circuit scale, and also provide an information reproducing device. <P>SOLUTION: It has a 1st storing step of storing the reproduce data in the storing bank of a 1st memory in the predetermined order, a 1st read step of reading the data in a order different from the storing order, and a 2nd storing step storing the read data in a 2nd memory. If the frames are detected to be out of steps when reproducing the data, the storing position is corrected in inside the storing bank for the following reproduced data. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method for deinterleaving reproduction data from an information recording medium having a frame structure such as an optical disc, a deinterleaving circuit, and an information reproducing apparatus.

  Conventionally, in an optical disc such as a DVD, an error correction code such as a Reed-Solomon code is used to correct an error caused by a medium defect or dust or scratches attached to the disc surface.

In the error correction code, the correction number t when the minimum distance of the code is d is generally:
d ≧ 2 × t + 1
Thus, up to t errors per codeword can be corrected.

  In general, an error that occurs in an optical disk is often a burst error, that is, data is continuously erroneous. In order to cope with such burst errors, it is common to perform so-called interleaving, in which data is recorded in a direction different from the encoding direction of the error correction code described above. For example, data arranged in a matrix is subjected to error correction coding in the column direction, and this is recorded in the row direction for interleaving, and burst errors are distributed to each code word, thereby reducing the number of errors per code word. It becomes possible to reduce.

  The interleaved encoded data is further divided into a plurality of blocks having a predetermined length, and is recorded on a recording medium as a frame in which a synchronization code is added to the head of each block.

By adopting such a frame structure, even if a bit slip that causes synchronization between the clock generated by the PLL and the reproduction data due to a long burst error or the like occurs, by performing resynchronization from the detection result of the synchronization code, It is possible to correct the synchronization shift (see, for example, Patent Document 1).
JP 2002-521789 (page 17 to page 18, FIG. 5)

  However, when reproducing the above-described interleaved recording data, for example, when the reproduction data is stored after being deinterleaved in a large capacity memory such as a DRAM, there is a problem that the access performance to the DRAM is lowered. DRAM has the property that continuous access within a page can be performed at a high speed but random access is performed at a low speed. For example, when the data direction of the correction code and the page direction of the DRAM are matched, the data direction during reproduction is the DRAM. Unlike the page direction, since high-speed page access is not possible, there is a problem that the access performance to the DRAM is lowered, and there is a problem in performance improvement such as higher speed.

  To deal with this problem, use a SRAM that can be randomly accessed at high speed for deinterleaving, and temporarily store all or part of the playback data in the SRAM so that it matches the page direction of the DRAM. By reading the data, it is possible to reduce a decrease in access performance to the DRAM. In this case, there is a problem that the circuit scale is increased due to the addition of the SRAM in contrast to storing the reproduction data directly in the DRAM.

  Further, a correction function when synchronization is lost is indispensable. In the configuration using the above-described SRAM, when a synchronization error is detected, a new SRAM area is required for storing data after synchronization correction. There is a problem that the circuit scale further increases.

  In view of the above problems, the present invention can reduce a decrease in access performance to a DRAM while minimizing an increase in circuit scale by using a minimum SRAM, and further detecting a synchronization error. An object of the present invention is to provide a deinterleaving method, a deinterleaving circuit, and an information reproducing apparatus that can perform synchronization correction.

  In order to solve the above problem, in the deinterleaving method of the present invention, when the first and second memories are provided and the reproduction data of a predetermined number of frames is one page, the first memory has at least two pages. A first storage step in which the reproduction data is divided into pages and stored in the bank of the first memory in a predetermined order; and the storage data of the bank Read out in a different order from the predetermined order, a second storage step for storing the read data in the second memory, and a bank management step for alternately switching between the storage bank and the read bank of the reproduction data In the case of detecting the frame synchronization deviation during the data reproduction, in the same bank as the storage bank at the time of detection, Those provided in characterized in that to correct the storage position of the reproduced data.

  The deinterleave circuit of the present invention has first and second memories, and when the reproduction data of a predetermined number of frames is one page, the first memory can store at least two pages of reproduction data 2. A first storage unit configured to divide the reproduction data into the pages and store the data in the bank of the first memory in a predetermined order; and the storage data of the bank is different from the predetermined order. First reading means for reading in order; second storage means for storing the read data in the second memory; and bank management means for alternately switching between the storage bank and the read bank of the reproduction data, When a frame synchronization error is detected during reproduction, the storage position of subsequent reproduction data is corrected in the same bank as the storage bank at the time of detection. It is those provided in the.

  In addition, the information reproducing apparatus of the present invention is characterized by comprising the above-described deinterleave circuit.

  With this configuration, it is possible to reduce the decrease in the access performance to the second memory while minimizing the increase in circuit scale, and further, when synchronization loss is detected, it is possible to perform synchronization correction can do.

  According to the deinterleaving method, the deinterleaving circuit, and the information reproducing apparatus of the present invention, it is possible to reduce the decrease in the access performance to the memory while minimizing the increase in circuit scale, and further, when the synchronization shift is detected By enabling synchronization correction, it is possible to reproduce data with high performance and high reliability with a small circuit scale.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1)
FIG. 1 is a configuration diagram of encoded data of a deinterleaving method according to Embodiment 1 of the present invention, and Embodiment 1 is an example of a deinterleaving method of reproduction data from an optical disc.

  In FIG. 1, 101 is data, and 102 is parity. For each column, 152 + 152 = 304 error correction codes encoded by adding a 32-byte parity in the column direction are collected. Structured data is configured. Data recording / reproduction is performed in units of the encoded data. The encoded data includes 216 × (152 × 2) = 65664 bytes of data 101, and approximately 64 Kbytes of user data can be stored in the data 101.

  Each error correction code is encoded with a Reed-Solomon code of a well-known Galois extension field GF (256), and one symbol that is a minimum unit constituting the code is 1 byte. Due to the parity 102 of 32 bytes, the minimum distance of each code is 33.

In the error correction code, when the minimum distance of the code is d, the correction number t is generally
d ≧ 2 × t + 1
The relationship is established. In this case, since the minimum distance d = 33, an error up to 16 bytes in the code length = 216 + 32 = 248 bytes can be corrected for each column.

  The above encoded data is recorded in the row direction when recorded on an optical disk or the like. In FIG. 1, recording is performed from the top row to the bottom row, and from left to right in each row. Here, interleaving is performed by recording in the row direction what is encoded in the column direction. By performing interleaving, burst errors occurring in the recording direction can be distributed to a plurality of codes, and the reliability of data reproduction can be improved. For example, when a 100-byte burst error occurs, when interleaving is performed in the row direction, each codeword has an error of 1 byte at most, and all can be corrected. On the other hand, if recording is performed in the codeword direction without interleaving, an error of 100 bytes occurs in one codeword, and correction is impossible up to a maximum of 16 bytes.

  Also, the encoded data is divided into 152-byte frames at the time of recording. A synchronization code 103 for identifying the head of each frame is added to the head of each frame. The encoded data shown in FIG. 1 is divided into two frames for each row, and is divided into 248 × 2 = 496 frames in total. By adopting such a frame structure, even if the clock and the playback data are once out of sync due to a scratch on the medium, for example, during data playback, resynchronization is performed using the detection timing of the synchronization code. , Can return to the correct playback state.

  Here, the out-of-synchronization state refers to, for example, the frame position of reproduction data assumed internally by the reproduction apparatus or the reproduction circuit, that is, the number of bytes and the number of clocks from the beginning of the encoded data. This means that the frame number obtained by this is different from the frame number of the reproduced data that is actually reproduced, and as described above, it occurs due to the frequency shift of the PLL clock. Further, the correction means that the once shifted state is correctly matched.

  The above interleaving and frame structure is a common technique for information recording media such as optical disks.

  FIG. 2 is a configuration diagram of an optical disc for explaining how the encoded data divided into a plurality of frames is recorded on the optical disc.

  In FIG. 2, 201 is an optical disk, 202 is encoded data divided into a plurality of frames, and stores approximately 64 Kbytes of user data.

  The encoded data 202 is divided into a plurality of frames, and each frame includes a synchronization code 203 indicating the head of the frame and a symbol 204 constituting the encoded data.

  A method for deinterleaving the encoded data recorded by interleaving on the optical disc as described above will be described below.

  FIG. 3 is a configuration diagram showing an outline of the deinterleaving method in the present embodiment.

  In FIG. 3, 301 is reproduction data reproduced from the optical disc 201, 302 is a first memory composed of a random accessible memory such as SRAM, 303 is a buffer memory, and a large capacity memory such as a DRAM. It is the comprised 2nd memory.

  Frame synchronization is achieved by detecting a synchronization code at the head of the frame from a reproduction signal reproduced from the optical disc 201 by a demodulation circuit (not shown) or the like. Next, the reproduction data 301 obtained by digitally demodulating the encoded data from which the synchronization code is removed is composed of a total of 496 frames, and is divided into 8 frames as one page. The division here is virtual, and simply means that subsequent processing such as data transfer is performed in units of pages.

  The reproduction data 301 is transferred to the first memory 302 page by page. The first memory 302 includes two banks that can store two pages of reproduction data. The first memory 302 includes a storage bank used for storing reproduction data and a read bank that creates the storage data in the second memory 303. By alternately switching the storage bank and the read bank in units of pages, it is possible to continuously deinterleave the reproduction data 301 reproduced from the optical disc 201.

  The reproduction data 301 is stored in the first storage step 304, and the storage data is read from the reading bank in the first reading step 305. Further, switching between the read bank and the write bank is managed by a bank management step 307.

  Since one page is composed of 8 frames, the first storage step 304 stores 8 frames, that is, 4 rows, in the write bank in the row direction in FIG. In other words, deinterleaving is performed by reading 4 bytes at a time in the column direction by the first reading step 305.

  The read data is stored in the second memory 303 by the second storage step 306. In the second memory 303, the read 4 bytes are stored in the order of addresses where high-speed page access is possible. By doing so, deinterleaving can be performed without degrading the bus access performance of the second memory 303. The second memory 303 stores all reproduction data. The reproduction data of page 0 to page 61 is deinterleaved and stored in each area of DILV 0 to DILV 61 of the second memory 303.

  The stored reproduction data is subjected to error correction processing by an error correction circuit (not shown) or the like to correct errors caused by a scratch on the medium.

  In the deinterleaving method according to the present embodiment configured as described above, when data is reproduced, when a synchronization error of a frame is detected from the detection result of the synchronization code at the head of the frame by a demodulation circuit (not shown), the first In the storing step 304, the storage position of the subsequent reproduction data is corrected in the same bank as the storage bank at the time of detection.

  An example of the correction process when the frame synchronization is shifted will be described in detail with reference to FIGS.

  FIG. 4 shows an example in which a frame synchronization shift is detected during reproduction and correction is advanced by 5 frames. In FIG. 4, 401 is reproduction data, 402 is a first memory, 403 is a second memory, and the numbers in each indicate frame numbers.

  In this example, correction is made to the frame 31 during the reproduction of the frame 26 (406). The reproduction data from frame 27 to frame 30 with () is skipped and not transferred. Here, it is assumed that the frame position of the reproduction data assumed internally by the reproduction apparatus or the reproduction circuit is the frame 26, and that the frame number of the reproduction data actually reproduced is the frame 30. Since it has been detected at this time, it means that playback is performed after correcting the assumed frame number to frame 30.

  At this time, in the writing to the writing bank 404 of the first memory 402, the storage position is corrected from the frame 26 to the frame 31 corresponding to the correction of the reproduction data (407). Correction at the write bank 404 is performed by the first storage step 304. By correcting the storage position to the occurrence position in the writing bank 404, the stored data and the data reproduced after the correction can be normally deinterleaved.

  The data stored in the write bank 404 is transferred to DILV3 of the second memory 403 after completion of storage (408). In this case, the reproduction data from frame 27 to frame 30 is lost, but it becomes a local error by performing correction, and can be reproduced correctly by performing error correction processing.

  FIG. 5 shows an example in which a frame synchronization shift is detected during reproduction and correction is made to advance by 7 frames, and the correction exceeds the page boundary. In FIG. 5, reference numeral 501 denotes reproduction data, 502 denotes a first memory, and 503 denotes a second memory. The numbers in each indicate frame numbers.

  In this example, correction is made to the frame 33 during the reproduction of the frame 26 (506). The reproduction data of frames 27 to 32 with () is not transferred. Further, the correction from the frame 26 to the frame 33 exceeds the page boundary.

  Even in such a correction exceeding the page boundary, in the present embodiment, the correction is executed only by correcting the storage position in the same bank as the reproduction data write bank before the correction. This eliminates the need to add a memory area for storing a new page after correction, and can be realized with a small circuit scale.

  In writing to the write bank 504 of the first memory 502, the storage position of the write address is corrected from the frame 26 to the frame 33 corresponding to the correction of the reproduction data (507). Here, since the frame 33 is originally page 4, it is corrected to a position corresponding to the frame number within the same bank. The reproduction data of the frames 25 and 26 stored before the correction is overwritten after the correction. Correction in the write bank 504 is performed by the first storage step 304. By correcting the storage position to the occurrence position in the write bank 504, the stored data and the data reproduced after the correction can be normally deinterleaved.

  Since the stored data in the write bank 504 is originally reproduction data of page 4, it is corrected and transferred to DILV4 of the second memory 503 (508). Here, the reproduction data of page 24, which is the reproduction data of page 3, is lost, but it becomes a local error by performing correction, and can be correctly reproduced by performing error correction processing. In addition, since the reproduction data before the correction of such a frame is originally out of synchronization, even if it is not lost, there is a high possibility that the reproduction data is erroneous, and the reproduction data of page 3 in the present embodiment. It is clear that the lack of has no substantial effect.

  FIG. 6 shows an example in which a frame misalignment is detected during reproduction and correction is advanced by 7 frames. In FIG. 6, reference numeral 601 denotes reproduction data, 602 denotes a first memory, and 603 denotes a second memory. The numbers in each indicate frame numbers.

  Here, it is an example in the case of correcting to the frame 31 during the reproduction of the frame 24 (606). The reproduction data of frames 25 to 30 with () is not actually transferred.

  In writing to the write bank 604 of the first memory 602, the storage position of the write address is corrected from the frame 24 to the frame 31 corresponding to the correction of the reproduction data (607). Correction in the write bank 604 is performed by the first storage step 304. By correcting the storage position to the occurrence position in the write bank 504, the stored data and the data reproduced after the correction can be normally deinterleaved.

  Here, in the example of this correction, the reproduction data is stored in the write bank 604 only in two frames, frame 24 and frame 31. Originally, storage in the write bank and read from the read bank can avoid the overflow of the bank by making the read sufficiently fast. However, in the case of this correction example, the write bank 604 is used. It is conceivable that the storage into the memory ends faster than the reading from the reading bank 605.

  At this time, in the deinterleaving method of the present embodiment, reading from the reading bank 605 is interrupted (608). Then, the write bank and the read bank are changed, the bank on the upper side of the first memory 602 is set as the write bank, and the reproduction data of the next page 4 is stored. Further, the lower bank of the first memory 602 is set as a read bank, and the storage data of page 3 is sent to DILV 3 (609). These interruption and bank switching processing are executed by the bank management step 307.

  In this example, the reproduction data of page 2, which is reproduction data of frame 16 to frame 23, is partially lost due to the interruption. However, when correction is performed, a local error occurs. Can play. In addition, since the reproduction data before the correction of such a frame is originally out of synchronization, even if it is not lost, there is a high possibility that the reproduction data is erroneous, and the reproduction data of page 3 in the present embodiment. It is clear that the lack of has no substantial effect.

  FIG. 7 shows an example in which a frame synchronization shift is detected during reproduction and correction is performed to return three frames. In FIG. 7, reference numeral 701 denotes reproduction data, 702 denotes a first memory, and 703 denotes a second memory, and the numbers in each indicate frame numbers.

  In this example, correction is made to the frame 27 during the reproduction of the frame 30 (706). The reproduction data from frame 27 to frame 30 once transferred before correction is transferred again.

  At this time, the writing to the writing bank 704 of the first memory 702 corrects the storage position of the writing address from the frame 30 to the frame 27 corresponding to the correction of the reproduction data (707). Correction in the write bank 704 is performed by the first storage step 304. By correcting the storage position to the occurrence position in the write bank 704, the data reproduced after the correction can be normally deinterleaved. It should be noted that the reproduction data of frames 27 to 30 transferred before correction is corrected to correct reproduction data by overwriting.

  The data stored in the write bank 704 is transferred to DILV3 of the second memory 703 after the storage is completed (708).

  FIG. 8 is an example in which a frame synchronization shift is detected during reproduction and correction is performed to return five frames, and the correction exceeds the page boundary. In FIG. 8, reference numeral 801 denotes reproduction data, reference numeral 802 denotes a first memory, and reference numeral 803 denotes a second memory. The numbers in each indicate frame numbers.

  In this example, correction is made to the frame 23 during the reproduction of the frame 28 (806). The reproduction data of frames 23 to 28 once transferred before correction is transferred again. Further, the correction from the frame 28 to the frame 23 exceeds the page boundary.

  Even in such a correction exceeding the page boundary, in the present embodiment, the correction is executed only by correcting the storage position in the same bank as the reproduction data write bank before the correction. This eliminates the need to add a memory area for storing a new page after correction, and can be realized with a small circuit scale.

  In writing to the write bank 804 of the first memory 802, the storage position of the write address is corrected from the frame 28 to the frame 23 corresponding to the correction of the reproduction data (807).

  Here, since frame 23 is originally page 2, it is corrected to a position corresponding to the frame number in the same bank.

  Correction in the write bank 804 is performed by the first storage step 304. By correcting the storage position to the occurrence position in the write bank 804, the stored data and the data reproduced after the correction can be normally deinterleaved.

  Since the stored data in the write bank 804 is originally reproduction data of page 2, it is corrected and transferred to DILV2 of the second memory 803 (808). In this example, data is stored twice in DILV2, but finally the corrected data is stored.

  FIG. 9 shows an example in which a frame synchronization shift is detected during reproduction and correction is performed to return one frame. In FIG. 9, reference numeral 901 denotes reproduction data, reference numeral 902 denotes a first memory, reference numeral 903 denotes a second memory, and the numbers in each indicate frame numbers.

  In this example, correction is made to the frame 23 during the reproduction of the frame 24 (906).

  For writing to the write bank 904 of the first memory 902, the storage position of the write address is corrected from the frame 24 to the frame 23 corresponding to the correction of the reproduction data (907). Here, since frame 23 is originally page 2, it is corrected to a position corresponding to the frame number in the same bank. Correction in the write bank 904 is performed by the first storage step 304. By correcting the storage position to the occurrence position in the write bank 904, the stored data and the data reproduced after the correction can be normally deinterleaved.

  Here, in this correction example, the reproduction data is stored in the writing bank 904 only in two frames, frame 24 and frame 23. Originally, storage in the write bank and read from the read bank can avoid the overflow of the bank by making the read sufficiently fast. However, in the case of this correction example, the write bank 904 It is conceivable that the storage to the memory ends faster than the reading from the reading bank 905.

  At this time, in the deinterleaving method of the present embodiment, reading from the reading bank 905 is interrupted (908). Then, the write bank and the read bank are changed, the bank on the upper side of the first memory 902 is set as the write bank, and the reproduction data of the next page 3 is stored. Further, the lower bank of the first memory 902 is set as a read bank, and the storage data of page 2 is sent to DILV 2 (909). These interruption and bank switching processing are executed by the bank management step 307.

  Note that here, the reproduction data of frame 16 to frame 23, which is the reproduction data of page 2, is transferred twice, but the data of correct frame 23 after correction can be finally transferred. Further, the reproduction data from frame 16 to frame 22 transferred before correction is lost, but it can be limited to local errors by performing correction, and can be correctly reproduced by performing error correction processing. Further, since the reproduction data before the correction of such a frame was originally out of synchronization, even if it is not lost, there is a high possibility that the reproduction data is incorrect, and the reproduction data of page 2 in the present embodiment. It is clear that the lack of has no substantial effect.

  It is obvious that the correction by the first storage step 304 in the write bank 904 can be easily realized by using an address table in the bank indicating the storage address at the head of each frame corresponding to the frame number, for example.

  In addition, information on which frame is corrected at the time of correction can be easily realized by notifying a frame number after correction from a demodulation circuit (not shown). Further, detection of loss of synchronization can be easily performed by detecting the synchronization code at the head of the frame. For example, in a DVD or the like, the synchronization code has a different pattern for each frame, and the frame number can be derived from the pattern of the synchronization code of several consecutive frames. Obviously, it is easy to identify the correct frame number.

  Here, the corrected frame can be any frame, but it may be limited to some extent. For example, here, since the total number is 496 frames, if it is possible to perform the timing at every 31 frames, the correctable timing is possible at 16 locations. By limiting the corrected frames in this way, the configuration of the address table and the like can be further simplified. In addition, it is possible to configure only by notifying the correction to the front or the correction to the rear instead of notifying the correction destination frame number.

  As described above, in the deinterleaving method according to Embodiment 1 of the present invention, when a frame synchronization shift is detected during data reproduction, the subsequent reproduced data is stored in the same bank as the storage bank at the time of detection. By correcting the storage position, it is possible to reduce the decrease in the access performance to the second memory while minimizing the increase in circuit scale. Make it possible to do.

(Embodiment 2)
FIG. 10 is a configuration diagram of the deinterleave circuit in the second embodiment of the present invention. In the first embodiment, an example of the deinterleave circuit for the encoded data shown in FIGS. 1 and 2 is shown. 2 is an example of a circuit that embodies the first deinterleaving method.

  In FIG. 10, 1001 is reproduction data reproduced from the optical disc 201, 1002 is a first memory composed of a random accessible memory such as SRAM, and 1003 is used as a buffer memory, and is a large capacity memory such as DRAM. It is the comprised 2nd memory.

  The operation of the deinterleave circuit configured as described above will be described below.

  Frame synchronization is achieved by detecting a synchronization code at the head of a frame from a reproduction signal reproduced from the optical disc 201 by a demodulation circuit (not shown) or the like. Next, reproduction data 1001 digitally demodulated is composed of a total of 496 frames. 8 frames are divided into one page.

  The reproduction data 1001 is transferred to the first memory 1002 in page units via the bank management circuit 1007. The first memory 1002 includes two banks that can store two pages of reproduction data. The first memory 1002 includes a storage bank used for storing reproduction data and a read bank that creates the storage data in the second memory. By alternately switching the storage bank and the read bank in units of pages, it is possible to continuously deinterleave the reproduction data 1001 reproduced from the optical disc 201.

  The reproduction data 1001 is stored in the storage bank according to the write address generated by the first storage circuit 1004. Reading stored data from the read bank is performed according to the read address generated by the first read circuit 1005. The switching between the read bank and the write bank is managed by the bank management circuit 1007 and executed by switching the upper address of the first memory 1002.

  Since one page is composed of 8 frames, the first storage circuit 1004 stores each of 8 frames, that is, 4 rows in the write bank in the row direction in FIG. That is, deinterleaving is performed by reading out 4 bytes at a time in the column direction by the first reading circuit 1005.

  The read data is stored by generating an address of the second memory 1003 by the second storage circuit 1006. In the second memory 1003, the read 4 bytes are stored in the order of addresses where high-speed page access is possible. By doing so, deinterleaving can be performed without degrading the bus access performance of the second memory 1003. The second memory 1003 stores all reproduction data. The reproduction data of page 0 to page 61 is deinterleaved and stored in each area of DILV 0 to DILV 61 of the second memory 1003.

  The second memory 1003 is shared with an error correction circuit (not shown), and access to the second memory 1003 is performed by recording and reproducing data under the control of the DRAM control circuit 1008 via the memory bus 1010. .

  The stored reproduction data is subjected to error correction processing by an error correction circuit (not shown) or the like to correct errors caused by a scratch on the medium.

  In the deinterleaving circuit according to the present embodiment configured as described above, when data is reproduced, when a frame synchronization shift is detected from the detection result of the synchronization code at the head of the frame by a demodulation circuit (not shown) or the like, The storage circuit 1004 corrects the storage position of the subsequent reproduction data in the same bank as the storage bank at the time of detection.

  The details of the correction when the synchronization shift is detected are the same as those in the first embodiment of the present invention shown in FIGS.

  As described above, in the deinterleave circuit according to the second embodiment, when a frame synchronization shift is detected during data reproduction, the subsequent reproduction data storage position in the same bank as the storage bank at the time of detection is detected. By correcting the above, it is possible to reduce the decrease in the access performance to the second memory while minimizing the increase in the circuit scale, and to perform the synchronization correction when the synchronization shift is detected. to enable.

  Note that the first storage circuit 1004, the first read circuit 1005, and the second storage circuit 1006 can be easily configured with, for example, an address table or counter in the bank indicating the storage address at the head of each frame corresponding to the frame number. realizable. Further, the bank management circuit 1007 can be easily realized by a selector, a simple logic circuit, or the like.

(Embodiment 3)
FIG. 11 is a block diagram of an optical disk playback device according to the third embodiment, and is a block diagram of an optical disk playback device including the deinterleave circuit according to the second embodiment.

  In FIG. 11, reference numeral 1101 denotes an optical disk on which compressed image data is recorded, 1102 denotes an optical head composed of a semiconductor laser or an optical element, 1103 denotes a reproduction circuit that binarizes an analog reproduction signal and generates a digital reproduction signal, 1104 Is a demodulation circuit that digitally demodulates the binarized reproduction signal and detects the synchronization code at the head of the frame to perform frame synchronization or resynchronization when synchronization is lost. Reference numeral 1105 denotes a deinterleave / error correction circuit including the deinterleave circuit of the second embodiment, 1106 denotes a second memory, 1107 denotes an MPEG decoding circuit for expanding MPEG compressed data, 1108 denotes a DA conversion circuit, and 1109 denotes an entire reproducing apparatus. A control CPU that performs control.

  The operation of the optical disk reproducing apparatus configured as described above will be described below.

  The laser light emitted from the semiconductor laser of the optical head 1102 returns to the optical head 1102 as reflected light modulated by pits or dark and light dots formed on the recording surface of the optical disk 1101. The modulated reflected light is converted into an electric signal by the photoelectric element and input to the reproduction circuit 1103 as an analog reproduction signal 1110. The reproduction circuit 1103 performs conversion from analog to digital, and sends it to the demodulation circuit 1104 as a digital reproduction signal. The demodulating circuit 1104 performs demodulation processing after frame synchronization, and sends it to the deinterleave / error correction circuit 1105 as reproduced data 1111. The reproduction data 1111 is the same as the reproduction data 301 shown in FIG.

  The deinterleave / error correction circuit 1105 deinterleaves the reproduction data 1111 in the second memory 1106 and stores it as encoded data, and then performs error correction processing. Details of deinterleaving are the same as in the second embodiment, and are omitted here. The first memory 1002 of the second embodiment in FIG. 10 is included in the deinterleave / error correction circuit 1105, and the second memory 1003 is externally attached as the second memory 1106.

  The user data 1112 that has been subjected to error correction is MPEG-decoded by the MPEG decoding circuit 1107. The expanded reproduction data 1113 is converted into an analog signal by a DA conversion circuit 1108 and sent to a TV monitor or the like as an audio or image signal. Control of the entire optical disc playback apparatus is performed by the control CPU 1109. In this configuration diagram, control signals, servo circuits for focusing, tracking, etc. are omitted.

  In the optical disk reproducing apparatus according to the third embodiment configured as described above, the deinterleave circuit included in the deinterleave / error correction circuit 1105 detects the frame synchronization deviation at the time of data reproduction by the demodulation circuit 1104. In this case, by correcting the storage position of the subsequent reproduction data in the same bank as the storage bank at the time of detection, it is possible to reduce the decrease in the access performance to the second memory while minimizing the increase in circuit scale. In addition, when synchronization loss is detected, synchronization correction can be performed and data can be reproduced with high reliability.

  The deinterleaving method, deinterleaving circuit, and information reproducing apparatus of the present invention are useful as a reproducing apparatus or recording / reproducing apparatus for a disk medium such as an optical disk or a magnetic disk.

Configuration diagram of encoded data in Embodiment 1 of the present invention Configuration diagram of an optical disc in Embodiment 1 of the present invention The block diagram which shows the outline | summary of the deinterleaving method in Embodiment 1 of this invention The figure which shows the example of the synchronous correction process in Embodiment 1 of this invention The figure which shows the example of the synchronous correction process in Embodiment 1 of this invention The figure which shows the example of the synchronous correction process in Embodiment 1 of this invention The figure which shows the example of the synchronous correction process in Embodiment 1 of this invention The figure which shows the example of the synchronous correction process in Embodiment 1 of this invention The figure which shows the example of the synchronous correction process in Embodiment 1 of this invention Configuration diagram of a deinterleave circuit in Embodiment 2 of the present invention Configuration diagram of optical disc playback apparatus in Embodiment 3 of the present invention

Explanation of symbols

101 Data 102 Parity 103, 203 Sync code 201, 1101 Optical disc 202 Encoded data 204 Symbols 301, 401, 501, 601, 701, 801, 901, 1001 constituting encoded data Reproduced data 302, 402, 502, 602 702, 802, 902, 1002 First memory 303, 403, 503, 603, 703, 803, 903, 1003 Second memory 304 First storage step 305 First reading step 306 Second storage step 307 Bank management step 404, 504 , 604, 704, 804, 904 Write bank 405, 505, 605, 705, 805, 905 Read bank 1004 First storage circuit 1005 First read circuit 1006 Second storage circuit 1007 Bank Management circuit 1008 DRAM control circuit 1010 Memory bus 1102 Optical head 1103 Reproduction circuit 1104 Demodulation circuit 1105 Deinterleave / error correction circuit 1106 Second memory 1107 MPEG decoding circuit 1108 DA conversion circuit 1109 Control CPU
1110 Analog playback signal 1111 Playback data 1112 User data 1113 Playback data

Claims (7)

A method of deinterleaving reproduction data from a recording medium in which data is divided into a plurality of frames and having first and second memories, and when the reproduction data of a predetermined number of frames is one page, 1 memory has a two-bank configuration capable of storing at least two pages of reproduction data, a first storage step of dividing the reproduction data into the pages and storing the reproduction data in the bank of the first memory in a predetermined order; A first read step for reading stored data in the bank in an order different from the predetermined order; a second storage step for storing the read data in the second memory; and a storage bank and a read bank for the reproduction data. A bank management step for switching between the frames, and when reproducing the data, if the frame synchronization deviation is detected, the case at the time of detection is detected. Deinterleaving method characterized by within the bank and the same bank, to correct the storage position of the subsequent reproduction data. When the frame synchronization deviation exceeds the page boundary, the storage position of the subsequent reproduction data is corrected in the same bank as the storage bank at the time of detection, and the corrected page of the reproduction data stored after correction is corrected. 2. The deinterleaving method according to claim 1, wherein the storage position in the second memory is corrected in response to. As a result of detecting the frame synchronization error and correcting the storage position of the reproduction data in the first storage step, if the storage of the reproduction data in the storage bank is completed earlier than the reading from the reading bank, the bank 2. The deinterleaving method according to claim 1, wherein the management step interrupts reading from the read bank and switches between the storage bank and the read bank. A deinterleaving circuit for reproduction data from a recording medium in which data is divided into a plurality of frames and has first and second memories, and when the reproduction data of a predetermined number of frames is one page, the first The first memory has a two-bank configuration capable of storing at least two pages of reproduction data, and the reproduction data is divided into pages and stored in the bank of the first memory in a predetermined order. First reading means for reading stored data in the bank in an order different from the predetermined order; second storing means for storing the read data in the second memory; and a storage bank and a read bank for the reproduction data Bank management means for alternately switching between the frames, and when reproducing the data, when the frame synchronization deviation is detected, it is the same as the storage bank at the time of detection. In tank, de-interleave circuit and correcting the storage position of the subsequent reproduction data. When the frame synchronization deviation exceeds the page boundary, the storage position of the subsequent reproduction data is corrected in the same bank as the storage bank at the time of detection, and the corrected page of the reproduction data stored after correction is corrected. The deinterleaving circuit according to claim 4, wherein the storage position in the second memory is corrected in response to. As a result of detecting the frame synchronization shift and correcting the storage position of the reproduction data by the first storage means, if the storage of the reproduction data in the storage bank is completed earlier than the reading from the reading bank, the bank 5. The deinterleave circuit according to claim 4, wherein the management unit interrupts reading from the read bank and switches between the storage bank and the read bank. An information reproducing apparatus comprising the deinterleave circuit according to any one of claims 4 to 6.

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