JP2005209172A - Semiconductor integrated circuit, development support device and execution history restoration method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To optimize trace information output, in a semiconductor integrated circuit capable of executing a program. <P>SOLUTION: When a call instruction or an interrupt branch is executed by a CPU 100, a stack memory 300 pushes its return destination address, and pops the return destination address being pushed when a return instruction is executed. When an return instruction is executed by the CPU 100, a comparator 400 compares a branch destination address outputted from the CPU 100 with an address outputted from the stack memory 300. As a result of the comparison, the branch destination address is not outputted as trace information in the case of coincidence, and a shift register 700 receives the branch destination address 110 from the CPU 100 to output it as trace information in the case of inconsistency. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor integrated circuit, a development support apparatus, and an execution history restoration method, and in particular, based on a processor having a “trace information output function” for outputting trace information related to program execution, and trace information output from the processor. The present invention relates to a development support apparatus and method for restoring a program execution history by a processor.

  The “trace information output function” is a function for outputting the program execution state of the processor to a debugger operating on an external host computer. When the system detects any abnormal operation, the accumulated trace information is used so that the system developer can confirm the execution history going back from that point and identify the cause.

  However, in order to support development as described above, a pin for outputting trace information must be provided in the processor, and the number and operating frequency (bandwidth of trace information output) are limited. There is also a limit to the memory capacity for storing trace information. Therefore, in order to maximize the effect with a limited bandwidth and memory capacity, it is necessary to compress the trace information.

  As an example of a method for compressing trace information, conventionally, a so-called “branch trace” trace information acquisition method is known (see, for example, Patent Document 1 and Non-Patent Document 1). According to this method, a mechanism for outputting the branch destination address to the outside of the chip every time a branch occurs is provided, and the execution history is restored based on the output branch destination address. Further, it is suggested that by analyzing the source program based on the output trace information, the execution history can be restored without necessarily having all branch destination addresses. For example, in the case of a direct branch in which the branch destination address is explicitly described in the source program, the execution history can be restored from the source program without outputting the branch destination address. On the other hand, in the case of an indirect branch in which the branch destination address is not explicitly described in the source program and is determined at the time of execution, it is necessary to output the branch destination address. In addition, even during an indirect branch, when executing a return instruction for a function call instruction, the branch destination address need not be output if the relationship between the call and the return can be traced from the trace information.

Hereinafter, hardware that realizes these suggestions and execution history restoration software will be described as conventional examples and described with reference to the drawings. FIG. 46 shows a configuration of a conventional semiconductor integrated circuit having a trace information output function. The trace packet control unit 200 includes an instruction completion signal (EOI) 101 from the CPU 100, a direct branch instruction execution signal (JMPDIR) 102, an indirect branch instruction execution signal (JMPIND) 103, a return instruction execution signal (RET) 106, and a conditional branch. In response to the condition fulfillment signal (JMPTKN) 104 at the time of instruction execution, decoding is performed in accordance with the state decoding table shown in FIG. 201 is generated. Note that the code and meaning of reference numeral 204 output to the trace status port (PCST) 901 are as follows.
Sign / Code / Meaning
SEQ "000" Sequential instruction execution
STL "010" CPU is stalled
NPC "101" Branch instruction execution without branch destination address output
JMP "100" Branch instruction execution with branch destination address output
EXP "110" Interrupt branch execution (with branch destination address output)
As shown in the state decode table of FIG. 47, only when an indirect branch instruction other than the return instruction is executed, the branch destination address 110 output from the CPU 100 is loaded into the shift register 700 and shift output is started. . When a branch instruction other than this is executed, “NPC” is output as reference numeral 204 and no significant data is output from the branch destination address output port (TPC) 902.

  On the other hand, FIG. 48 shows the configuration of the development support apparatus. The development support device includes a trace information storage device 2 and a host computer 3. The trace information storage device 2 receives the trace state signal 911 and the branch destination address signal 912 from the semiconductor integrated circuit (processor) 1 and stores them in the trace memory 1030 as trace information. The host computer 3 sends a trace memory read request 1041 to the trace information storage device 2 and acquires a trace memory output 1031.

  Next, a method for restoring the program execution history of the semiconductor integrated circuit 1 based on the trace information output from the semiconductor integrated circuit 1 will be described using the program shown in FIG. 49 as an example. It is assumed that the semiconductor integrated circuit 1 outputs the trace information shown in FIG. 50 by executing the program shown in FIG. The trace start is assumed to be the same execution order “1” (address “0x40000000”) as the program execution start.

  FIG. 51 is a flowchart of a conventional execution history restoration method. The host computer 3 restores the execution history according to the flow shown in FIG. First, in step 5001, an execution pointer IP = 0x40000000 and a trace pointer TP = 0 are set. Next, in step 5006, an instruction “instruction 1” with IP = 0x40000000 is displayed. Since the sign when TP = 0 is “SEQ” (steps 5007, 5008, 5015, 5019 and 5021), IP is incremented at step 5022 (IP = 0x40000004), and TP is incremented at step 5023 (TP = 1) Return to step 5006. The code “SEQ” when TP = 1,3,4,6,7,8,10,11,15,16 is similarly processed.

  When TP = 2, IP = 0x40000008, and in step 5006, the instruction “call Sub_A” with IP = 0x40000008 is displayed. Since the sign when TP = 2 is “NPC” (steps 5007 and 5008) and the instruction with IP = 0x40000008 is a call instruction (CALL) (steps 5009 and 5012), the address of the next instruction in step 5013 “0x4000000c” is pushed to a simulation stack implemented as software (hereinafter referred to as “soft stack”). In step 5014, IP is set to “0x40000100” (Sub_A) obtained from the source program. In step 5023, TP is incremented (TP = 3), and the process returns to step 5006. The same processing is performed for the code “NPC” when TP = 5.

  When TP = 9, IP = 0x4000020c, and in step 5006, the instruction “call (a0)” with IP = 0x4000020c is displayed. Since the sign when TP = 9 is “JMP” (steps 5007, 5008 and 5015) and the instruction with IP = 0x4000020c is a call instruction (CALL) (step 5016), the address of the next instruction in step 5017 “0x40000210” is pushed onto the soft stack, the branch destination address “0x40000300” when IP is TP = 9 is set at step 5018, TP is incremented at step 5023 (TP = 10), and the processing returns to step 5006.

  When TP = 12, IP = 0x40000308, and in step 5006, the instruction “ret” with IP = 0x40000308 is displayed. Since the sign when TP = 12 is “NPC” (steps 5007 and 5008) and the instruction with IP = 0x40000308 is a return instruction (RET) (step 5009), the return destination address is returned from the soft stack in step 5010. In step 5011, the IP address is set to “0x40000210”. In step 5023, TP is incremented (TP = 13), and the process returns to step 5006. The same processing is performed for the code “NPC” when TP = 13 and 14.

FIG. 52 shows a restoration result obtained by executing the above-described execution history restoration method. As shown in FIG. 52, the execution history of the processor 1 is correctly restored based on the source program shown in FIG. 49 and the trace information shown in FIG.
JP-A-8-185336 Tatsuo Yano and one other, “Real-time tracing was realized with a 50MHz MPU for mass production”, Nikkei Electronics 1995.7.31 (no.641) p.133-140

  The conventional technology described above has several problems as follows.

  (1) For return instructions such as function return instructions and interrupt return instructions, the output of the branch destination address is always omitted. Therefore, when the stack is switched by task switching (context switch), the branch destination address information is obtained from the source program. Not always available. Similarly, even when the stack used by the CPU is destroyed for some reason and the return address becomes invalid, the return address cannot be correctly restored.

  (2) When tracing starts from the middle instead of from the beginning of the program, the function call instruction corresponding to the return instruction and the execution of the interrupt branch do not remain as trace information, so the branch destination address information cannot be obtained. The return address of the return instruction cannot be restored.

  Similarly, when tracing with the delayed trigger method, the trace memory is used cyclically, so the past trace data is overwritten and there is no trace information related to the execution of the branch instruction corresponding to the return instruction. The execution history cannot be restored.

  (3) When indirect branching continues, information necessary for history restoration may be lost. This problem can be temporarily solved by providing an operation mode (full trace mode) in which execution of the next instruction is stopped until all branch destination addresses are output. However, when the processor is operated in the full trace mode, the execution time of the program is affected. In particular, the system may not be established in the real-time control.

  In particular, by storing the branch destination address in the branch destination address register and the branch destination instruction in the branch destination instruction register, a “high-speed branch instruction” that branches at high speed without penalizing the branch execution is provided. There is an implemented architecture. Since such a high-speed branch instruction is an indirect branch instruction, it is necessary to output a branch destination address as trace information. The high-speed branch instruction is effective when it is used as a branch of a repeated loop. However, since the interval at which the CPU executes the branch instruction is shorter than the number of cycles for outputting the branch destination address to the port 902, the trace information is displayed when the trace is output in the operation mode (non-full trace mode) in which the CPU is not stopped. In the absence of a complete history cannot be restored. On the other hand, when the trace output is performed in the full trace mode, the operation time of the CPU is affected, and in particular, there is a high possibility that the system is not established in the real-time application.

  (4) As for the high-speed branch instruction, as in the prior art, the setting instruction of the branch destination address register and the high-speed branch instruction are associated with each other to suppress the output of the branch destination address of the high-speed branch instruction. The problem is solved, but this time the branch destination address cannot be restored when the trace information of the setting instruction of the branch destination address register preceding the fast branch instruction does not remain in the trace memory. Similar problems arise.

  In view of the above problems, an object of the present invention is to optimize the output of trace information for a semiconductor integrated circuit that can execute a program. Another object of the present invention is to accurately restore a program execution history based on trace information output from such a semiconductor integrated circuit.

  Means taken by the present invention to solve the above problems is that, as a semiconductor integrated circuit, when a call instruction is executed, the first signal is asserted and a branch destination address and a return destination address related to the call instruction are output. When the interrupt branch is executed, the second signal is asserted, the branch destination address and the return destination address related to the interrupt branch are output, and when the return instruction is executed, the third signal is asserted and the return instruction When the CPU that outputs the branch destination address and any of the first and second signals are asserted, the return destination address output from the CPU is pushed, and when the third signal is asserted, the push is performed. Stack memory that pops the return destination address that has been popped, and the return destination address popped from the stack memory and the CPU A comparator that compares the branch destination address, a trace packet control unit that receives a plurality of signals including first to third signals from the CPU and outputs a trace status code based on the plurality of signals, and a CPU And an address register that receives the branch destination address output from the terminal and outputs the address under the control of the trace packet control unit. Here, it is assumed that the trace packet control unit instructs the address register to output an address when the third signal is asserted and the comparison result received from the comparator indicates a mismatch.

  According to the present invention, when a call instruction or an interrupt branch is executed by the CPU, the return destination address is pushed to the stack memory, and when the return instruction is executed by the CPU, the return destination address pushed to the stack memory is popped. The comparator compares the popped address with the actual branch destination output from the CPU, and if there is a mismatch, the address is output from the CPU by the address register instructed by the trace packet control unit. The branch destination address is output as trace information. That is, when the return instruction is executed, only when the branch destination is different from the predicted branch destination, the branch destination address is output as the trace information, and the trace information output is optimized.

  Further, as a development support apparatus for restoring the program execution history based on the trace information output from the semiconductor integrated circuit, a trace memory for storing the trace state code and address output from the semiconductor integrated circuit as trace information, and this An execution history restoring unit that restores the execution history of the source program executed by the CPU while sequentially corresponding the source program executed by the CPU in the semiconductor integrated circuit and the trace information stored in the trace memory is provided. The history restoration unit obtains a return destination address from the source program and pushes it from the trace information when a call instruction is detected from the source program or when a code indicating execution of an interrupt branch is detected from the trace information. Get branch destination address And source, upon detection of a return instruction from a source program, shall be restored by popping the return address that is pushed.

  According to the present invention, when the call history is detected from the source program by the execution history restoring unit or the code indicating execution of the interrupt branch is detected from the trace information stored in the trace memory, the return obtained from the source program is obtained. The destination address is pushed and the branch destination address obtained from the trace information is restored. When a return instruction is detected from the source program, the pushed return destination address is popped and restored. Therefore, the branch destination address at the time of task switching or interrupt processing that cannot be traced only from the source program is acquired from the trace information, and the program execution history is accurately restored.

  Also, the trace status code and address are obtained as trace information from this semiconductor integrated circuit, and the source program execution history by this CPU is correlated with the source program executed by the CPU in this semiconductor integrated circuit and the trace information in order. As a restoration method, a step of detecting a call instruction from a source program, a step of detecting a code indicating execution of an interrupt branch from trace information, a step of detecting a return instruction from the source program, and the above-described call instruction and code When either one is detected, the return destination address is obtained from the source program and pushed, and when any one of the above call instructions and codes is detected, the branch destination address is obtained from the trace information and restored. Step and the above return instruction When it is assumed that a step of restoring pops the return address that is pushed.

  According to the present invention, when a call instruction is detected from the source program or when a code indicating execution of an interrupt branch is detected from the stored trace information, the return destination address obtained from the source program is pushed and the trace information The branch destination address obtained from the above is restored, and when a return instruction is detected from the source program, the pushed return destination address is popped and restored. Therefore, the branch destination address at the time of task switching or interrupt processing that cannot be traced only from the source program is acquired from the trace information, and the program execution history is accurately restored.

  Preferably, in the semiconductor integrated circuit, the trace packet control unit instructs the address register to output an address when the third signal is asserted and an underflow occurs in the stack memory.

  According to the present invention, when a return instruction is executed even though the stack memory is empty, an unexpected branch destination address is output as trace information.

  Preferably, the semiconductor integrated circuit includes a synchronization request generation circuit that asserts a fourth signal when tracing is started. In addition, the stack memory initializes the stored contents when the fourth signal is asserted.

  According to the present invention, when the trace is started in the middle of the program execution, the contents of the stack memory are initialized, and when the return instruction corresponding to the call instruction or the like executed before the start of the trace is executed, the stack is Since the memory is empty, a mismatch occurs with the branch destination address of the return instruction, and the branch destination address related to the subsequent return instruction is output as trace information. As a result, the development history before the start of tracing is accurately restored by the development support apparatus.

  More preferably, the CPU outputs an execution address of the executed instruction when the instruction is executed, and the semiconductor integrated circuit outputs either one of the branch destination address and the execution address output from the CPU. It is assumed that a selector that selectively outputs is provided. Here, the address register receives the address output from the selector instead of the branch destination address output from the CPU, and outputs the address under the control of the trace packet control unit. The trace packet control unit When the fourth signal is asserted, a code indicating a trace start is output as the trace status code, and when the first and second signals are negated, the selector is instructed to select an execution address. In other cases, the selector is instructed to select a branch destination address.

  According to the present invention, when the trace is started, if the executed instruction is a normal sequential execution instruction, its execution address is output as trace information, and if it is a branch instruction, its branch destination address is output. As a result, the address information of the trace start point is output.

  Further, as a development support apparatus for restoring the program execution history based on the trace information output from the semiconductor integrated circuit, a trace memory for storing the trace state code and address output from the semiconductor integrated circuit as trace information, and this An execution history restoring unit that restores the execution history of the source program executed by the CPU while sequentially corresponding the source program executed by the CPU in the semiconductor integrated circuit and the trace information stored in the trace memory is provided. The history restoration unit obtains a return destination address from the source program and pushes it from the trace information when a call instruction is detected from the source program or when a code indicating execution of an interrupt branch is detected from the trace information. Get branch destination address When a return instruction is detected from the source program, the pushed return destination address is popped and restored, and when a code indicating the trace start is detected from the trace information, the pushed return is detected. It is assumed that the destination address is initialized, and either the execution address or the branch destination address corresponding to the code is obtained from the trace information and restored.

  According to the present invention, when the code indicating the start of tracing is detected from the trace information stored in the trace memory by the execution history restoring unit, the return destination address being pushed is initialized, and the code obtained from the trace information is initialized. One of the execution address and the branch destination address corresponding to is restored. Therefore, the execution history is accurately restored immediately after the trace starts.

  Also, the trace status code and address are obtained as trace information from this semiconductor integrated circuit, and the source program execution history by this CPU is correlated with the source program executed by the CPU in this semiconductor integrated circuit and the trace information in order. As a restoration method, a step of detecting a call instruction from the source program, a step of detecting a return instruction from the source program, a step of detecting a first code indicating execution of an interrupt branch from the trace information, and a trace from the trace information A step of detecting a second code indicating a start; a step of obtaining and pushing a return destination address from the source program when one of the call instruction and the first code is detected; and the call instruction and the first code When either one of the codes is detected, A branch destination address is obtained from the source information and restored; when a return instruction is detected, a step of popping and restoring the pushed return destination address; and when a second code is detected, push Initializing the restored return address, and obtaining and restoring either the execution address or the branch destination address corresponding to the second code from the trace information when the second code is detected. Shall be.

  According to the present invention, when the code indicating the trace start is detected from the trace information, the return destination address being pushed is initialized, and either the execution address or the branch destination address corresponding to the code obtained from the trace information is initialized. Is restored. Therefore, the execution history is accurately restored immediately after the trace starts.

  On the other hand, the means taken by the present invention to solve the above problem is a CPU having an indirect branch instruction that branches to a branch destination address stored in a register as a semiconductor integrated circuit, and when this register is updated, When the first signal is asserted and the indirect branch instruction is executed, the second signal is asserted and the branch destination address related to the indirect branch instruction is output, and the second signal after the first signal is asserted. Until the signal of the signal is asserted, a loop detection circuit that asserts the third signal, and a trace that receives a plurality of signals including the second signal from the CPU and outputs a trace status code based on the plurality of signals A packet control unit and an address register that receives the branch destination address output from the CPU and outputs the address under the control of the trace packet control unit; It is assumed that with. Here, it is assumed that the trace packet control unit instructs the address register to output an address when the second and third signals are asserted.

  According to the present invention, when the loop detection circuit detects the start of high-speed loop processing with a high-speed branch instruction and the CPU executes the first indirect branch instruction in the loop processing, the branch destination address is used as trace information. The branch destination address is not output for the execution of the second and subsequent indirect branch instructions. Thereby, the trace information output of the semiconductor integrated circuit in which the indirect branch instruction is mounted is optimized.

  Further, as a development support apparatus for restoring the program execution history based on the trace information output from the semiconductor integrated circuit, a trace memory for storing the trace state code and address output from the semiconductor integrated circuit as trace information, and this An execution history restoring unit that restores the execution history of the source program executed by the CPU while sequentially corresponding the source program executed by the CPU in the semiconductor integrated circuit and the trace information stored in the trace memory is provided. When the history restoring unit detects an indirect branch instruction from the source program and detects a code indicating execution of the indirect branch instruction with the branch destination address from the trace information, the history restoring unit stores the branch destination address and the branch destination. Restore address and indirectly from source program Detecting a 岐命 age, and when detecting a code indicating the execution of the indirect branch instruction without a branch address from the trace information shall restore the stored branch address.

  According to the present invention, the execution history restoring unit detects an indirect branch instruction from the source program, and detects a code indicating execution of the indirect branch instruction with the branch destination address from the trace information stored in the trace memory. When this branch destination address is stored, this branch destination address is restored, an indirect branch instruction is detected from the source program, and a code indicating execution of the indirect branch instruction without the branch destination address from the trace information When is detected, the stored branch destination address is restored. Accordingly, even when the trace information does not include the branch destination address of the indirect branch instruction related to the second and subsequent executions regarding the high-speed loop processing including the indirect branch instruction, the program execution history is accurately restored.

Further, a trace state code and an address are obtained as trace information from the semiconductor integrated circuit, and the source program executed by the CPU in the semiconductor integrated circuit is sequentially associated with the trace information, and the execution history of the source program executed by the CPU. Are detected as follows: a step of detecting an indirect branch instruction from a source program; a step of detecting a first code indicating execution of an indirect branch instruction with a branch destination address from trace information; and a branch destination address from trace information Detecting a second code indicative of execution of an indirect branch instruction without the step; storing a branch destination address associated with the first code when the indirect branch instruction and the first code are detected; When the indirect branch instruction and the first code are detected, the branch destination address associated with the first code is detected. And restoring the less, when the indirect branch instruction and the second code is detected, it is assumed that a step of restoring the stored branch destination address.
An execution history restoration method characterized by the above.

  According to the present invention, when an indirect branch instruction is detected from the source program and the first code indicating execution of the indirect branch instruction with the branch destination address is detected from the trace information, the branch destination address is stored. And the branch destination address is restored, the indirect branch instruction is detected from the source program, and the second code indicating the execution of the indirect branch instruction without the branch destination address is detected from the trace information, The stored branch destination address is restored. Accordingly, even when the trace information does not include the branch destination address of the indirect branch instruction related to the second and subsequent executions regarding the high-speed loop processing including the indirect branch instruction, the program execution history is accurately restored.

  Specifically, in the above-described semiconductor integrated circuit, when the first signal is asserted, the loop detection circuit is asserted with a holding circuit that holds the third signal in an asserted state and a second signal. And a reset circuit for resetting the state held by the holding circuit.

  Preferably, the semiconductor integrated circuit includes a synchronization request generation circuit that asserts a fourth signal when tracing is started. The loop detection circuit asserts the third signal during the period from when the fourth signal is asserted to when the signal is asserted.

  According to the present invention, when the trace is started in the middle of the program execution, the loop process is detected again by the loop detection circuit, and the second and subsequent executions in the high-speed loop process started before the trace start. The branch destination address of the indirect branch instruction related to the first execution after the trace is started is output as trace information. As a result, the development history before the start of tracing is accurately restored by the development support apparatus.

  More preferably, the CPU outputs an execution address of the executed instruction when the instruction is executed, and the semiconductor integrated circuit outputs either one of the branch destination address and the execution address output from the CPU. It is assumed that a selector that selectively outputs is provided. Here, the address register receives the address output from the selector instead of the branch destination address output from the CPU, and outputs the address under the control of the trace packet control unit. The trace packet control unit When the fourth signal is asserted, a code indicating the trace start is output as the trace status code, and when the second signal is negated, the selector is instructed to select the execution address. In this case, the selector is instructed to select a branch destination address.

  According to the present invention, when the trace is started, if the instruction to be executed is a normal sequential execution instruction, its execution address is output as trace information, and if it is an indirect branch instruction, its branch destination address is output. As a result, the address information of the trace start point is output.

  Further, as a development support apparatus for restoring the program execution history based on the trace information output from the semiconductor integrated circuit, a trace memory for storing the trace state code and address output from the semiconductor integrated circuit as trace information, and this An execution history restoring unit that restores the execution history of the source program by the CPU while sequentially corresponding the source program executed by the CPU in the semiconductor integrated circuit and the trace information stored in the trace memory, When the execution history restoring unit detects an indirect branch instruction from the source program and detects a code indicating execution of the indirect branch instruction with the branch destination address from the trace information, the execution history restoring unit stores the branch destination address and the branch destination. Restore address and indirectly from source program When the branch instruction is detected and the code indicating the execution of the indirect branch instruction without the branch destination address is detected from the trace information, the stored branch destination address is restored, and the trace start is started from the trace information. When the code shown is detected, either the execution address or the branch destination address corresponding to the code is obtained from the trace information and restored.

  According to the present invention, when the execution history restoring unit detects a code indicating the start of tracing from the trace information stored in the trace memory, either the execution address or the branch destination address corresponding to the code obtained from the trace information is detected. Is restored. Therefore, the execution history is accurately restored immediately after the trace starts.

  Also, the trace status code and address are obtained as trace information from this semiconductor integrated circuit, and the source program execution history by this CPU is correlated with the source program executed by the CPU in this semiconductor integrated circuit and the trace information in order. As a restoration method, a step of detecting an indirect branch instruction from a source program, a step of detecting a first code indicating execution of an indirect branch instruction accompanied by a branch destination address from trace information, and a branch destination address from trace information Detecting a second code indicating execution of an indirect branch instruction without accompanying; detecting a third code indicating start of tracing from the trace information; and detecting an indirect branch instruction and the first code, Storing a branch destination address associated with the first code, and indirect branching A step of restoring the branch destination address associated with the first code when the instruction and the first code are detected; and a stored branch destination address when the indirect branch instruction and the second code are detected. And a step of obtaining and restoring either the execution address or the branch destination address corresponding to the third code from the trace information when the third code is detected.

  According to the present invention, when a code indicating a trace start is detected from the trace information, either the execution address or the branch destination address corresponding to the code obtained from the trace information is restored. Therefore, the execution history is accurately restored immediately after the trace starts.

  On the other hand, the means taken by the present invention to solve the above problems is a CPU having an indirect branch instruction that branches to a branch destination address stored in a register as a semiconductor integrated circuit, and executes the indirect branch instruction. The CPU that asserts the first signal and outputs the branch destination address related to the indirect branch instruction, and outputs the stored address when the first signal is asserted, and the branch destination output from the CPU A first address register for storing an address; a comparator for comparing a branch destination address output from the first address register with a branch destination address output from the CPU; and a plurality of signals including a first signal from the CPU A trace packet control unit that receives a signal and outputs a trace status code based on the plurality of signals, and a branch destination address output from the CPU. Only, and that a second address register for outputting the address under the control of the trace packet control unit. Here, it is assumed that the trace packet control unit instructs the second address register to output an address when the first signal is asserted and the comparison result received from the comparator indicates a mismatch.

  According to the present invention, when the indirect branch instruction is executed by the CPU, the branch destination address stored in the first address register is output and the content is updated, and the comparator executes the indirect branch instruction. When the branch destination address and the branch destination address output from the first address register do not match, the branch destination address output from the CPU is output as trace information, and is not output when they match. That is, in high-speed loop processing including an indirect branch instruction, the branch destination address is output as trace information for the first indirect branch instruction execution, and the branch destination for the second and subsequent indirect branch instruction executions. The address is not output. Thereby, the trace information output of the semiconductor integrated circuit in which the indirect branch instruction is mounted is optimized.

  Further, as a development support apparatus for restoring the program execution history based on the trace information output from the semiconductor integrated circuit, a trace memory for storing the trace state code and address output from the semiconductor integrated circuit as trace information, and this An execution history restoring unit that restores the execution history of the source program executed by the CPU while sequentially corresponding the source program executed by the CPU in the semiconductor integrated circuit and the trace information stored in the trace memory is provided. When the history restoring unit detects an indirect branch instruction from the source program and detects a code indicating execution of the indirect branch instruction with the branch destination address from the trace information, the history restoring unit stores the branch destination address and the branch destination. Restore address and indirectly from source program Detecting a 岐命 age, and when detecting a code indicating the execution of the indirect branch instruction without a branch address from the trace information shall restore the stored branch address.

  According to the present invention, the execution history restoring unit detects an indirect branch instruction from the source program, and detects a code indicating execution of the indirect branch instruction with the branch destination address from the trace information stored in the trace memory. When this branch destination address is stored, this branch destination address is restored, an indirect branch instruction is detected from the source program, and a code indicating execution of the indirect branch instruction without the branch destination address from the trace information When is detected, the stored branch destination address is restored. Accordingly, even when the trace information does not include the branch destination address of the indirect branch instruction related to the second and subsequent executions regarding the high-speed loop processing including the indirect branch instruction, the program execution history is accurately restored.

Further, a trace state code and an address are obtained as trace information from the semiconductor integrated circuit, and the source program executed by the CPU in the semiconductor integrated circuit is sequentially associated with the trace information, and the execution history of the source program executed by the CPU. Are detected as follows: a step of detecting an indirect branch instruction from a source program; a step of detecting a first code indicating execution of an indirect branch instruction with a branch destination address from trace information; and a branch destination address from trace information Detecting a second code indicative of execution of an indirect branch instruction without the step; storing a branch destination address associated with the first code when the indirect branch instruction and the first code are detected; When the indirect branch instruction and the first code are detected, the branch destination address associated with the first code is detected. And restoring the less, when the indirect branch instruction and the second code is detected, it is assumed that a step of restoring the stored branch destination address.
An execution history restoration method characterized by the above.

  According to the present invention, when an indirect branch instruction is detected from the source program and the first code indicating execution of the indirect branch instruction with the branch destination address is detected from the trace information, the branch destination address is stored. And the branch destination address is restored, the indirect branch instruction is detected from the source program, and the second code indicating the execution of the indirect branch instruction without the branch destination address is detected from the trace information, The stored branch destination address is restored. Accordingly, even when the trace information does not include the branch destination address of the indirect branch instruction related to the second and subsequent executions regarding the high-speed loop processing including the indirect branch instruction, the program execution history is accurately restored.

  Preferably, the semiconductor integrated circuit includes a synchronization request generation circuit that asserts the second signal when tracing is started. The first address register initializes the stored contents when the second signal is asserted.

  According to the present invention, when tracing is started in the middle of program execution, the storage contents of the first address register are initialized, and the second and subsequent executions are performed in the high-speed loop processing started before the start of tracing. Thus, the branch destination address of the indirect branch instruction related to the first execution after the trace is started is output as trace information. As a result, the development history before the start of tracing is accurately restored by the development support apparatus.

  More preferably, the CPU outputs an execution address of the executed instruction when the instruction is executed, and the semiconductor integrated circuit outputs either one of the branch destination address and the execution address output from the CPU. It is assumed that a selector that selectively outputs is provided. Here, the second address register receives the address output from the selector instead of the branch destination address output from the CPU, and outputs the address under the control of the trace packet control unit. When the second signal is asserted, the control unit outputs a code indicating a trace start as a trace status code, and further instructs the selector to select an execution address when the first signal is negated. In other cases, the selector is instructed to select a branch destination address.

  According to the present invention, when the trace is started, if the instruction to be executed is a normal sequential execution instruction, its execution address is output as trace information, and if it is an indirect branch instruction, its branch destination address is output. As a result, the address information of the trace start point is output.

  Further, as a development support apparatus for restoring the program execution history based on the trace information output from the semiconductor integrated circuit, a trace memory for storing the trace state code and address output from the semiconductor integrated circuit as trace information, and this An execution history restoring unit that restores the execution history of the source program by the CPU while sequentially corresponding the source program executed by the CPU in the semiconductor integrated circuit and the trace information stored in the trace memory, When the execution history restoring unit detects an indirect branch instruction from the source program and detects a code indicating execution of the indirect branch instruction with the branch destination address from the trace information, the execution history restoring unit stores the branch destination address and the branch destination. Restore address and indirectly from source program When the branch instruction is detected and the code indicating the execution of the indirect branch instruction without the branch destination address is detected from the trace information, the stored branch destination address is restored, and the trace start is started from the trace information. When the code shown is detected, either the execution address or the branch destination address corresponding to the code is obtained from the trace information and restored.

  According to the present invention, when the execution history restoration unit detects a code indicating the start of tracing from the trace information stored in the trace memory, either the execution address or the branch destination address corresponding to the code obtained from the trace information is detected. Is restored. Therefore, the execution history is accurately restored immediately after the trace starts.

  Also, the trace status code and address are obtained as trace information from this semiconductor integrated circuit, and the source program execution history by this CPU is correlated with the source program executed by the CPU in this semiconductor integrated circuit and the trace information in order. As a restoration method, a step of detecting an indirect branch instruction from a source program, a step of detecting a first code indicating execution of an indirect branch instruction accompanied by a branch destination address from trace information, and a branch destination address from trace information Detecting a second code indicating execution of an indirect branch instruction without accompanying; detecting a third code indicating start of tracing from the trace information; and detecting an indirect branch instruction and the first code, Storing a branch destination address associated with the first code, and indirect branching A step of restoring the branch destination address associated with the first code when the instruction and the first code are detected; and a stored branch destination address when the indirect branch instruction and the second code are detected. And a step of obtaining and restoring either the execution address or the branch destination address corresponding to the third code from the trace information when the third code is detected.

  According to the present invention, when a code indicating a trace start is detected from the trace information, either the execution address or the branch destination address corresponding to the code obtained from the trace information is restored. Therefore, the execution history is accurately restored immediately after the trace starts.

  According to the present invention, the branch destination address that can be restored by referring to the source program when restoring the program execution history is not output as trace information, and cannot be traced only by referring to the source program, for example, task switching. The branch destination address related to the return instruction is output as the trace information when an interrupt process or the like occurs or when the trace is started later than the program execution. Thereby, the trace information output of the semiconductor integrated circuit is optimized. Further, an accurate program execution history is restored based on the trace information output from such a semiconductor integrated circuit.

  The best mode for carrying out the present invention will be described below with reference to the drawings.

(First embodiment)
FIG. 1 shows a configuration of a semiconductor integrated circuit according to the first embodiment of the present invention. The semiconductor integrated circuit 1 according to the present embodiment includes a CPU 100, a trace packet control unit 200, a stack memory 300, a comparator 400, and a shift register 700.

  The CPU 100 executes the instruction execution completion signal (EOI) 101 when the instruction execution is completed, the direct branch instruction execution signal (JMPDIR) 102 when the direct branch instruction is executed, and the indirect branch instruction when the indirect branch instruction is executed. When the execution signal (JMPIND) 103 is executed, when the conditional branch instruction is executed, the condition establishment signal (JMPTKN) 104 is executed. When the function call instruction is executed, the function call instruction execution signal (CALL) 105 is sent as the function return instruction or interrupt return. When an instruction is executed, a return instruction execution signal (RET) 106 is asserted. When an interrupt is accepted and a branch is executed, an interrupt execution signal (EXP) 108 is asserted. Further, the CPU 100 executes the function call instruction, interrupt branch, function return instruction, or interrupt return instruction when the function call instruction or interrupt branch is executed. Output each.

  The stack memory 300 receives the logical sum of the signals CALL and EXP calculated by the OR circuit 350 as a push signal, the signal RET as a pop signal, and the return destination address 120 as data. That is, the stack memory 300 pushes the return address 120 output from the CPU 100 when the function call instruction or interrupt branch is executed by the CPU 100, and pushes when the function return instruction or interrupt return instruction is executed. The return address that is present is popped and the stack top data 301 is output. The output data 301 represents the expected value of the return destination address. Further, the stack memory 300 asserts the stack valid signal 302 when the stack contents are valid.

  The comparator 400 compares the data 301 output from the stack memory 300 with the branch destination address 110 output from the CPU 100, and outputs a match / mismatch as a comparison result signal 401. The comparison result signal 401 is asserted when they match and is negated when they do not match. The comparison result signal 401 and the stack valid signal 302 are ANDed by the AND circuit 500 and sent to the trace packet control unit 200 as a return destination address match signal 501.

  FIG. 2 shows a state decoding table of the trace packet control unit 200. The trace packet control unit 200 receives the signals EOI, JMPDIR, JMPIND, CALL, RET, JMPTKN and EXP, and the return destination address match signal 501, and according to the state decode table shown in FIG. 2, the branch destination address load enable signal (TPCLDEN ) 201 and the code 204 to be output to the trace status port (PCST) 901 is determined.

  When the signal TPCLDEN is asserted, the shift register 700 loads the branch destination address 110, converts it into serial data, and sends the data 701 to the branch destination address output port (TPC) 902.

  On the other hand, the development support apparatus according to the present embodiment has the same configuration as the development support apparatus shown in FIG. The trace memory control unit 1010 and the serial-parallel converter 1020 in the trace information storage device 2 reshape the trace state signal 911 and the branch destination address signal 912 output from the semiconductor integrated circuit 1, respectively, and store the trace information in the trace memory 1030. Accumulate as. The host computer 3 sends a trace memory read request 1041 to the trace information storage device 2, acquires the trace memory output 1031, and restores the program execution history of the semiconductor integrated circuit 1 while sequentially matching the acquired information and the source program. To do. The operation of the host computer 3 as the execution history restoring unit is different from the conventional one. This will be described later.

  Next, trace information output and execution history restoration by the semiconductor integrated circuit 1 and the development support apparatus according to the present embodiment will be described by taking the case of executing the program shown in FIG. 3 as an example. In this example, the semiconductor integrated circuit 1 starts program execution and tracing from the instruction “instruction 1” at the address “0x50000000” (execution order “1”), and the instruction “at the address“ 0x50000210 ”(execution order“ 14 ”)” After executing "ret", the interrupt is accepted and the branch is executed, the task is switched from task "taskA" to task "taskB" with interrupt handler "int0h", and address "0x40000110" (execution order "19") The instruction “rti” returns to the address “0x50000610”. Note that saving / restoring processing of registers and the like is omitted.

  FIG. 4 shows trace information output when the semiconductor integrated circuit 1 executes the program shown in FIG. The trace information shown in FIG. 4 is obtained as a result of the operation of the semiconductor integrated circuit 1 described below. In the following description, when addresses are pushed to the stack memory 300 in the order of A, B, C, and D, the contents of the stack are represented as (D, C, B, A). When the stack memory 300 is popped, the stack top data 301 is output in the order of D, C, B, and A.

  When the CPU 100 executes the normal sequential execution instructions in the execution order “1, 2, 4, 5, 7, 8, 9, 11, 12, 15, 16, 17, 18, 22, 23”, only the signal EOI is Asserted (output "1"). At this time, the signal TPCLDEN is not asserted (output “0”), and only the code “SEQ” is output as the trace information.

When the CPU 100 executes the call instruction “call Sub_A” at the address “0x50000008” (execution order “3”), the signals JMPDIR, CALL, JMPTKN, and EOI are asserted. At this time, when the push signal output from the OR circuit 350 is asserted, the return destination address 120 ("0x5000000c") output from the CPU 100 is pushed, and the contents of the stack memory 300 are:
(0x5000000c)
It becomes. At this time, the signal TPCLDEN is not asserted, and only the code “NPC” is output as the trace information.

Similarly, when the CPU 100 executes the call instruction “call Sub_B” at the address “0x50000108” (execution order “6”), the return destination address 120 (“0x5000010c”) is pushed, and the contents of the stack memory 300 are:
(0x5000010c, 0x5000000c)
It becomes. At this time, only the code “NPC” is output as the trace information.

When the CPU 100 executes the call instruction “call (a0)” at the address “0x5000020c” (execution order “10”), the return address 120 (“0x50000210”) is pushed, and the contents of the stack memory 300 are
(0x50000210,0x5000010c, 0x5000000c)
It becomes. At this time, since the branch condition is satisfied, the signal JMPIND is asserted and the signal TPCLDEN is asserted (output “1”). As a result, the code “JMP” is output as the trace information. When the signal TPCLDEN is asserted, the shift register 700 receives the branch destination address 110 (“0x50000300”) output from the CPU 100, and outputs the branch destination address “0x50000300” as trace information.

When the CPU 100 executes the return instruction “ret” at the address “0x50000308” (execution order “13”), the signal RET is asserted. Then, the expected value “0x500000210” of the return destination address is popped, and the contents of the stack memory 300 are
(0x5000010c, 0x5000000c)
It becomes. At this time, since the popped expected value (“0x500000210”) matches the actual branch destination address 110 (“0x500000210”) output from the CPU 100, the comparison result signal 401 is asserted (output “1”). . At this time, since the contents of the stack memory 300 are valid, the stack valid signal 302 is asserted, and the return address match signal 501 is asserted (output “1”). When the signal RET and the return address match signal 501 are asserted, the signal TPCLDEN is not asserted, and only the code “NPC” is output as the trace information.

Similarly, when the CPU 100 executes the return instruction “ret” in the execution order “14” (address “0x50000210”), the expected value “0x5000010c” of the return destination address is popped, and the contents of the stack memory 300 are
(0x5000000c)
It becomes. At this time, since the popped expected value (“0x5000010c”) matches the branch destination address 110 (“0x5000010c”) output from the CPU 100, only the code “NPC” is output as the trace information.

An interrupt occurs after execution of the return instruction “ret” of the execution order “14” (address “0x50000210”) and before execution of the return instruction “ret” of the return destination address “0x5000010c”, and the CPU 100 accepts this interrupt. , Signal EXP is asserted. At this time, when the push signal output from the OR circuit 350 is asserted, the return address 120 (“0x5000010c”) output from the CPU 100 is pushed, and the contents of the stack memory 300 are:
(0x5000010c, 0x5000000c)
It becomes. At this time, the signal TPCLDEN is asserted, and the code “EXP” and the branch destination address “0x40000100” are output as the trace information.

In the interrupt handler “int0h”, the stack is switched, and when the CPU executes the interrupt return instruction “rti” in the execution order “19” (address “0x40000110”), the signal RET is asserted. Then, the expected value “0x5000010c” of the return destination address is popped, and the contents of the stack memory 300 are
(0x5000000c)
It becomes. At this time, since the branch destination address 110 output from the CPU 100 is “0x50000610” and does not match the popped expected value “0x5000010c”, the comparison result signal 401 is not asserted (output “0”), and the return destination address The match signal 501 is also not asserted. When the signal RET is asserted and the return destination address match signal 501 is not asserted, the signal TPCLDEN is asserted, and the code “JMP” and the branch destination address “0x50000610” are output as the trace information.

Similarly, when the CPU 100 executes the return instruction “ret” in the execution order “20” (address “0x50000610”), the expected value “0x5000000c” of the return destination address is popped, and the contents of the stack memory 300 are
()
It becomes. At this time, the branch destination address 110 output from the CPU 100 is “0x5000050c” and does not match the popped expected value “0x5000000c”, so the code “JMP” and the branch destination address “0x5000050c” are output as the trace information. .

  When the CPU 100 executes the return instruction “ret” in the execution order “21” (address “0x5000050c”), the signal RET is asserted. However, since the stack memory 300 is empty, an underflow occurs. As a result, the stack valid signal 302 is negated (output “0”), and the return address match signal 501 is also negated (output “0”). When the signal RET is asserted and the return destination address match signal 501 is not asserted, the signal TPCLDEN is asserted, and the code “JMP” and the branch destination address “0x5000040c” are output as the trace information.

  With the above operation, the trace information shown in FIG. 4 is output from the semiconductor integrated circuit 1 according to the present embodiment.

  On the other hand, FIG. 5 and FIG. 6 are flowcharts of the execution history restoration method executed by the development support apparatus according to this embodiment. FIG. 7 shows a program execution history restored by the development support apparatus according to the present embodiment. The program execution history shown in FIG. 7 is obtained as a result of execution of the execution history restoring method described below.

  The trace pointer (TP) at the start of processing is “24” (IP = 24). First, in step 2001, the end trace pointer (ETP) becomes the current trace pointer (ETP = 24), and the trace pointer (TP). Is set to the start address of the trace memory (TP = 0), and the execution pointer (IP) is set to the trace start address (IP = 0x50000000).

  When TP = 0, IP = 0x50000000, and in step 2006, the program part “0x50000000 taskA: instruction 1” obtained from the source program is restored and displayed. At this time, since the code indicated in the trace information is “SEQ” (steps 2007, 2008, 2017, 2024 and 2032), IP is incremented in step 2033 (IP = 0x5000004), and TP is incremented in step 2034. (TP = 1), the process returns to step 2006. The same processing is performed when TP = 1,3,4,6,7,8,10,11,15,16,17,18,22,23.

When TP = 2, IP = 0x50000008, the sign shown in the trace information is “NPC” (steps 2007 and 2008), and the instruction shown in the source program is “call Sub_A”, that is, a call instruction ( CALL) (steps 2009 and 2014), the next address “0x5000000c” of the current IP is pushed to the soft stack as the return destination address in step 2015, and the contents of the soft stack are
(0x5000000c)
It becomes. In step 2016, IP is set to the branch destination address of the instruction “call Sub_A” indicated in the source program (IP = 0x50000100), TP is incremented in step 2034 (TP = 3), and the process returns to step 2006. . The same processing is performed when TP = 5.
(0x5000010c, 0x5000000c)
It becomes.

When TP = 9, IP = 0x5000020c, the code shown in the trace information is “JMP” (steps 2007, 2008 and 2017), and the instruction shown in the source program is “call (a0)”, that is, Since this is a call instruction (CALL) (steps 2018 and 2020), the next address “0x50000210” of the current IP is pushed to the soft stack as the return destination address in step 2021, and the contents of the soft stack are
(0x50000210,0x5000010c, 0x5000000c)
It becomes. Then, in step 2028, IP is set to the branch destination address “0x50000300” corresponding to TP = 9 indicated in the trace information (IP = 0x50000300), and TP is incremented in step 2034 (TP = 10). Return to 2006.

When TP = 12, IP = 0x50000308, the sign shown in the trace information is “NPC” (steps 2007 and 2008), and the instruction shown in the source program is “ret”, that is, a return instruction (RET ) (Step 2009), the return address “0x50000210” is popped from the soft stack in step 2010, and the contents of the soft stack are
(0x5000010c, 0x5000000c)
It becomes. In step 2011, the IP is set to the popped address (IP = 0x50000210). In step 2034, TP is incremented (TP = 13), and the process returns to step 2006.

When TP = 13, the same processing is performed as when TP = 12, and the IP is set to the popped address (IP = 0x5000010c). The contents of the soft stack at the end of the process of TP = 13 are
(0x5000000c)
It becomes.

When TP = 14, IP = 0x5000010c, and the code indicated in the trace information is “EXP” (steps 2007, 2008, 2017, and 2024). Therefore, the address “0x5000010c” indicated by the current IP in step 2025 Is pushed onto the soft stack and the contents of the soft stack are
(0x5000010c, 0x5000000c)
It becomes. Then, in step 2028, IP is set to the branch destination address “0x40000100” corresponding to TP = 14 indicated in the trace information (IP = 0x40000100), and in step 2034, TP is incremented (TP = 15). Return to 2006.

When TP = 19, IP = 0x40000110, the sign shown in the trace information is “JMP” (steps 2007, 2008 and 2017), and the instruction shown in the source program is “rti”, that is, a return instruction (RET) (step 2018), the return address “0x5000010c” is popped from the soft stack in step 2019, and the contents of the soft stack are
(0x5000000c)
It becomes. However, since the branch destination address “0x50000610” corresponding to TP = 19 is included in the trace information, the popped return destination address “0x5000010c” is discarded, and the TP = IP indicated in the trace information in step 2028 The branch destination address “0x50000610” corresponding to 19 is set (IP = 0x50000610), TP is incremented in step 2034 (TP = 20), and the process returns to step 2006. The same processing is performed when TP = 20 and 21.

  With the above processing, the program execution history shown in FIG. 7 is restored by the development support apparatus according to the present embodiment.

  As described above, according to the present embodiment, the branch destination address related to the return instruction is not normally output as trace information of the program execution by the CPU, and is output only when it is different from the expected return destination by stack switching or interrupt processing. The In other words, even if stack switching, interrupt processing, etc. occurs, the branch destination address related to the minimum return instruction is output so that the correct program execution history can be restored, and the trace information output is optimal It becomes. In addition, the program execution history can be accurately restored from the trace information optimized in this way.

(Second Embodiment)
FIG. 8 shows a configuration of a semiconductor integrated circuit according to the second embodiment of the present invention. The semiconductor integrated circuit 1 according to the present embodiment has a configuration in which a synchronization request request generation circuit 800 and a selector 750 are added to the semiconductor integrated circuit according to the first embodiment. Hereinafter, a different part from the semiconductor integrated circuit according to the first embodiment will be described.

  When the CPU 100 executes an instruction, the CPU 100 outputs an execution address 111 of the instruction. The selector 750 receives the branch destination address 110 and the execution address 111 from the CPU 100, and outputs one of these input addresses in accordance with the selection signal 202 output from the trace packet control unit 200. Shift register 700 receives address 751 output from selector 750.

  The synchronization request generation circuit 800 is a request from the development support apparatus at the time of system reset such as when the semiconductor integrated circuit 1 is started up, at the time of task switching such as when the task is switched by the CPU 100, at the start of tracing to start outputting trace information The synchronization request signal 801 is asserted every hour or every fixed period. Thereby, for example, when the trace memory 1030 in the development support apparatus shown in FIG. 48 is likely to overflow, the synchronization request signal 801 is asserted in response to a request from the development support apparatus. Also, for example, when the synchronization request signal 801 is asserted at a constant cycle, the trace information output is initialized at a constant cycle. When the synchronization request signal 801 is asserted, the stack memory 300 initializes the stack pointer and invalidates the pushed stack contents.

  FIG. 9 shows a state decoding table of the trace packet control unit 200. Compared to the first embodiment, the trace packet control unit 200 according to the present embodiment is added with a synchronization request signal 801 as an input and a selection signal (TPCSEL) 202 as an output. Also, “SYN” and “JMPS” are added as output codes.

  On the other hand, the development support apparatus according to the present embodiment has the same configuration as the development support apparatus shown in FIG. However, the operation of the host computer 3 as the execution history restoring unit is different from the conventional one. This will be described later.

  Next, trace information output and execution history restoration by the semiconductor integrated circuit 1 and the development support apparatus according to the present embodiment will be described by taking the case of executing the program shown in FIG. 10 as an example. In this example, the semiconductor integrated circuit 1 starts program execution from the address “0x50000000” (execution order “1”), the subroutine “Sub_A” is called at the address “0x50000008” (execution order “3”), and the address “0x50000100” "Jump to. Then, when the instruction “instruction 4” at the address “0x50000104” (execution order “5”) is executed, the trace is started. Thereafter, the semiconductor integrated circuit 1 jumps to the subroutine “Sub_B” of the address “0x50000200” at the address “0x50000108” (execution order “6”), and the address “0x50000300” at the address “0x5000020c” (execution order “10”). Jump to the subroutine “Sub_C” and return to the caller in the order of “0x50000210, 0x5000010c, 0x5000010” from the address “0x50000308”.

  FIG. 11 shows trace information output when the semiconductor integrated circuit 1 executes the program shown in FIG. The trace information shown in FIG. 11 is obtained as a result of the operation of the semiconductor integrated circuit 1 described below. A characteristic part of this embodiment will be described.

By executing the call instruction “call Sub_A” at the address “0x50000008” (execution order “3”) before the trace is started, the contents of the stack memory 300 are
(0x5000000c)
It has become. However, when the execution order is “5”, tracing starts and the synchronization request signal 801 is asserted. Thereby, the stack memory 300 is initialized, and its contents are
()
It becomes.

  When the CPU 100 executes the instruction “instruction 4” at the address “0x50000104” (execution order “5”), the signal EOI is asserted and the execution address 111 (“0x50000104”) is output. At this time, the signal JMPTKN is not asserted, and the trace packet control unit 200 asserts the signal TPCLDEN and sets the value of the signal TPCSEL to “0” according to the state decoding table shown in FIG. "Is output. When the value of the signal TPCSEL is “0”, the selector 750 selects the execution address 111 (“0x5000104”) and inputs it to the shift register 700. When the signal TPCLDEN is asserted, the shift register 700 sequentially outputs the address 751 (“0x50000104”) received from the selector 750 to the port 902 as data 701. That is, when the CPU 100 executes a normal sequential execution instruction other than the branch instruction and the synchronization request signal 801 is asserted, the trace packet control unit 200 outputs “SYN” instead of “SEQ” as the reference numeral 204. At the same time, the values of the signal TPCLDEN and the signal TPCSEL are set so that the execution address 111 is output as the data 701 instead of the branch destination address 110.

  Thereafter, until the execution order “14”, trace information is output in the same manner as described in the first embodiment. In particular, when the call instruction “call (a0)” at the address “0x5000020c” (execution order “10”) is executed, the trace packet control unit 200 asserts the signal TPCLDEN and sets the value of the signal TPCSEL to “1”. Set and output “JMP” as reference numeral 204. As a result, the branch destination address 110 (“0x50000300”) is selected by the selector 750 and output from the shift register 700. The stack memory 300 is pushed in the execution order “6” and “10”, popped in the execution order “13” and “14”, and the instruction at the address “0x50000210” (execution order “14”) is executed. It is empty at the time.

  Next, when the CPU 100 executes the return instruction “ret” at the address “0x5000010c” (execution order “15”), an underflow occurs in the stack memory 300 and the return destination address match signal 501 is not asserted. The trace packet control unit 200 asserts the signal TPCLDEN according to the state decoding table shown in FIG. 9, sets the value of the signal TPCSEL to “1”, and outputs “JMP” as the code 204. As a result, the branch destination address 110 (“0x5000000c”) is sequentially output from the shift register 700 to the port 902 as data 701.

  With the above operation, the trace information shown in FIG. 11 is output from the semiconductor integrated circuit 1 according to the present embodiment.

  On the other hand, FIGS. 12 and 13 are flowcharts of an execution history restoration method executed by the development support apparatus according to the present embodiment. FIG. 14 shows a program execution history restored by the development support apparatus according to the present embodiment. The program execution history shown in FIG. 14 is obtained as a result of execution of the execution history restoring method described below. A characteristic part of this embodiment will be described.

  In step 2001, the current trace pointer (TP = 13) is set to the end trace pointer (ETP), and the trace pointer is trace data having a sign of “SYN” or “JMPS” before the current trace pointer. Set to pointer (TP = 0). Since the sign when TP = 0 is “SYN” (step 2002), in step 2003, IP is set to the execution address “0x50000104” corresponding to TP = 0 indicated in the trace information (IP = 0x50000104) The process proceeds to step 2006. The subsequent processing is the same as that described in the first embodiment. In particular, when restoring the branch destination address of the return instruction “ret” when TP = 10, the contents of the soft stack are empty and invalid, but the branch information “0x5000000c” is included in the trace information. In step 2028, IP is set to the branch destination address “0x5000000c” corresponding to TP = 10 indicated in the trace information (IP = 0x5000000c), and the restoration process is continued.

  Through the above processing, the program execution history shown in FIG. 14 is restored by the development support apparatus according to the present embodiment.

  Next, another example of trace information output by the semiconductor integrated circuit 1 according to the present embodiment and execution history restoration by the development support apparatus will be described taking the case of executing the program shown in FIG. 15 as an example. In this example, the program itself is the same as the previous example shown in FIG. 10, but the trace starts from the instruction at address “0x50000108” (execution order “6”) one instruction after the previous example. Yes.

  FIG. 16 shows trace information output when the semiconductor integrated circuit 1 executes the program shown in FIG. The trace information shown in FIG. 16 is obtained as a result of the operation of the semiconductor integrated circuit 1 described below. A characteristic part of this embodiment will be described.

The contents of the stack memory 300 are obtained by executing the call instruction “call Sub_A” at the address “0x50000008” (execution order “3”) and the call instruction “call Sub_B” at the address “0x5000108” (execution order “6”) before starting the trace. Is
(0x500010c, 0x5000000c)
It has become. However, when the execution order is “6”, tracing is started and the synchronization request signal 801 is asserted. Thereby, the stack memory 300 is initialized, and its contents are
()
It becomes.

  When the CPU 100 executes the instruction “call Sub_B” at the address “0x5000108” (execution order “6”), the signals CALL and JMPTKN are asserted. At this time, the trace packet control unit 200 asserts the signal TPCLDEN, sets the value of the signal TPCSEL to “1”, and outputs “JMPS” as a symbol 204 in accordance with the state decoding table shown in FIG. When the value of the signal TPCSEL is “1”, the selector 750 selects the branch destination address 110 (“0x50000200”) and inputs it to the shift register 700. When the signal TPCLDEN is asserted, the shift register 700 sequentially outputs the address 751 (“0x50000200”) received from the selector 750 to the port 902 as data 701. That is, when the CPU 100 executes a branch instruction and the synchronization request signal 801 is asserted, the trace packet control unit 200 outputs “JMPS” instead of “NPC” or “JMP” as a reference numeral 204. The values of the signal TPCLDEN and the signal TPCSEL are set so that the branch destination address 110 is output as the data 701.

  The subsequent operation is the same as in the previous example. In particular, the stack memory 300 is pushed in the execution order “10”, popped in the execution order “13”, and becomes empty when the instruction at the address “0x50000308” (execution order “13”) is executed. Yes. For this reason, when instructions are executed in the execution order “10” and “15”, an underflow occurs in the stack memory 300, the return address match signal 501 is not asserted, and “JMP” is output as the code 204. In addition, the branch destination address 110 is sequentially output to the port 902 as data 701.

  With the above operation, the trace information shown in FIG. 16 is output from the semiconductor integrated circuit 1 according to the present embodiment.

  On the other hand, FIG. 17 shows a program execution history restored by the development support apparatus according to the present embodiment. The program execution history shown in FIG. 14 is obtained according to the flow shown in FIGS.

  Unlike the previous example, since the sign when TP = 0 is “JMPS” (steps 2001 and 2002), IP is set to the branch destination address corresponding to TP = 0 in the trace information in step 2004 ( IP = 0x50000200), after TP is incremented in step 2005 (TP = 1), the process proceeds to step 2006. The subsequent processing is the same as in the previous example.

  As described above, according to the present embodiment, even when the trace is started after execution of the program is started, the execution address or the branch destination address at the start of the trace is output, and is also executed before the start of the trace. When a return instruction corresponding to the issued call instruction is executed, the branch destination address is output as trace information. Thereby, even if the trace is started in the middle of the program execution, the program part at the start of the trace can be restored, and further, the program part executed before the trace can be restored.

(Third embodiment)
FIG. 18 shows a configuration of a semiconductor integrated circuit according to the third embodiment of the present invention. The semiconductor integrated circuit 1 according to the present embodiment includes a CPU 100, a trace packet control unit 200, a loop detection circuit 600, and a shift register 700. Note that the shift register 700 is the same as that in the first embodiment, and a description thereof will be omitted.

  The CPU 100 implements a register indirect branch instruction as a high-speed branch instruction. For example, when executing a loop portion of a program, the branch address is stored in the loop address register (LAR) 150 and the loop instruction register (LIR) 160, respectively. The branch destination instruction is stored, and the loop portion is executed by referring to these registers, thereby enabling high-speed branching. The CPU 100 asserts the LAR update signal 130 when the register 150 is updated, and asserts the LAR indirect branch instruction execution signal (LCC) when executing the branch instruction to the branch destination address stored in the register 150. Since the other points are the same as those of the CPU 100 in the semiconductor integrated circuit 1 according to the first embodiment, description thereof is omitted.

  The loop detection circuit 600 includes a holding circuit 610 and a reset circuit 620. The holding circuit 610 is configured by an RS flip-flop, and receives the LAR update signal 130 at the set terminal and the reset signal 621 output from the reset circuit 620 at the reset terminal, and outputs the LAR update flag signal 601. The reset circuit 620 includes an AND circuit 630 that calculates a logical product of the signals LCC and JMPTKN, and a D flip-flop 640 that receives the output of the AND circuit 630 and outputs a reset signal 621. The D flip-flop 640 is provided to delay the output of the AND circuit 630 in order to adjust the set / reset timing of the holding circuit 610. With the above configuration, the loop detection circuit 600 asserts the LAR update flag signal 601 when the register 150 is updated and the LAR update signal 130 is asserted, and when the loop initial signal LCC and JMPTKN are asserted, The update flag signal 601 is negated. That is, the loop detection circuit 600 asserts the LAR update flag signal 601 only when the execution of a certain loop portion is started and the register indirect branch instruction is executed for the first time, and the second and subsequent register indirect branch instructions are executed. Do not assert. As shown in FIG. 19, the holding circuit 610 in the loop detection circuit 600 may be configured with a D flip-flop.

  FIG. 20 shows a state decoding table of the trace packet control unit 200. The trace packet control unit 200 receives the signals EOI, JMPDIR, JMPIND, RET, LCC, JMPTKN and EXP, and the LAR update flag signal 601, and receives the branch destination address load enable signal (TPCLDEN) according to the state decoding table shown in FIG. 201 and a code 204 to be output to the trace status port (PCST) 901 are determined.

  On the other hand, the development support apparatus according to the present embodiment has the same configuration as the development support apparatus shown in FIG. However, the operation of the host computer 3 as the execution history restoring unit is different from the conventional one. This will be described later.

  Next, trace information output and execution history restoration by the semiconductor integrated circuit 1 and the development support apparatus according to the present embodiment will be described by taking the case of executing the program shown in FIG. 21 as an example. In this example, the semiconductor integrated circuit 1 starts program execution and tracing from the address “0x50000000” (execution order “1”), and by the instruction “setlb” at the address “0x50000004” (execution order “2”), the register 150 The branch destination address “0x50000008” of the loop “loop0” is stored in the register 160, and the first instruction “instruction 2” of the loop is stored in the register 160, respectively. Then, after executing the loop twice by the register indirect branch instruction “leq” at the address “0x50000010” (execution order “5” and “8”), the interrupt is accepted during the third loop execution, and the address “0x40000100” Starts execution of the interrupt handler "int0h" (execution order "10"). In the interrupt handler “int0h”, after executing another loop “loop1” with the register indirect branch instruction “lne” twice, return to the previous loop “loop0”, execute the fourth loop, and then execute the same loop. Ends.

  FIG. 22 shows trace information output when the semiconductor integrated circuit 1 executes the program shown in FIG. The trace information shown in FIG. 22 is obtained as a result of the operation of the semiconductor integrated circuit 1 described below. A characteristic part of this embodiment will be described.

  When the CPU 100 executes the instruction “setlb” at the address “0x50000004” (execution order “2”), the LAR update signal 130 is asserted and the LAR update flag signal 601 is asserted, but the signals LCC and JMPTKN are not asserted yet. Therefore, the trace packet control unit 200 outputs “SEQ” as the reference numeral 204 in accordance with the state decoding table shown in FIG. Thereafter, when the register indirect branch instruction “leq” at the address “0x50000010” (execution order “5”) is executed, the LAR update flag signal 601 and the signals LCC and JMPTKN are asserted. At the same time, the address “0x50000008” is output as data 701.

  One cycle after the execution of the register indirect branch instruction “leq” at the address “0x50000010” (execution order “5”), the holding circuit 610 is reset and the LAR update flag signal 601 is negated. Thus, when the CPU 100 executes the register indirect branch instruction “leq” at the address “0x50000010” (execution order “8”), the signals LCC and JMPTKN are asserted, but the LAR update flag signal 601 is negated. In accordance with the state decoding table shown in FIG. 20, only “NPC” is output as the reference numeral 204 from the trace packet control unit 200.

  Similarly, after the CPU 100 accepts the interrupt and executes the branch, and the processing moves to the interrupt handler “int0h”, when the CPU 100 executes the instruction “setlb” at the address “0x40000104” (execution order “11”), Since the LAR update signal 130 is asserted and the LAR update flag signal 601 is asserted, but the signals LCC and JMPTKN are not yet asserted, the trace packet control unit 200 uses the state decode table shown in FIG. "SEQ" is output. Thereafter, when the CPU 100 executes the register indirect branch instruction “lne” at the address “0x40000110” (execution order “14”), this instruction is the first high-speed branch instruction in the loop “loop1”. “JMP” is output, and “0x40000108” is output as data 701. On the other hand, even with the same register indirect branch instruction “lne”, when the execution order is “17”, since the branch condition is not satisfied, the signal JMPTKN is not asserted, and “SEQ” is output as the code 204.

  When the CPU 100 executes the instruction “movm (sp), regs” at the address “0x40000114” (execution order “18”), the LAR update signal 130 is asserted and the LAR update flag signal 601 is asserted. When the CPU 100 executes the register indirect branch instruction “leq” at the address “0x50000010” (execution order “21”), this instruction is not the first register indirect branch instruction in the loop “loop0”, but the LAR update flag Since the signal 601 is asserted and the signals LCC and JMPTKN are asserted, “JMP” is output as the reference numeral 204 and the address “0x50000008” is output as the data 701. After that, when the CPU 100 executes the register indirect branch instruction “leq” in the execution order “24”, the branch condition is not satisfied, and therefore the signal JMPTKN is not asserted and “SEQ” is output as the code 204.

  With the above operation, the trace information shown in FIG. 22 is output from the semiconductor integrated circuit 1 according to the present embodiment.

  On the other hand, FIG. 23 and FIG. 24 are flowcharts of the execution history restoration method executed by the development support apparatus according to the present embodiment. FIG. 25 shows a program execution history restored by the development support apparatus according to the present embodiment. The program execution history shown in FIG. 25 is obtained as a result of execution of the execution history restoring method described below. A characteristic part of this embodiment will be described.

  When TP = 4, the sign shown in the trace information is “JMP” (steps 2007, 2008 and 2017), and the instruction shown in the source program is the register indirect branch instruction “leq” (LCC). (Steps 2018, 2020, and 2022) and the branch destination address “0x50000008” corresponding to TP = 4 indicated in the trace information in the simulated loop address register (hereinafter referred to as software LAR) implemented in software in Step 2023 Is stored. Thereafter, in step 2028, IP is set to the branch destination address “0x50000008” corresponding to TP = 4 indicated in the trace information (IP = 0x50000008), and after TP is incremented in step 2034 (TP = 5), step Return to 2006. The same processing is performed when TP = 14,21.

  On the other hand, when TP = 7, the sign shown in the trace information is “NPC” (steps 2007 and 2008), and the instruction shown in the source program is the register indirect branch instruction “leq” as in TP = 4. Since it is (LCC) (steps 2009 and 2012), in step 2013, IP is set to the branch destination address “0x50000008” stored in the software LAR (IP = 0x50000008). Then, after TP is incremented in Step 2034 (TP = 8), the process returns to Step 2006.

  Through the above processing, the program execution history shown in FIG. 25 is restored by the development support apparatus according to the present embodiment.

  As described above, according to the present embodiment, in the loop processing including the register indirect branch instruction, the branch destination address is output as trace information for the first execution of the register indirect branch instruction, and the second and subsequent register indirect branch instructions are output. For execution, since the branch destination address is not output as trace information, the bandwidth is not compressed for the output of trace information. In other words, the trace information output of the semiconductor integrated circuit that implements the register indirect branch instruction is optimized, and even when the semiconductor integrated circuit is traced by operating under actual operating conditions, the accurate program execution history can be restored. Can do.

(Fourth embodiment)
FIG. 26 shows a configuration of a semiconductor integrated circuit according to the fourth embodiment of the present invention. The semiconductor integrated circuit 1 according to the present embodiment has a configuration in which the synchronization request request generation circuit 800 and the selector 750 described in the second embodiment are added to the semiconductor integrated circuit according to the third embodiment. Hereinafter, a different part compared with the semiconductor integrated circuit which concerns on 2nd and 3rd embodiment is demonstrated.

  The OR circuit 650 in the loop detection circuit 600 calculates a logical sum of the LAR update signal 130 and the synchronization request signal 801, and this logical sum becomes a set signal of the holding circuit 610. That is, when the synchronization request signal 801 is asserted, the LAR update flag signal 601 is asserted until the signals LCC and JMPTKN are next asserted. Note that the timing at which the synchronization request signal 801 is asserted is as described in the second embodiment.

  FIG. 27 shows a state decoding table of the trace packet control unit 200. Compared with the third embodiment, the trace packet control unit 200 according to the present embodiment is added with a synchronization request signal 801 as an input and a selection signal (TPCSEL) 202 as an output. Also, “SYN” and “JMPS” are added as output codes.

  On the other hand, the development support apparatus according to the present embodiment has the same configuration as the development support apparatus shown in FIG. However, the operation of the host computer 3 as the execution history restoring unit is different from the conventional one. This will be described later.

  Next, trace information output and execution history restoration by the semiconductor integrated circuit 1 and the development support apparatus according to the present embodiment will be described taking the case of executing the program shown in FIG. 28 as an example. In this example, the semiconductor integrated circuit 1 starts the trace in the execution order “6” at the second execution of the loop “loop0” four times.

  FIG. 29 shows trace information output when the semiconductor integrated circuit 1 executes the program shown in FIG. The trace information shown in FIG. 29 is obtained as a result of the operation of the semiconductor integrated circuit 1 described below. A characteristic part of this embodiment will be described.

  When the execution order is “6”, tracing is started, the synchronization request signal 801 is asserted, and the LAR update flag signal 601 is asserted. When the CPU 100 executes the instruction “instruction 2” at the address “0x40000008” (execution order “6”), the signal EOI is asserted and the execution address 111 (“0x40000008”) is output. At this time, the signal LCC is not asserted, and according to the state decoding table shown in FIG. 27, the trace packet control unit 200 asserts the signal TPCLDEN, sets the value of the signal TPCSEL to “0”, "Is output. Further, the execution address “0x40000008” at this time is output from the shift register 700 as data 701.

  Thereafter, when the CPU 100 executes the register indirect branch instruction “leq” at the address “0x40000010” (execution order “8”), the signals LCC and JMPTKN are asserted. At this time, the LAR update flag signal 601 is asserted, “JMP” is output as the reference numeral 204, and the branch destination address “0x40000008” is output as the data 701.

  On the other hand, FIGS. 30 and 31 are flowcharts of an execution history restoration method executed by the development support apparatus according to the present embodiment. FIG. 32 shows a program execution history restored by the development support apparatus according to the present embodiment. The program execution history shown in FIG. 32 is obtained as a result of execution of the execution history restoring method described below. A characteristic part of this embodiment will be described.

  When TP = 0, the sign indicated in the trace information is “SYN” (step 2002), so in step 2003, IP is set to the execution address “0x40000008” corresponding to TP = 0 indicated in the trace information. (IP = 0x40000008), the process proceeds to step 2006.

  When TP = 2, the sign indicated in the trace information is “JMP” (steps 2007, 2008 and 2017), and the instruction indicated in the source program is the register indirect branch instruction “leq” (LCC). (Steps 2018, 2020 and 2022) In step 2023, the branch destination address “0x40000008” corresponding to TP = 4 indicated in the trace information is stored in the software LAR. Thereafter, in step 2028, IP is set to the branch destination address “0x40000008” corresponding to TP = 4 indicated in the trace information (IP = 0x40000008), and after TP is incremented in step 2034 (TP = 3), step Return to 2006.

  On the other hand, when TP = 5, the sign shown in the trace information is “NPC” (steps 2007 and 2008), and the instruction shown in the source program is the register indirect branch instruction “leq” as in TP = 2. Since (LCC) (steps 2009 and 2012), in step 2013, the IP is set to the branch destination address “0x40000008” stored in the software LAR (IP = 0x40000008). Then, after TP is incremented in step 2034 (TP = 6), the process returns to step 2006.

  Next, another example of trace information output by the semiconductor integrated circuit 1 according to the present embodiment and execution history restoration by the development support apparatus will be described taking the case of executing the program shown in FIG. In this example, the program itself is the same as the previous example shown in FIG. 28, but the trace starts from the instruction at the address “0x40000010” (execution order “5”) one instruction before the previous example. Yes.

  FIG. 34 shows trace information output when the semiconductor integrated circuit 1 executes the program shown in FIG. The trace information shown in FIG. 34 is obtained as a result of the operation of the semiconductor integrated circuit 1 described below. A characteristic part of this embodiment will be described.

  Unlike the previous example, when TP = 0, the code indicated in the trace information is “JMPS” (steps 2001 and 2002), so that IP corresponds to TP = 0 indicated in the trace information in step 2004. Branch destination address “0x40000008” is set (IP = 0x40000008), TP is incremented in step 2005 (TP = 1), and then the process proceeds to step 2006. The subsequent processing is the same as in the previous example.

  As described above, according to the present embodiment, even when the trace is started after the execution of the program is started, the execution address or the branch destination address at the start of the trace is output, and the trace is performed during the loop processing. When started, when the indirect branch instruction that branches to the top of the loop after the trace starts is executed for the first time, the branch destination address is output. As a result, even when tracing is started in the middle of program execution, the program portion at the start of tracing is restored, and the execution history of the program portion of the loop including the high-speed branch instruction is accurately restored.

(Fifth embodiment)
FIG. 36 shows a configuration of a semiconductor integrated circuit according to the fifth embodiment of the present invention. The semiconductor integrated circuit 1 according to the present embodiment includes a CPU 100, a trace packet control unit 200, a comparator 400, an address register 670, a shift register 700, a selector 750, and a synchronization request generation circuit 800. Among these, the shift register 700, the selector 750, and the synchronization request generation circuit 800 are the same as those in the second embodiment. Hereinafter, the CPU 100, the comparator 400, and the address register 670 will be described.

  The CPU 100 implements an indirect branch instruction that branches to a branch destination address stored in a general-purpose register (not shown) as a high-speed branch instruction. When the branch condition is satisfied and the indirect branch instruction is executed, the CPU 100 asserts signals JMPIND and JMPTKN and outputs the branch destination address 110. Further, when the CPU 100 executes an instruction, the CPU 100 outputs an execution address 111 of the instruction. The other points are the same as in the second embodiment except that some signals are omitted.

  The address register 670 receives the logical product of the signals JMPIND and JMPTKN calculated by the AND circuit 660 as a load signal 661 and the branch destination address 110 output from the CPU 100 as data. That is, the address register 670 outputs the stored address and stores the branch destination address 110 when an indirect branch instruction is executed by the CPU 100. The address register 670 initializes the stored contents when the synchronization request signal 801 is asserted.

  The comparator 400 compares the data 671 output from the address register 670 with the branch destination address 110 output from the CPU 100, and outputs a match / mismatch as a comparison result signal 401. The comparison result signal 401 is asserted when they match and is negated when they do not match.

  FIG. 37 shows a state decoding table of the trace packet control unit 200. The trace packet control unit 200 receives the signals EOI, JMPDIR, JMPIND, JMPTKN and EXP, the comparison result signal 401 and the synchronization request signal 801, and follows the branch destination address load enable signal (TPCLDEN) according to the state decoding table shown in FIG. 201, the selection signal (TPCSEL) 202, and the code | symbol 204 output to the trace status port (PCST) 901 are determined.

  On the other hand, the development support apparatus according to the present embodiment has the same configuration as the development support apparatus shown in FIG. However, the operation of the host computer 3 as the execution history restoring unit is different from the conventional one. This will be described later.

  Next, trace information output and execution history restoration by the semiconductor integrated circuit 1 and the development support apparatus according to the present embodiment will be described by taking the case of executing the program shown in FIG. 38 as an example. In this example, the semiconductor integrated circuit 1 starts the trace in the execution order “6” at the second execution of the loop “loop0” four times.

  FIG. 39 shows trace information output when the semiconductor integrated circuit 1 executes the program shown in FIG. The trace information shown in FIG. 39 is obtained as a result of the operation of the semiconductor integrated circuit 1 described below. A characteristic part of this embodiment will be described.

  When the CPU 100 executes the indirect branch instruction “beq (a0)” at the address “0x40000010” (execution order “5”), the signals JMPIND and JMPTKN are asserted, and the branch destination address 110 (“0x40000008”) is stored in the address register 670. Stored. The instruction “beq (a0)” is an indirect branch instruction that branches to the branch destination address stored in the register “a0” when the condition is satisfied.

  Next, when the execution order is “6”, tracing is started, the synchronization request signal 801 is asserted, and the address register 670 is initialized. When the CPU 100 executes the instruction “instruction 2” at the address “0x40000008” (execution order “6”), the signal EOI is asserted and the execution address 111 (“0x40000008”) is output. At this time, the signals JMPIND and JMPTKN are not asserted, and the trace packet control unit 200 asserts the signal TPCLDEN and sets the value of the signal TPCSEL to “0” according to the state decoding table shown in FIG. Output "SYN". Further, the execution address “0x40000008” of the instruction “instruction 2” in the execution order “6” is output as data 701 from the shift register 700.

  Thereafter, when the CPU 100 executes the indirect branch instruction “beq (a0)” at the address “0x40000010” (execution order “8”), the signals JMPIND and JMPTKN are asserted, and the address stored in the address register 670 and the branch destination Address 110 is compared. Since the address register 670 is initialized at the start of tracing, these addresses do not match and the comparison result signal 401 is not asserted. Accordingly, the trace packet control unit 200 asserts the signal TPCLDEN, sets the value of the signal TPCSEL to “1”, and outputs “JMP” as the reference numeral 204 in accordance with the state decoding table shown in FIG. The shift register 700 outputs the execution address “0x40000008” of the instruction “instruction 2” in the execution order “6” as data 701.

  On the other hand, when the CPU 100 executes the indirect branch instruction “beq (a0)” at the address “0x40000010” (execution order “11”), the signals JMPIND and JMPTKN are asserted, and the address stored in the address register 670 and the branch destination The address 110 “0x40000008” is compared. Since the address register 670 stores the address “0x40000008” by executing the indirect branch instruction “beq (a0)” of the execution order “8”, these two addresses match and the comparison result signal 401 is asserted. The As a result, “NPC” is output as reference numeral 204 in accordance with the state decoding table shown in FIG. At this time, data 701 is not output from the shift register 700.

  With the above operation, the trace information shown in FIG. 39 is output from the semiconductor integrated circuit 1 according to the present embodiment.

  On the other hand, FIGS. 40 and 41 are flowcharts of the execution history restoration method executed by the development support apparatus according to the present embodiment. FIG. 42 shows a program execution history restored by the development support apparatus according to the present embodiment. The program execution history shown in FIG. 42 is obtained as a result of execution of the execution history restoration method described below. A characteristic part of this embodiment will be described.

  When TP = 0, the sign indicated in the trace information is “SYN” (step 2002), so in step 2003, IP is set to the execution address “0x40000008” corresponding to TP = 0 indicated in the trace information. (IP = 0x40000008), the process proceeds to step 2006.

  When TP = 2, the sign shown in the trace information is “JMP” (steps 2007, 2008 and 2017), and the instruction shown in the source program is the indirect branch instruction “beq (a0)” ( The branch destination address “0x40000008” corresponding to TP = 4 indicated in the trace information is stored in the simulation register (hereinafter referred to as “soft register”) realized by software in steps 204, 2020 and 2042) and 2043). The Thereafter, in step 2028, IP is set to the branch destination address “0x40000008” corresponding to TP = 4 indicated in the trace information (IP = 0x40000008), and after TP is incremented in step 2034 (TP = 3), step Return to 2006.

  On the other hand, when TP = 5, the sign shown in the trace information is “NPC” (steps 2007 and 2008), and the instruction shown in the source program is the indirect branch instruction “beq (a0) as in TP = 2. ) "(Steps 2009 and 2040), the IP is set to the branch destination address" 0x40000008 "stored in the soft register in step 2041 (IP = 0x40000008). Then, after TP is incremented in step 2034 (TP = 6), the process returns to step 2006.

  Next, another example of trace information output by the semiconductor integrated circuit 1 according to the present embodiment and execution history restoration by the development support apparatus will be described taking the case of executing the program shown in FIG. In this example, the program itself is the same as the previous example shown in FIG. 38, but the trace starts from the instruction at the address “0x40000010” (execution order “5”) one instruction before the previous example. Yes.

  FIG. 44 shows trace information output when the semiconductor integrated circuit 1 executes the program shown in FIG. The trace information shown in FIG. 44 is obtained as a result of the operation of the semiconductor integrated circuit 1 described below. A characteristic part of this embodiment will be described.

  Unlike the previous example, when TP = 0, the code indicated in the trace information is “JMPS” (steps 2001 and 2002), so that IP corresponds to TP = 0 indicated in the trace information in step 2004. Branch destination address “0x40000008” is set (IP = 0x40000008), TP is incremented in step 2005 (TP = 1), and then the process proceeds to step 2006. The subsequent processing is the same as in the previous example.

  As described above, according to the present embodiment, in the loop processing including the indirect branch instruction, the branch destination address is output as the trace information for the first indirect branch instruction execution, and the second and subsequent indirect branch instruction executions are performed. In this case, since the branch destination address is not output as the trace information, the bandwidth is not compressed with respect to the output of the trace information. In other words, the trace information output of the semiconductor integrated circuit in which the indirect branch instruction is implemented is optimized, and even when the semiconductor integrated circuit is traced by operating under actual operating conditions, an accurate program execution history can be restored. it can.

  Furthermore, even if tracing is started after program execution has started, the execution address or branch destination address at the start of tracing is output, and if tracing is started during loop processing, tracing When the indirect branch instruction that branches to the top of the loop after the start is executed for the first time, the top address of the loop is output. As a result, even when tracing is started in the middle of program execution, the program portion at the start of tracing is restored, and the execution history of the program portion of the loop including the high-speed branch instruction is accurately restored.

  As in the first and third embodiments, the configuration that does not include the synchronization request generation circuit 800 and the selector 750 does not impair the effect of optimizing the output of trace information according to the present invention.

  In addition, the semiconductor integrated circuit according to each of the above embodiments may include an address register that outputs retained data in parallel instead of the shift register 700. Even when the branch destination address is output in parallel, the effect of the present invention is not impaired.

  For convenience of explanation, the development support apparatus according to each of the above embodiments restores the program execution history based on the trace information output from the semiconductor integrated circuit according to each of the above embodiments. It is possible to restore the program execution history based on the trace information output from the integrated circuit.

  The semiconductor integrated circuit and the development support apparatus according to the present invention are useful as means for analyzing and evaluating the operation of the processor from the outside.

1 is a configuration diagram of a semiconductor integrated circuit according to a first embodiment of the present invention. It is a state decoding table of the trace packet control unit in the semiconductor integrated circuit according to the first embodiment of the present invention. It is a figure which shows a program example and execution order. It is a figure which shows the trace information output when the semiconductor integrated circuit which concerns on the 1st Embodiment of this invention runs the program shown in FIG. It is a flowchart of the execution log | history restoration method by the development assistance apparatus which concerns on the 1st Embodiment of this invention. It is a flowchart of the execution history restoration method by the development assistance apparatus which concerns on the 1st Embodiment of this invention. It is a figure which shows the program execution log decompress | restored by the development assistance apparatus which concerns on the 1st Embodiment of this invention. It is a block diagram of the semiconductor integrated circuit which concerns on the 2nd Embodiment of this invention. It is a state decoding table | surface of the trace packet control part in the semiconductor integrated circuit which concerns on the 2nd Embodiment of this invention. It is a figure which shows a program example and execution order. It is a figure which shows the trace information output when the semiconductor integrated circuit which concerns on the 2nd Embodiment of this invention runs the program shown in FIG. It is a flowchart of the execution log restoration method by the development assistance apparatus which concerns on the 2nd Embodiment of this invention. It is a flowchart of the execution log restoration method by the development assistance apparatus which concerns on the 2nd Embodiment of this invention. It is a figure which shows the program execution log | history decompress | restored by the development assistance apparatus which concerns on the 2nd Embodiment of this invention. It is a figure which shows a program example and execution order. FIG. 16 is a diagram showing trace information output when the semiconductor integrated circuit according to the second embodiment of the present invention executes the program shown in FIG. 15. It is a figure which shows the program execution log | history decompress | restored by the development assistance apparatus which concerns on the 2nd Embodiment of this invention. It is a block diagram of the semiconductor integrated circuit which concerns on the 3rd Embodiment of this invention. It is another block diagram of a loop detection circuit. It is a state decoding table | surface of the trace packet control part in the semiconductor integrated circuit which concerns on the 3rd Embodiment of this invention. It is a figure which shows a program example and execution order. It is a figure which shows the trace information output when the semiconductor integrated circuit which concerns on the 3rd Embodiment of this invention runs the program shown in FIG. It is a flowchart of the execution log restoration method by the development assistance apparatus which concerns on the 3rd Embodiment of this invention. It is a flowchart of the execution log restoration method by the development assistance apparatus which concerns on the 3rd Embodiment of this invention. It is a figure which shows the program execution log decompress | restored by the development assistance apparatus which concerns on the 3rd Embodiment of this invention. It is a block diagram of the semiconductor integrated circuit which concerns on the 4th Embodiment of this invention. It is a state decoding table | surface of the trace packet control part in the semiconductor integrated circuit which concerns on the 4th Embodiment of this invention. It is a figure which shows a program example and execution order. It is a figure which shows the trace information output when the semiconductor integrated circuit which concerns on the 4th Embodiment of this invention runs the program shown in FIG. It is a flowchart of the execution log restoration method by the development assistance apparatus which concerns on the 4th Embodiment of this invention. It is a flowchart of the execution log restoration method by the development assistance apparatus which concerns on the 4th Embodiment of this invention. It is a figure which shows the program execution log decompress | restored by the development assistance apparatus which concerns on the 4th Embodiment of this invention. It is a figure which shows a program example and execution order. It is a figure which shows the trace information output when the semiconductor integrated circuit which concerns on the 4th Embodiment of this invention runs the program shown in FIG. It is a figure which shows the program execution log decompress | restored by the development assistance apparatus which concerns on the 4th Embodiment of this invention. It is a block diagram of the semiconductor integrated circuit which concerns on the 5th Embodiment of this invention. It is a state decoding table | surface of the trace packet control part in the semiconductor integrated circuit which concerns on the 5th Embodiment of this invention. It is a figure which shows a program example and execution order. FIG. 39 is a diagram showing trace information output when the semiconductor integrated circuit according to the fifth embodiment of the present invention executes the program shown in FIG. 38. It is a flowchart of the execution log restoration method by the development assistance apparatus which concerns on the 5th Embodiment of this invention. It is a flowchart of the execution log restoration method by the development assistance apparatus which concerns on the 5th Embodiment of this invention. It is a figure which shows the program execution log decompress | restored by the development assistance apparatus which concerns on the 5th Embodiment of this invention. It is a figure which shows a program example and execution order. It is a figure which shows the trace information output when the semiconductor integrated circuit which concerns on the 5th Embodiment of this invention runs the program shown in FIG. It is a figure which shows the program execution log decompress | restored by the development assistance apparatus which concerns on the 5th Embodiment of this invention. It is a block diagram of a semiconductor integrated circuit having a conventional trace information output function. 47 is a state decode table of a trace packet control unit in the semiconductor integrated circuit of FIG. It is a block diagram of a development support apparatus. It is a figure which shows the example of an execution program, and execution order. It is a figure which shows the trace information output by execution of the program of FIG. It is a flowchart of the conventional execution history restoration method. It is a figure which shows the program execution log | history restored | restored based on the trace information of FIG.

Explanation of symbols

1 Semiconductor Integrated Circuit 100 CPU
300 Stack Memory 400 Comparator 200 Trace Packet Control Unit 700 Shift Register (Address Register, Second Address Register)
800 Synchronization request generation circuit 750 Selector 600 Loop detection circuit 610 Holding circuit 620 Reset circuit 670 Address register (first address register)
1030 Trace memory 3 Host computer (execution history restoration unit)

Claims (28)

When the call instruction is executed, the first signal is asserted and the branch destination address and the return destination address related to the call instruction are output. When the interrupt branch is executed, the second signal is asserted and the interrupt branch is set. A CPU that outputs the branch destination address and the return destination address and outputs a branch destination address related to the return instruction while asserting a third signal when the return instruction is executed;
When one of the first and second signals is asserted, the return address output from the CPU is pushed, and when the third signal is asserted, the pushed return address is popped. Stack memory to
A comparator that compares the return destination address popped from the stack memory with the branch destination address output from the CPU;
A trace packet control unit that receives a plurality of signals including the first to third signals from the CPU and outputs a trace state code based on the plurality of signals;
An address register that receives a branch destination address output from the CPU and outputs the address under the control of the trace packet control unit;
The trace packet control unit instructs the address register to output an address when the third signal is asserted and the comparison result received from the comparator indicates a mismatch. The semiconductor integrated circuit according to claim 1,
The trace packet control unit instructs the address register to output an address when the third signal is asserted and an underflow occurs in the stack memory. The semiconductor integrated circuit according to claim 1,
A synchronization request generation circuit for asserting a fourth signal when tracing is started;
The stack memory initializes stored contents when the fourth signal is asserted. A semiconductor integrated circuit, wherein: The semiconductor integrated circuit according to claim 3,
When the CPU executes an instruction, it outputs an execution address of the executed instruction,
The semiconductor integrated circuit is
A selector that selectively outputs one of a branch destination address and an execution address output from the CPU;
The address register receives the address output from the selector instead of the branch destination address output from the CPU, and outputs the address under the control of the trace packet control unit,
The trace packet control unit outputs a code indicating a trace start as a trace status code when the fourth signal is asserted, and further, when the first and second signals are negated, the selector In the semiconductor integrated circuit, the selection of the execution address is instructed, and in other cases, the selector is instructed to select the branch destination address. The semiconductor integrated circuit according to claim 3,
The synchronization request generation circuit asserts the fourth signal at least one of system reset, task switching, and trace start. The semiconductor integrated circuit according to claim 3,
The synchronization request generation circuit asserts the fourth signal when instructed from outside. The semiconductor integrated circuit according to claim 3,
The synchronization request generation circuit asserts the fourth signal at a constant period. A CPU having an indirect branch instruction that branches to a branch destination address stored in a register, asserts a first signal when the register is updated, and outputs a second signal when the indirect branch instruction is executed. CPU that asserts and outputs a branch destination address related to the indirect branch instruction;
A loop detection circuit that asserts a third signal between the assertion of the first signal and the assertion of the second signal;
A trace packet control unit that receives a plurality of signals including the second signal from the CPU and outputs a trace status code based on the plurality of signals;
An address register that receives a branch destination address output from the CPU and outputs the address under the control of the trace packet control unit;
The trace packet control unit instructs the address register to output an address when the second and third signals are asserted. The semiconductor integrated circuit according to claim 8, wherein
The loop detection circuit
A holding circuit for holding the third signal in an asserted state when the first signal is asserted;
And a reset circuit that resets the state held by the holding circuit when the second signal is asserted. The semiconductor integrated circuit according to claim 8, wherein
A synchronization request generation circuit for asserting a fourth signal when tracing is started;
The semiconductor integrated circuit, wherein the loop detection circuit asserts the third signal between the assertion of the fourth signal and the assertion of the second signal. The semiconductor integrated circuit according to claim 10,
When the CPU executes an instruction, it outputs an execution address of the executed instruction,
The semiconductor integrated circuit is
A selector that selectively outputs one of a branch destination address and an execution address output from the CPU;
The address register receives the address output from the selector instead of the branch destination address output from the CPU, and outputs the address under the control of the trace packet control unit,
The trace packet control unit outputs a code indicating a trace start as a trace status code when the fourth signal is asserted, and further, when the second signal is negated, executes the execution to the selector. A semiconductor integrated circuit characterized by instructing selection of an address, and instructing the selector to select the branch destination address at other times. The semiconductor integrated circuit according to claim 10,
The synchronization request generation circuit asserts the fourth signal at least one of system reset, task switching, and trace start. The semiconductor integrated circuit according to claim 10,
The synchronization request generation circuit asserts the fourth signal when instructed from outside. The semiconductor integrated circuit according to claim 10,
The synchronization request generation circuit asserts the fourth signal at a constant period. A CPU having an indirect branch instruction that branches to a branch destination address stored in a register, and when the indirect branch instruction is executed, asserts a first signal and outputs a branch destination address related to the indirect branch instruction CPU,
A first address register that outputs a stored address when the first signal is asserted, and stores a branch destination address output from the CPU;
A comparator that compares the branch destination address output from the first address register with the branch destination address output from the CPU;
A trace packet controller that receives a plurality of signals including the first signal from the CPU and outputs a trace status code based on the plurality of signals;
A second address register that receives the branch destination address output from the CPU and outputs the address under the control of the trace packet control unit;
The trace packet control unit instructs the second address register to output an address when the first signal is asserted and the comparison result received from the comparator indicates a mismatch. Integrated circuit. The semiconductor integrated circuit according to claim 15, wherein
A synchronization request generation circuit that asserts a second signal when tracing is started;
The semiconductor integrated circuit according to claim 1, wherein the first address register initializes stored contents when the second signal is asserted. The semiconductor integrated circuit according to claim 16, wherein
When the CPU executes an instruction, it outputs an execution address of the executed instruction,
The semiconductor integrated circuit is
A selector that selectively outputs one of a branch destination address and an execution address output from the CPU;
The second address register receives the address output from the selector instead of the branch destination address output from the CPU, and outputs the address under the control of the trace packet control unit,
The trace packet control unit outputs a code indicating a trace start as a trace status code when the second signal is asserted, and further, when the first signal is negated, executes the execution to the selector. A semiconductor integrated circuit characterized by instructing selection of an address, and instructing the selector to select the branch destination address at other times. The semiconductor integrated circuit according to claim 16, wherein
The synchronization request generation circuit asserts the second signal at least one of system reset, task switching, and trace start. The semiconductor integrated circuit according to claim 16, wherein
The synchronization request generation circuit asserts the second signal when instructed from the outside. The semiconductor integrated circuit according to claim 16, wherein
The synchronization request generation circuit asserts the second signal at a constant cycle. A trace memory that stores the trace status code and address output from the semiconductor integrated circuit according to claim 1 as trace information;
An execution history restoring unit that restores the execution history of the source program by the CPU while sequentially corresponding the source program executed by the CPU in the semiconductor integrated circuit and the trace information stored in the trace memory;
The execution history restoration unit
When a call instruction is detected from the source program or when a code indicating execution of an interrupt branch is detected from the trace information, a return destination address is obtained from the source program and pushed and branched from the trace information A development support apparatus, wherein a destination address is obtained and restored, and when a return instruction is detected from the source program, the pushed return destination address is popped and restored. A trace memory for storing a trace state code and an address output from the semiconductor integrated circuit according to claim 4 as trace information;
An execution history restoring unit that restores the execution history of the source program by the CPU while sequentially corresponding the source program executed by the CPU in the semiconductor integrated circuit and the trace information stored in the trace memory;
The execution history restoration unit
When a call instruction is detected from the source program or when a code indicating execution of an interrupt branch is detected from the trace information, a return destination address is obtained from the source program and pushed and branched from the trace information Obtain and restore the destination address, and when the return instruction is detected from the source program, the return destination address being pushed is popped and restored, and
When a code indicating a trace start is detected from the trace information, the return destination address being pushed is initialized, and either the execution address or the branch destination address corresponding to the code is obtained from the trace information and restored. Development support device characterized by that. A trace memory that stores the trace status code and address output from the semiconductor integrated circuit according to any one of claims 8 and 15 as trace information;
An execution history restoring unit that restores the execution history of the source program by the CPU while sequentially corresponding the source program executed by the CPU in the semiconductor integrated circuit and the trace information stored in the trace memory;
The execution history restoration unit
When an indirect branch instruction is detected from the source program and a code indicating execution of an indirect branch instruction with a branch destination address is detected from the trace information, the branch destination address is stored and the branch destination address is restored. When the indirect branch instruction is detected from the source program and the code indicating the execution of the indirect branch instruction without the branch destination address is detected from the trace information, the stored branch destination address is restored. Development support device. A trace memory that stores a trace state code and an address output from the semiconductor integrated circuit according to claim 11 as trace information;
An execution history restoring unit that restores the execution history of the source program by the CPU while sequentially corresponding the source program executed by the CPU in the semiconductor integrated circuit and the trace information stored in the trace memory;
The execution history restoration unit
When an indirect branch instruction is detected from the source program and a code indicating execution of an indirect branch instruction with a branch destination address is detected from the trace information, the branch destination address is stored and the branch destination address is restored. When the indirect branch instruction is detected from the source program and the code indicating the execution of the indirect branch instruction without the branch destination address is detected from the trace information, the stored branch destination address is restored. ,And,
When a code indicating a trace start is detected from the trace information, the development support apparatus obtains either the execution address or the branch destination address corresponding to the code from the trace information and restores it. A trace state code and an address are obtained as trace information from the semiconductor integrated circuit according to claim 1, and the source program executed by the CPU in the semiconductor integrated circuit and the trace information are sequentially associated with the source by the CPU. In the method of restoring the program execution history,
Detecting a call instruction from the source program;
Detecting a code indicating execution of an interrupt branch from the trace information;
Detecting a return instruction from the source program;
When one of the call instruction and the code is detected, obtaining and returning a return destination address from the source program; and
When one of the call instruction and code is detected, obtaining and restoring a branch destination address from the trace information; and
And a step of popping and restoring the pushed return destination address when the return instruction is detected. 5. The trace state code and address are obtained as trace information from the semiconductor integrated circuit according to claim 4, and the source program executed by the CPU in the semiconductor integrated circuit and the trace information are sequentially associated with the source by the CPU. In the method of restoring the program execution history,
Detecting a call instruction from the source program;
Detecting a return instruction from the source program;
Detecting a first code indicating execution of an interrupt branch from the trace information;
Detecting a second code indicating a trace start from the trace information;
When one of the call instruction and the first code is detected, obtaining and returning a return destination address from the source program; and
When one of the call instruction and the first code is detected, obtaining and restoring a branch destination address from the trace information; and
Popping and restoring the pushed return destination address when the return instruction is detected; and
Initializing the pushed return address when the second code is detected;
An execution history restoration comprising: obtaining and restoring either an execution address or a branch destination address corresponding to the second code from the trace information when the second code is detected Method. A trace status code and an address are obtained as trace information from the semiconductor integrated circuit according to any one of claims 8 and 15, and a source program executed by a CPU in the semiconductor integrated circuit and the trace information are sequentially associated with each other. However, in the method of restoring the execution history of the source program by the CPU,
Detecting an indirect branch instruction from the source program;
Detecting a first code indicating execution of an indirect branch instruction with a branch destination address from the trace information;
Detecting a second code indicating execution of an indirect branch instruction without a branch destination address from the trace information;
Storing the branch destination address associated with the first code when the indirect branch instruction and the first code are detected;
Restoring the branch destination address associated with the first code when the indirect branch instruction and the first code are detected;
An execution history restoring method comprising: restoring the stored branch destination address when the indirect branch instruction and the second code are detected. A trace state code and an address are obtained as trace information from the semiconductor integrated circuit according to claim 11, and a source program executed by a CPU in the semiconductor integrated circuit and the trace information are sequentially associated with each other. However, in the method of restoring the execution history of the source program by the CPU,
Detecting an indirect branch instruction from the source program;
Detecting a first code indicating execution of an indirect branch instruction with a branch destination address from the trace information;
Detecting a second code indicating execution of an indirect branch instruction without a branch destination address from the trace information;
Detecting a third code indicating a trace start from the trace information;
Storing the branch destination address associated with the first code when the indirect branch instruction and the first code are detected;
Restoring the branch destination address associated with the first code when the indirect branch instruction and the first code are detected;
Restoring the stored branch destination address when the indirect branch instruction and the second code are detected;
An execution history restoration comprising: a step of obtaining and restoring either an execution address or a branch destination address corresponding to the third code from the trace information when the third code is detected Method.

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