JP2005208837A - レイアウト検証装置 - Google Patents

レイアウト検証装置 Download PDF

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Publication number
JP2005208837A
JP2005208837A JP2004013387A JP2004013387A JP2005208837A JP 2005208837 A JP2005208837 A JP 2005208837A JP 2004013387 A JP2004013387 A JP 2004013387A JP 2004013387 A JP2004013387 A JP 2004013387A JP 2005208837 A JP2005208837 A JP 2005208837A
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JP
Japan
Prior art keywords
layout
region
verification
information
resistance
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JP2004013387A
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English (en)
Japanese (ja)
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JP2005208837A5 (enExample
Inventor
Takao Sato
貴雄 佐藤
Masanori Kanehama
正典 金浜
Tetsuya Murayama
哲也 村山
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Renesas Technology Corp
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Renesas Technology Corp
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Priority to JP2004013387A priority Critical patent/JP2005208837A/ja
Publication of JP2005208837A publication Critical patent/JP2005208837A/ja
Publication of JP2005208837A5 publication Critical patent/JP2005208837A5/ja
Pending legal-status Critical Current

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JP2004013387A 2004-01-21 2004-01-21 レイアウト検証装置 Pending JP2005208837A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2004013387A JP2005208837A (ja) 2004-01-21 2004-01-21 レイアウト検証装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004013387A JP2005208837A (ja) 2004-01-21 2004-01-21 レイアウト検証装置

Publications (2)

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JP2005208837A true JP2005208837A (ja) 2005-08-04
JP2005208837A5 JP2005208837A5 (enExample) 2006-09-07

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ID=34899463

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JP2004013387A Pending JP2005208837A (ja) 2004-01-21 2004-01-21 レイアウト検証装置

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JP (1) JP2005208837A (enExample)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008009964A (ja) * 2006-05-31 2008-01-17 Toshiba Corp 半導体集積回路のレイアウト作成装置及び作成方法
JP2008097541A (ja) * 2006-10-16 2008-04-24 Renesas Technology Corp レイアウト検証方法およびレイアウト検証装置
JP2009069884A (ja) * 2007-09-10 2009-04-02 Toshiba Corp 情報処理装置、電源系統ツリー作成方法およびプログラム
JP2009194315A (ja) * 2008-02-18 2009-08-27 Nec Electronics Corp レイアウト検証装置及びレイアウト検証方法
EP2226736A1 (en) 2009-03-06 2010-09-08 Fujitsu Semiconductor Limited Layout verification method
CN114186525A (zh) * 2021-12-15 2022-03-15 四川创安微电子有限公司 一种mos耐压及漏电流验证方法、系统和计算机终端
JP2023080408A (ja) * 2021-11-30 2023-06-09 エイブリック株式会社 レイアウト設計支援装置、レイアウト設計支援方法、レイアウト設計支援装置及び半導体装置の製造方法
KR102686725B1 (ko) * 2023-10-06 2024-07-19 위더맥스(주) 소자 영역간 전압차에 따른 반도체 레이아웃 drc 검증 장치 및 방법

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008009964A (ja) * 2006-05-31 2008-01-17 Toshiba Corp 半導体集積回路のレイアウト作成装置及び作成方法
JP2008097541A (ja) * 2006-10-16 2008-04-24 Renesas Technology Corp レイアウト検証方法およびレイアウト検証装置
JP2009069884A (ja) * 2007-09-10 2009-04-02 Toshiba Corp 情報処理装置、電源系統ツリー作成方法およびプログラム
JP2009194315A (ja) * 2008-02-18 2009-08-27 Nec Electronics Corp レイアウト検証装置及びレイアウト検証方法
EP2226736A1 (en) 2009-03-06 2010-09-08 Fujitsu Semiconductor Limited Layout verification method
JP2023080408A (ja) * 2021-11-30 2023-06-09 エイブリック株式会社 レイアウト設計支援装置、レイアウト設計支援方法、レイアウト設計支援装置及び半導体装置の製造方法
JP7696283B2 (ja) 2021-11-30 2025-06-20 エイブリック株式会社 レイアウト設計支援装置、レイアウト設計支援方法、レイアウト設計支援装置及び半導体装置の製造方法
CN114186525A (zh) * 2021-12-15 2022-03-15 四川创安微电子有限公司 一种mos耐压及漏电流验证方法、系统和计算机终端
KR102686725B1 (ko) * 2023-10-06 2024-07-19 위더맥스(주) 소자 영역간 전압차에 따른 반도체 레이아웃 drc 검증 장치 및 방법

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