JP2005208696A - Delay time display method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a delay time display method that helps efficient measures against delay time violating connection paths. <P>SOLUTION: The delay time display method for, by means of a computer device, displaying delay times of a plurality of signal paths included in a logic circuit diagram on a display part includes a process of specifying the start point and end point of a signal path whose delay time should be displayed in the signal paths, a process of acquiring the delay time of the signal path from the start point to the end point thus specified, and a display process of displaying a sequential circuit at the specified start point, a sequential circuit at the specified end point, a connection line from the start point to the end point, and the delay time acquired about the start point and end point, independently of the circuit diagram, as keeping not displayed combinational circuits in the signal path from the start point to the end point specified. The displayed objects such as the start point and end point are selected ones, so that the logic circuit designer can display only the connection line and delay time connected with the start and end points to be analyzed in the entire logic circuit. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a delay time calculation result display method in logic circuit design, and more particularly to a delay time calculation result display method that is effective when applied to the design of a large-scale logic circuit using an electronic computer.

  As logic circuits become larger and more complex, it has become very difficult to design a logic circuit to satisfy a target delay time. In order to design a high-performance logic circuit, the delay time of a large number of connection paths must be within the target delay time, and a great deal of man-hours are spent on optimizing the delay time for the logic design results. Yes. By automatic processing using an electronic computer, it is possible to design the delay time of a connection path up to a certain extent to be within the target delay time. However, in reality, the delay time of all the connection routes cannot be kept within the target delay time at one time, and the logic circuit designer must analyze the calculation result of the delay time and take measures to deal with the delay time violation connection route. It is essential.

  For countermeasures against the delay time violation connection path, it is necessary to frequently grasp the status of the entire logic circuit and acquire detailed information on the delay time violation connection path, and the conventional method for displaying the delay time calculation result is sufficient in this respect. There has been a problem that no consideration has been made and it has been impossible to efficiently take measures against a delay time violation connection path. In order to efficiently take measures against this delay time violation connection path, an interactive delay time calculation result display method using a graphical user interface (hereinafter referred to as GUI) is used.

  As a delay time calculation result display method using a conventional GUI, there is a delay time display method disclosed in Patent Document 1. The display screen is composed of a first window that displays a path delay time list of a combination of a start point and an end point of a path, and a second window that displays a cell delay time list of each cell corresponding to the path of the path. By selecting a path in one window, the details of the corresponding path are displayed in the second window so that the status of the entire logical block can be grasped and detailed information on the delay time violation path can be easily obtained. is there.

JP 2002-366605 A

  The present inventor has studied a method for displaying a delay time calculation result when optimizing the delay time. According to this, when taking measures against a delay time violation connection route, detailed information on the start and end points such as the clock type and the external delay time of the start point and the end point, the end point having a connection relationship with the start point, the start point having a connection relationship with the end point, etc. It is necessary to obtain frequently. Also, the logic designer must find the abnormal part of the delay time violation connection path. When the number of delay time violation connection paths is enormous, the logic circuit designer must analyze all connection paths. The conventional delay time calculation result display method does not give sufficient consideration to this point, and there is a problem that it is not possible to efficiently take measures against a delay time violation connection path.

  The object of the present invention is to easily grasp the status of the entire logic circuit and to acquire detailed information on the delay time violation connection path and the start and end points, and contribute to improving the efficiency of the delay time violation connection path. The purpose is to propose a delay time display method.

  Another object of the present invention is to propose a delay time display method capable of easily finding an abnormal part of a delay time violation connection path and contributing to the efficiency of measures for the delay time violation connection path. It is in.

  Still another object of the present invention is to reduce the number of start and end points and the number of connection paths that must be analyzed by a logic circuit designer, and a delay time that can contribute to the efficiency of measures against a delay time violation connection path. It is to propose a display method.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  A delay time display method according to the present invention is a delay time display method for displaying delay times of a plurality of signal paths included in a logic circuit diagram on a display unit using a computer device having a display unit, A process for designating a start point and an end point of a signal path for which a delay time is to be displayed; a process for obtaining a delay time of a signal path from the designated start point to the end point; and a signal path from the designated start point to the end point The combinational circuit is not displayed, the designated start point sequential circuit, the designated end point sequential circuit, the connection line from the start point to the end point, and the delay time acquired corresponding to the start point and the end point. Display processing independent of the circuit diagram.

  From the above, when displaying the calculation result of the delay time, since the delay time is displayed on the connection line when displaying the connection line, the start point and the end point on the first window, the logic circuit designer grasps the situation of the entire logic circuit. It can be done easily. Since the display target such as the start point and the end point is selected, the logic circuit designer can display only the connection line and delay time that are connected to the start point or end point to be analyzed in the entire logic circuit. it can.

  As a specific form of the present invention, the target delay time, violation delay time, and logical stage number of the corresponding connection path may be displayed together with the delay time. Thereby, the logic circuit designer can easily find the abnormal part.

  As a more specific form of the present invention, by selecting the start point or the end point in the first window displaying the connection line, the start point and the end point, the corresponding start point or end point clock type, external delay time, maximum violation time Is displayed. Thereby, the logic circuit designer can easily acquire detailed information on the start and end points of the delay time violation connection path.

  As another specific form of the present invention, the delay time violation start / end point is highlighted in the first window displaying the connection line, the start point and the end point, or the start / end point display colors other than the delay time violation start / end point are displayed. make it thin. As a result, the number of start and end points that must be analyzed by the logic circuit designer can be reduced.

  As yet another specific form of the present invention, the delay time violation connection line is highlighted in the first window displaying the connection line, the start point and the end point, or the display color of the connection line other than the delay time violation connection line Thin out. As a result, the number of connection paths that must be analyzed by the logic circuit designer can be reduced, and abnormal parts can be easily found.

  In another aspect of the invention, the first window is configured to include a first window that displays a connection line, a start point, and an end point, and a second window that displays each logic gate included in the connection path and their delay time. By selecting the connection line at, the details of the corresponding connection path are displayed in the second window. Thereby, the logic circuit designer can easily acquire detailed information on the delay time violation connection path.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  According to the present invention, it is possible to easily grasp the status of the entire logic circuit and acquire detailed information on the delay time violation connection line, and to efficiently take measures against the delay time violation portion.

  FIG. 2 generally shows a method for designing a semiconductor integrated circuit. Functional design is performed according to the design specifications (S1). In the subsequent logic design (S2), a specific logic configuration for realizing the function designed is designed. The logical design is performed using, for example, HDL (Hardware Description Language). The logic design result by HDL or the like is logically synthesized, whereby circuit diagram data is generated and can be displayed as a circuit diagram (S3). Based on the logic-synthesized circuit diagram and the like, optimization for the delay time of the signal path and the like is performed (S4). In the delay time optimization process, the signal path of interest and the delay time of the signal path are displayed (S5). As will be described later, the display can easily grasp the status of the entire logic circuit and acquire detailed information on the delay time violation connection line, and can efficiently take measures against the delay time violation point. It is said. The target signal path displayed in such a display form and its delay time are referred to, and the delay time of the signal path is optimized. After optimization for the logic synthesis result, layout design is performed (S6).

  FIG. 3 illustrates a computer device used in the design method. The computer apparatus 1 is realized by a computer apparatus such as an engineering workstation, and performs processing such as logic design, logic synthesis, and delay time display described with reference to FIG. The computer device 1 includes a display 2 as a display device, an input device 3 such as a keyboard and a mouse, and an auxiliary memory for storing a netlist 4A, a design constraint 4B, a cell library 4C, a logic design file 4D, a logic synthesis file 4E, and the like. A device 4 is connected. The logic design file 4D includes logic design data of the semiconductor integrated circuit described in HDL. The cell library 4C includes transistor circuit configuration information of various logic gates such as NAND gates and performance information such as driving power. The netlist 4A includes connection information of the semiconductor integrated circuit. The design constraint 4B includes performance constraints such as circuit operation speed and allowable operation delay. The result of logic synthesis is stored in the logic synthesis file 4E.

  When the computer apparatus 1 performs processing such as optimization (S4) and delay time display (S5) of the logic synthesis result in the design flow of the semiconductor integrated circuit, it reads the necessary logic synthesis result from the logic synthesis file 4E, and designs it. The signal path delay time is calculated based on the circuit performance information of the constraint 4B and the cell library 4C. The signal path delay time must be optimized to be within the target delay time. For this purpose, the logic circuit designer analyzes the calculation result of the delay time, and performs a process for dealing with the delay time violation connection path. As countermeasures for the delay time violation connection path, it is necessary to grasp the status of the entire logic circuit and acquire detailed information on the delay time violation connection path. In the delay time display process (S5), for example, a process for designating the start point and the end point of the signal path for displaying the delay time in the signal path of interest by interactive processing using GUI, and from the designated start point to the end point. A process for obtaining a delay time of the signal path to reach, and a combinational circuit in the signal path from the specified start point to the end point is hidden, the sequential circuit of the specified start point, the sequential circuit of the specified end point, A display process for displaying the connection line from the start point to the end point and the delay time acquired corresponding to the start point and the end point independently of the circuit diagram is performed. Details of the delay time display process will be described below.

  FIG. 1 shows an example of a display form by the delay time display process. A main window 100 is displayed on the display 2. The main window 100 includes a first window 101 and a second window 102. The first window 101 displays the delay time on the start point, end point and connection path (defined by the combination of the start point and end point) included in the logic circuit to be designed. The second window 102 displays all the logic gates constituting at least one selected connection path among the connection paths displayed in the first window 101.

  Here, the logic circuit obtained by logic synthesis (S3) is, for example, the logic circuit shown in FIG. The logic circuit of FIG. 4 includes flip-flops 801 to 804, an external input port 805, an external output port 806, and logic gates 807 to 819. It is assumed that the delay times of all connection paths are calculated in advance using the computer apparatus 1 and the calculated delay times of the connection paths are stored in the storage device of the computer apparatus 1. Here, all the connection paths are the flip-flops 801 (A), 802 (B), 803 (C) and the external input port 805 (D), and the flip-flops 804 (E) and the external output port 806 (F ) Are all connection paths existing as end points. Specifically, a connection path from the start point A to the end point E passes through the logic gate 811, the logic gate 815, and the logic gate 818, and a connection that passes through the logic gate 807, the logic gate 811, the logic gate 815, and the logic gate 818. Path, connection path passing through logic gate 807, logic gate 812, logic gate 815, and logic gate 818, and connection path passing through logic gate 807, logic gate 812, logic gate 816, and logic gate 818, starting point B From the start point C to the end point E, the start point C to the end point E is also the same, the start point C to the end point F is also the same, the start point D to the end point F is also the same, and there are 14 connection routes in total. Exists. In the example of FIG. 1, only the most critical connection route and its delay time among the start and end points and the connection route are displayed. The delay time 113 of the connection path 112, that is, the connection path from the start point A to the end point E is 3.0.

  According to the example shown in FIG. 1, when the logic circuit designer displays the delay time on the screen displaying all the logic gates and connection paths shown in FIG. 10 in the window 101 displaying the start and end points and the connection paths. In contrast, the number of logic gates and start / end points to be displayed is reduced from 19 to 6, and the number of connection paths is reduced from 14 to 5, so that the entire logic circuit can be easily grasped.

  5A and 5B show another example of the display form in the first window 101 by the delay time display process. 5A and 5B display only the start and end points in the first window, do not display the connection line, and when the operator selects the start point or end point, the route passing through the selected start point or end point is displayed. The connection line and the delay time are displayed.

  Since the logic circuit designer can display only the connection path that passes through the selected start point by selecting the start point for taking measures against the delay time in the window 101 displaying only the start and end points, the delay time violation can be efficiently performed. It is possible to take measures against the connection path. Here, as a method of selecting the start point, a known method such as a method of clicking the start point displayed using the mouse cursor or a method of selecting the enter point by moving the cursor up and down using the keyboard is used. Can do. According to the example shown in FIG. 5A, when the start point 203 is clicked, the connection route 207 and the connection route 208 passing through the start point 203 are displayed, and it can be seen that the start point 203 affects the end point 205 and the end point 206.

  In the display form of FIG. 5B, the logic circuit designer can display only the connection route passing through the selected end point by selecting the end point for which the countermeasure for the delay time is taken in the window 101 displaying only the start and end points. Therefore, it is possible to efficiently take countermeasures for the delay time violation connection path. According to the example shown in FIG. 5B, when the end point 205 is clicked, the connection route 209, the connection route 210, and the connection route 207 that pass through the end point 205 are displayed, and the end point 205 affects the start point 201, the start point 202, and the start point 203. I understand.

  FIG. 6 shows still another example of the display form in the first window 101 by the delay time display process. In the display form shown in FIG. 6, only the start and end points and connection lines are displayed in the first window, and at least one of the target delay time, violation delay time, and logic stage number between the start and end points of the selected connection line is displayed. Or one of them is displayed.

  According to the example shown in FIG. 6, the logic circuit designer selects the connection path for which the countermeasure for the delay time is taken in the window 101 that displays the start and end points and the connection path, so that the target delay time 308 of the selected connection path 307 is selected. The violation delay time 309 and the number of logical stages 310 are displayed. This allows the logic circuit designer to understand the ratio of the number of logic stages to the target delay time and violation delay time of the connection path, and makes it easier to examine countermeasures for the delay time violation connection path. It is possible to take measures against the connection path. According to the example shown in FIG. 6, the target delay time of the connection path 307 is 3.0, the violation delay time is 0.5, and the number of logic stages is 7. Therefore, the logic circuit designer sets the number of logic stages of the violation path to one stage. It can be seen that compression corresponding to the minute is sufficient.

  FIG. 7 shows still another example of the display form in the first window 101 and the second window 102 by the delay time display process. In the display form shown in FIG. 7, only the start and end points and connection lines are displayed in the first window, and all the logic gates and delay times constituting the signal path indicated by the selected connection line are displayed in the second window. It is characterized by displaying.

  According to the example shown in FIG. 7, the logic circuit designer configures the selected connection path 401 by selecting a connection path for taking a countermeasure for the delay time in the first window 101 displaying the start and end points and the connection path. In order to display all the logic gates to be displayed, the second window 102 is newly opened, and the details of the corresponding connection path are displayed in the second window 102. As a result, the details of the connection path can be viewed, and the countermeasure against the delay time violation connection path can be efficiently taken. According to the example shown in FIG. 7, when a connection path 401 that requires countermeasures for delay time is clicked, details of the logic gates constituting the connection path 401 are displayed in the window 102. As a result, the logic circuit designer knows that the logic gate having the long delay time is the logic gate 109, and that the countermeasure for the connection path 401 should be a countermeasure around the logic gate 109.

  8A and 8B show still another example of the display form in the first window 101 by the delay time display process. 8A and 8B display only the start and end points and connection lines in the first window, and when the operator selects the start or end point, the clock type and external delay of the selected start or end point are displayed. At least one of time and maximum violation delay time is displayed.

  According to the example shown in FIG. 8A, the logic circuit designer selects the start point or the end point clock type selected by selecting the start point or the end point for which the countermeasure for the delay time is taken in the window 101 displaying the start and end points and the connection path, Since the external delay time and the maximum violation time can be displayed, the delay time violation connection route can be efficiently taken. According to the example shown in FIG. 8A, the logic circuit designer can display the clock type 501, the external delay time 502, and the maximum violation time 503 by selecting the start point 504. According to the example shown in FIG. 8B, the logic circuit designer can display the clock type 506, the external delay time 507, and the maximum violation time 508 by selecting the end point 505.

  FIG. 9 shows still another example of the display form in the first window 101 by the delay time display process. The display form shown in FIG. 9 displays only the start and end points and connection lines in the first window, and distinguishes and displays the start and end points that violate the delay time and the start and end points that do not violate the delay time. It is characterized by doing. When the logic circuit designer identifies the start and end points of the violation of the delay time in the window 101 displaying the start and end points and the connection path, if the start and end points of the logic circuit reach a huge number, all the start and end points must be analyzed. It requires a lot of man-hours for countermeasures against the delay time violation route. In such a case, since the start and end points of the delay time violation can be determined instantaneously by the display method of the present invention, it is possible to efficiently take measures against the delay time violation connection path. As a display method, it is only necessary to be able to display the start and end points in an identifiable manner, such as highlighting the start and end points of the delay time violation or reducing the display color of the start and end points other than the start and end points of the delay time violation. According to the example shown in FIG. 9, the logic circuit designer can instantly determine that the start point 601, start point 602, end point 603, and end point 604 are the start and end points of the delay time violation, and efficiently take measures against the delay time violation connection path. It is possible.

  FIG. 10 shows still another example of the display form in the first window 101 by the delay time display process. In the display form shown in FIG. 10, only the start and end points and connection lines are displayed in the first window, and the connection lines that violate the delay time and the connection lines that do not violate the delay time are distinguished and displayed. It is characterized by doing. When a logic circuit designer identifies a delay time violation connection path in the window 101 displaying the start and end points and the connection path, if the connection path of the logic circuit reaches a large number, all the connection paths must be analyzed. In other words, it takes a lot of man-hours to deal with the delay time violation route. In such a case, since the delay time violation connection path can be determined instantaneously by the display method of the present invention, it is possible to efficiently take measures against the delay time violation connection path. As a display method, it is only necessary to display the connection route in an identifiable manner, such as highlighting the delay time violation connection route or reducing the display color of connection lines other than the delay time violation connection route. According to the example shown in FIG. 10, the logic circuit designer can instantly determine that the connection path 701 and the connection path 702 are delay time violation connection paths, and can efficiently take measures against the delay time violation connection paths. is there.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof. For example, the logic circuit that is the target of delay time display or development is not limited to that shown in FIG. 4, but can be an appropriate logic configuration.

It is explanatory drawing which shows an example of the display form by the delay time display method which concerns on this invention. 3 is a flowchart showing an overall design method of a semiconductor integrated circuit. It is a block diagram which shows an example of the computer apparatus used for the design method of FIG. 3 is a logic circuit diagram illustrating the configuration of a logic circuit obtained by logic synthesis processing. FIG. It is explanatory drawing which shows another example of the display form in the 1st window by a delay time display method. It is explanatory drawing which shows another example of the display form in the 1st window by a delay time display method. It is explanatory drawing which shows another example of the display form in the 1st window by a delay time display method. It is explanatory drawing which shows another example of the display form in the 1st window and 2nd window by a delay time display method. It is explanatory drawing which shows another example of the display form in the 1st window by a delay time display method. It is explanatory drawing which shows another example of the display form in the 1st window by a delay time display method. It is explanatory drawing which shows another example of the display form in the 1st window by a delay time display method. It is explanatory drawing which shows another example of the display form in the 1st window by a delay time display method.

Explanation of symbols

100 Main window 101 First window 102 Second window 112, 207-210, 307 Connection path 113 Delay time 308 Target delay time 309 Violation delay time 310 Number of logical stages 401 Selected connection path 501, 506 Clock type 502, 507 External Delay time 503,508 Maximum violation time 504 Selected start point 505 Selected end point 601, 602 Highlighted start point 603, 604 Highlighted end point 701, 702 Highlighted connection route

Claims (1)

A delay time display method for displaying delay times of a plurality of signal paths included in a logic circuit diagram on a display unit using a computer device having a display unit,
A process for designating a start point and an end point of a signal path for which a delay time is to be displayed in the signal path;
Processing for obtaining a delay time of a signal path from the designated start point to the end point;
The combinational circuit in the signal path from the specified start point to the end point is hidden, the specified start point sequential circuit, the specified end point sequence circuit, the connection line from the start point to the end point, and the start point And a display process for displaying the delay time acquired corresponding to the end point independently of the circuit diagram.

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