JP2005204050A - Circuit for detecting known signal section - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a circuit for detecting known signal section whose detection accuracy is improved. <P>SOLUTION: A DFT part 36 executes discrete Fourier transformation of a detection signal obtained; by detecting a received signal for a specified period shorter than a known signal section in a received signal at each timing point. An intensity acquiring part 38 acquires the intensity of a component, corresponding to the frequency of variation in symbol value in a known signal section, in the output from the DFT part 36. A known signal section acquiring part 40 acquires the known signal section of the received signal, based on the intensity obtained with a plurality of timings. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a circuit for detecting a known signal section such as a preamble included in a received signal.

  In order to synchronize the apparatus reference timing for symbol reproduction etc. with the received signal, a technique for detecting a known signal section using DFT (Discrete Fourier Transform) has been proposed (for example, Non-Patent Document 1). In this method, a DFT is applied to a detection signal obtained by detecting a received signal, and a period in which the intensity of a specific frequency component (a frequency component corresponding to a change in a symbol value in a known signal section) is high is determined based on the DFT result. A preamble is detected, and an error in symbol reproduction timing with respect to the received signal is detected from the preamble.

Yung-Liang Huang, Kong-Dar Fan, Chia-Chi Huang, A Fully Digital Noncoherent and Coherent GMSK Receiver Archetecture with Joint Symbol Timing Error and Frequency Offset Estimation, IEEE Transactions on vehicular technology, May 2000, Vol. 49, pp .863-874.

  However, in the above method, when the intensity of the set frequency component is accidentally increased during reception of noise or data other than the preamble, the period is erroneously detected as a preamble, and errors such as timing may occur. There is a problem that it is difficult to perform correction with high accuracy. In that case, it becomes difficult to correctly reproduce the symbols.

  A known signal section detection circuit according to the present invention performs a discrete Fourier transform on a detection signal obtained by detecting a received signal at each timing for a predetermined period shorter than the known signal section in the received signal. Obtained at a plurality of timings, a discrete Fourier transform unit, an intensity acquisition unit that obtains the intensity of the component corresponding to the frequency of the change of the symbol value in the known signal section of the output from the discrete Fourier transform unit at each timing. A known signal section obtaining unit for obtaining a known signal section of the received signal based on the obtained intensity.

  In the known signal section detection circuit according to the present invention, the known signal section acquisition unit calculates a period corresponding to the timing when the intensity is equal to or exceeds a predetermined threshold at a predetermined number of consecutive times. It is preferable to use the known signal section.

  In the known signal section detection circuit according to the present invention, the known signal section acquisition unit detects the timing when the intensity is equal to or exceeds a predetermined threshold at a predetermined number of times or more within a predetermined period. It is preferable that the period corresponding to is a known signal section.

  In the known signal section detection circuit according to the present invention described above, at each timing, a component having a frequency different from a component corresponding to the frequency of the change in the symbol value in the known signal section of the output from the discrete Fourier transform unit. A second intensity acquisition unit for acquiring an intensity; and the known signal section acquisition unit further detects a known signal section of the received signal based on the intensity obtained at a plurality of timings in the second intensity acquisition unit. It is preferable to do this.

  In the known signal section detection circuit according to the present invention, at least a part of the known signal section detection circuit operates at a timing other than the reception period of the known signal section based on the detection result of the known signal section acquisition unit. It is preferred to be stopped.

  In the known signal section detection circuit according to the present invention, it is preferable that the operation of at least a part of the known signal section detection circuit is stopped at the timing of the data section in the received signal.

  In the known signal section detection circuit according to the present invention, it is preferable that the intensity acquisition unit acquires the intensity as the sum of the absolute value of the in-phase component and the absolute value of the quadrature component of the discrete Fourier transform.

  In the known signal section detection circuit according to the present invention, the average value acquisition unit that acquires the average value of the detection signal for a predetermined period shorter than the known signal section in the received signal, and the average value acquisition unit A difference obtaining unit that obtains a difference value between the average value obtained and the average value obtained previously by a predetermined number of timings, and receives based on the magnitude of the difference value obtained by the difference obtaining unit It is preferable to detect a known signal section of the signal.

  An error detection circuit according to the present invention includes a known signal section detection circuit according to the present invention and a timing error detection unit that detects an error in a device reference timing with respect to a received signal based on an output signal from the discrete Fourier transform unit. And comprising.

  In the error detection circuit according to the present invention, it is preferable that the timing error detection unit outputs, as a detection result, an error with respect to the received signal at the device reference timing acquired at a predetermined timing within the detected known signal section. is there.

  In the error detection circuit according to the present invention, the timing error detection unit includes a shift register, and sequentially stores timing errors acquired at each timing when the intensity exceeds a threshold value in the shift register. When is detected, it is preferable to output the timing error stored in a predetermined stage of the shift register as a detection result.

In the error detection circuit according to the present invention, the timing error detection unit includes a phase error θ (= tan ⁻¹ (Im) obtained from the in-phase component Re and the quadrature component Im in the discrete Fourier transform result obtained by the discrete Fourier transform unit. It is preferable to output a timing error corresponding to / Re)) as a detection result.

  The receiving apparatus according to the present invention is a receiving apparatus that corrects the apparatus reference timing based on the timing error detected by the error detection circuit according to the present invention, and the known signal section is acquired by the known signal section acquisition unit. When detected, the apparatus reference timing is corrected.

  A receiving apparatus according to the present invention is a receiving apparatus that detects a received signal to generate a detected signal, and is based on the known signal section detected by the known signal section detecting circuit, and receives the non-received period of the received signal. A non-reception period predicting unit that predicts the operation, and stops at least some of the operations of the receiving apparatus in the non-reception period.

  Preferred embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram illustrating an example of a receiving device 10 according to the present embodiment, and FIG. 2 illustrates an example of an integrated block 24 (including a known signal section detecting unit 26 and an error detecting unit 28) included in the receiving device 10. FIG. 8 is a block diagram showing another example of the receiving device 10 (10a), and FIG. 9 is a block diagram showing another example of the integrated block 24 (24a).

  In the example of FIG. 1, the RF signal received by the antenna 12 is subjected to processing such as amplification, filtering, and frequency conversion by the RF processing circuit 14 to become an IF signal.

  The IF signal is filtered by the IF filter 16 and then input to the detection unit 18. The detection signal output from the detection unit 18 is sent to the symbol acquisition unit 22, where each symbol is acquired.

  The detection unit 18 performs detection according to the signal demodulation method. As an example, when the signal is digitally modulated by GMSK or GFSK, the detector 18 can be configured as a discriminator detector. As another example, when the signal is digitally modulated by PSK or QAM, the detection unit can be configured as a quadrature detection unit.

  Further, the symbol acquisition unit 22 acquires (samples) a detection signal at the symbol reproduction timing based on the apparatus, and based on the comparison result between the value and a predetermined threshold value, the bit (H / L or 1/0) of each symbol. ) Is acquired. Instead of acquiring the symbol directly from the detection signal, the symbol may be acquired after performing some kind of preprocessing (for example, thinning processing).

  The device reference timing and the predetermined threshold value in the symbol acquisition unit 22 are corrected in the correction unit 20. These corrections are performed so as to eliminate various errors acquired by the integrated block 24 for detecting known signals and errors. The integrated block 24 includes a known signal section detection unit 26 and an error detection unit 28. These configuration examples will be described in detail later.

  Further, the receiving apparatus 10 of FIG. 1 includes power control units 30 and 32 and a non-reception period predicting unit 34, which are configured to control the power supply of each unit of the apparatus. These operations will be described in detail later.

  Now, the known signal section detector 26 shown as an example in FIG. 2 includes a discrete Fourier transform section (hereinafter simply referred to as a DFT section) 36, an intensity acquisition section 38, and a known signal section acquisition section 40. In the following description, the receiving apparatus 10 according to the present embodiment is applied to an automatic identification system (AIS) for ships.

  FIG. 3 is a diagram illustrating a configuration example of one slot of the AIS packet 50. In the example of FIG. 3, one slot is composed of a total of 256 symbols (256 bits), and the breakdown is as follows: ramp up: 8 symbols, training sequence: 24 symbols, start flag: 8 symbols, data: 168 symbols, CRC : 16 symbols, end flag: 8 symbols, buffering: 24 symbols. Among these, the training sequence (24 symbols) is called a preamble and corresponds to a known signal section.

  The DFT unit 36 performs discrete Fourier transform processing (hereinafter simply referred to as DFT processing) on the detection signal from the detection unit 18. The DFT processing here is executed on data discretized at a predetermined period shorter than the known signal section at each timing.

となる。ここに、Ｎは、ＤＦＴ処理を行う期間で離散化したポイント数である。 Assuming that the signal input to the DFT unit 36 is f (k), the DFT processing output F (k), its real component Re (k), and its imaginary component Im (k) are:

It becomes. Here, N is the number of points discretized in the period during which DFT processing is performed.

となる。また、実数成分Ｒｅ_２４００（ｔ）は、式（２）から

となり、また、虚数成分Ｉｍ_２４００（ｔ）は、式（３）から

となる。 When the DFT unit 36 performs DFT processing on data obtained by discretizing a period of 16 symbols shorter than a 24-symbol training sequence at symbol reproduction timing, the DFT processing output F ₂₄₀₀ (t) From 1)

It becomes. Further, the real number component Re ₂₄₀₀ (t) is obtained from the equation (2).

And the imaginary number component Im ₂₄₀₀ (t) is obtained from the equation (3).

It becomes.

  The DFT unit 36 can output a DFT processing result for a specific frequency component. In the present embodiment, a frequency band component including a frequency at which the value of the symbol in the known signal section changes is output. This is for detecting whether or not a known signal section is included from the intensity of the frequency component in the subsequent circuit. Specifically, for example, when the frequency of the AIS symbol is 9600 [Hz] and the value of the symbol changes every two symbols in the training sequence, such as 11001100. A period corresponding to the symbol, and the frequency at which the value of the symbol changes is 9600/4 = 2400 [Hz]. That is, 2400 [Hz] component is included in the portion corresponding to the known signal section of the detection signal. Therefore, the DFT unit 36 calculates the values of the above equations (5) and (6) for the frequency component of 2400 [Hz] (band), and outputs this.

Based on the output signal of the DFT unit 36, the intensity acquisition unit 38 acquires the intensity (amplitude) of the frequency component at which the symbol value in the known signal section changes at each timing. As an example, this intensity can be acquired as the sum of the absolute value of the real component and the absolute value of the imaginary component of the output signal from the DFT unit 36. That is, the intensity A ₂₄₀₀ (t) of the component of 2400 [Hz] is A ₂₄₀₀ (t) = | Re ₂₄₀₀ (t) | + | Im ₂₄₀₀ (t) | Here, Re ₂₄₀₀ (t) is a real component of the 2400 [Hz] band, and Im ₂₄₀₀ (t) is also an imaginary component. This intensity can also be obtained as the sum of the square of the real component and the square of the imaginary component, or the square root thereof, but the circuit that performs the operation is the most when obtained as the sum of the absolute values. Be simple.

  Then, the known signal section acquisition unit 40 detects the known signal section from the intensity obtained by the intensity acquisition unit 38. The lower part of FIG. 3 (enlarged view) shows an example of a period (Td; each of 16T, T: interval of timing t) that is a source of DFT processing at each timing (however, only before and after the training sequence). The intensity obtained by the intensity acquisition unit 38 is obtained based on the frequency band component in which the symbol value changes in the known signal section in the DFT processing result. Therefore, when the period Td that is the source of the DFT process overlaps with the known signal section, the intensity should increase.

  The known signal section acquisition unit 40 according to the present embodiment first compares the intensity obtained by the intensity acquisition unit 38 with a predetermined threshold. At this time, if it is equal to or exceeds the predetermined threshold, it can be said that there is a high possibility that the period corresponding to the intensity is a known signal section. As the threshold value, an appropriate value (for example, 90% of the maximum intensity) is set in advance based on the actually obtained intensity or the expected intensity.

  Furthermore, the known signal section acquisition unit 40 according to the present embodiment sets a period corresponding to the timing as a known signal section when the intensity is the same as or exceeds a predetermined threshold at a predetermined number of consecutive times. . Here, it is possible to detect a known signal section by examining the intensity of the DFT processing result based on a longer period than that (for example, once). However, in such a case, if the intensity is accidentally increased due to noise or the like at a time not in the known signal section, it cannot be excluded. That is, the possibility of erroneous detection becomes relatively high. On the contrary, if the calculation is performed for a longer period, the circuit scale of the DFT unit 36 is increased accordingly. Therefore, in this embodiment, the detection accuracy is improved by examining the intensity output from the intensity acquisition unit 38 a plurality of times while reducing the circuit size by reducing the data size for a period shorter than the known signal period. I am trying.

FIG. 4 is a diagram illustrating an example of a waveform of each unit of the known signal section detection unit 26 when the AIS packet 50 illustrated in FIG. 3 is received. In FIG. 4, (a) is the detection signal output from the detection unit 18, and (b) is the intensity A ₂₄₀₀ (t) in the 2400 [Hz] band acquired at timing t. As is apparent from this figure, it can be seen that a period in which the intensity A ₂₄₀₀ (t) is higher than the threshold value Ath appears at a plurality of consecutive times.

Here, FIG. 4 shows an example in which the training sequence is 24 symbols and the timing t is once per symbol. In this case, the intensity A ₂₄₀₀ (t) is a period (= 24) corresponding to the training sequence. It can be seen that the period is larger over a period of 16T, which is shorter than the period of symbols, that is, 24T). This is because the intensity A ₂₄₀₀ (t) when the period Td from which the DFT processing is based is shifted before or after the training sequence (A or C in FIG. 3), the period Td is completely within the training sequence. This is because it is smaller than the intensity A ₂₄₀₀ (t) in the case of being included (B in FIG. 3). Also, from FIG. 4 (b), it can be seen that periods that exceed the threshold continuously do not appear outside the period corresponding to the training sequence. In consideration of such a phenomenon, the number of consecutive times for determining the known signal section is less than the number of timings corresponding to at least the entire known signal section (the number of symbols in the known signal section in the case of one per symbol), and It is preferable to increase the number of consecutive times (for example, 2 or 3) that may occur by chance outside the known signal interval. Specifically, in the example of FIG. 4, the known signal section (training sequence) appears as a period of 16T, whereas the number of consecutive times for determining the known signal section is, for example, 8 times. . That is, when the intensity A ₂₄₀₀ (t) is equal to or exceeds the threshold value Ath for eight consecutive times, the known signal section acquisition unit 40 has at least a known signal section (training) corresponding to the timing. Sequence). In this case, the known signal section acquisition unit 40 includes a counter (not shown) to which an H level signal is input only when the threshold value Ath is exceeded, and the known signal section is acquired in the known signal section when the count number reaches the continuous number. It may be determined that there is. Furthermore, if the count number is reset by the L level signal input when the threshold value Ath is not exceeded, the known signal section can be detected by the continuous number of times. Note that the threshold Ath and the number of consecutive times are not limited to the above example, and different values can be set according to the communication environment, the device configuration, and the like.

In rare cases, some noise may be mixed in the known signal section, and the intensity A ₂₄₀₀ (t) corresponding to the known signal section may temporarily drop. Therefore, the known signal section acquisition unit 40 may determine that the signal is a known signal section when the intensity is equal to or exceeds a predetermined threshold at a predetermined number of times or more within a predetermined period. As an example, in the case of the example of FIG. 4, when the intensity A ₂₄₀₀ (t) exceeds the threshold value Ath 8 times or more out of 10 consecutive timings t, the period corresponding to the timing t is at least a known signal interval. What is necessary is just to determine that it is (training sequence).

  Further, the known signal section may be more reliably detected based on the intensity of the DFT processing result for the frequency other than the frequency of the change of the symbol value in the known signal section. As described above, since the symbol value fluctuates at a predetermined frequency (2400 [Hz] in the above example) within a known signal section of a desired received signal, the intensity is relatively small at other frequencies. On the other hand, in the case of noise, there is a possibility that the intensity is increased at frequencies other than the frequency at which the symbol value changes. Therefore, as illustrated in FIG. 9, the known signal interval detection unit 26 includes a second intensity acquisition unit 38 a, and the frequency at which the symbol value in the known signal interval changes at each timing from the output signal of the DFT unit 36. The intensity (amplitude) of the component of the frequency other than (for example, 1200 [Hz]) is acquired. The known signal section acquisition unit 40a detects the known signal section regardless of the output result of the intensity acquisition unit 38 when the intensity obtained by the second intensity acquisition unit 38a is greater than a predetermined threshold. Absent. Thereby, the detection accuracy of a known signal area can be improved.

  Note that, before being input to the DFT unit 36, predetermined processing (for example, thinning processing, integration processing of two symbol periods, etc.) may be performed on the detection signal. The thinning process reduces the data size and contributes to circuit miniaturization.

  2 further includes a phase error acquisition unit 42, a timing error acquisition unit 44, and an offset error acquisition unit 46. The error detection unit 28 illustrated in FIG.

The phase error acquisition unit 42 acquires a phase error based on the real number component Re and the imaginary number component Im acquired by the DFT unit 36 at each timing t. For example, when the real component of the frequency 2400 [Hz] is Re ₂₄₀₀ and the imaginary component is Im ₂₄₀₀ , the phase error Δθ can be obtained as Δθ = tan ⁻¹ (Im ₂₄₀₀ / Re ₂₄₀₀ ).

  The timing error acquisition unit 44 acquires a timing error corresponding to the phase error. FIG. 5 is a diagram showing an example of the relative relationship between the phase error Δθ and the timing error Δt in the AIS example. Since the signal of 2400 [Hz] is one cycle with four symbols (= 360 (°; deg)), the timing error Δt is Δt = 0 when Δθ = 0, where T is the cycle of one symbol. When Δθ = 45 (deg), Δt = 0.5T, when Δθ = 90 (deg), Δt = T, when Δt = −45 (deg), Δt = −0.5T, Δθ = −90 ( deg), Δt = −T. Information indicating the relative relationship is stored in, for example, a storage unit (for example, a memory or the like; not shown), and the timing error acquisition unit 44 calculates a timing error Δt corresponding to the phase error Δθ received from the phase error acquisition unit 42. get.

  However, only the phase error and timing error acquired in this way are acquired based on the detection signal in the known signal section. Therefore, the timing error acquisition unit 44 according to the present embodiment outputs information indicating the timing error only when the known signal section is detected by the known signal section detection unit 26. For example, as described above, when the intensity is the same as or exceeds the threshold value Ath for eight consecutive times, when it is determined that the period corresponding to the timing is a known signal section, the timing error acquisition unit 44 may output the timing error Δt only at the eighth timing.

In addition, the timing error Δt _i acquired at each timing t when the intensity A _f (t) exceeds the threshold value Ath is sequentially stored in, for example, a shift register, and when a known signal section is detected, the shift register The timing error Δt stored in a predetermined stage may be output. FIG. 6 is a diagram illustrating an example of a main part of the timing error acquisition unit 44 that performs such processing. In this case, the position of the output tap (that is, the stage position) of the shift register 44a is set so that the timing error Δt is output at a predetermined timing (preferably at a substantially central timing) in the known signal section. decide. For example, in the known signal section acquisition unit 40, the known signal section is a section in which the intensity exceeds the threshold value Ath continuously M times (where M ≧ Mmin, Mmin is a preset value, in the case of FIG. 4, for example, Mmin = 14), the timing error at the start or end of the section (Δt ₀ or Δt _{15 in} FIG. 6) is M / 2 or M / 2 + 1 (where M is an even number) or M / 2 + 0. 5 or M / 2-0.5th timing error (when M is an odd number) (in FIG. 6, Δt ₈ , which is the _eighth from the start (Δt ₀ ), that is, at a timing that is substantially at the center of the known signal section. The timing error acquisition unit 44 outputs the shift register according to the number of consecutive times M acquired from the known signal section detection unit 26 so that the timing error Δt _i ) is output. Switch the tap position. Note that, when the tap position is determined based on the timing at which the known signal section ends, the number of stages of the shift register 44a can be set to M / 2 + 1 stages, which has an advantage that the circuit scale can be reduced. The timing for obtaining the timing error Δt may be a timing other than the center of the known signal section, or may be changed or switched dynamically as appropriate. Furthermore, an average value of the timing errors Δt at all timings in the known signal section stored in the shift register may be used.

  The offset error acquisition unit 46 acquires the offset error ΔA of the output (for example, F (t)) of the DFT unit 36 in the known signal section. This offset error ΔA is also preferably acquired when a known signal section is detected, like the timing error Δt. When the detection signal in the known signal section periodically changes, the offset amount of the detection signal can be acquired by acquiring the integral value or average value of the detection signal in the known signal section. When the modulation method is GMSK or GFSK, the offset amount of the detection signal corresponds to a frequency error. The section for acquiring the offset error ΔA is not necessarily a DFT section of 2400 [Hz] (16T in the above example), and may be another section (for example, 8T). Alternatively, the offset error ΔA may be calculated from data with a greater or lesser number of discretization points. Similarly to the case of the timing error Δt, the offset error ΔA can be acquired using a shift register. Here, the shift register may be used only for obtaining the offset error ΔA, and data at a timing before the timing at which the known signal section is detected may be used for obtaining the offset error ΔA.

  The timing error Δt and the offset error acquired in this way by the error detection unit 28 are sent to the correction unit 20 and are used for correction of the symbol reproduction timing in the symbol acquisition unit 22, correction of the threshold for bit determination, and the like. Here, any correction may be performed so as to eliminate the acquired error. By performing such correction, the accuracy of symbol reproduction in the symbol acquisition unit 22 can be further improved. Further, as illustrated in FIG. 8, a correction unit 20a may be provided to correct timing (advance correction / delay correction) and amplitude offset correction on the detection signal. In addition, you may correct | amend in the other part (for example, detection part etc.) of a receiver using the acquired error.

  The integrated block 24 including the known signal section detection unit 26 and the error detection unit 28 may stop the processing in a period in which the input detection signal does not include the known signal section. Therefore, in this embodiment, the power control unit 32 is provided so that power is not supplied to the integrated block 24 during a predetermined period. As an example, when the packet 50 of FIG. 3 is received, the power supply control unit 32 performs a predetermined period (for example, a period from when the start flag is detected until the end flag is detected, a period corresponding to the data section, The power supply to the integrated block 24 can be stopped during the period until the packet ends. As another example, the power supply control unit 32 can stop the supply of power to the integrated block 24 in a period other than the known signal section with reference to the known signal section detected by the known signal section acquisition unit 40. In that case, a margin period for supplying power may be set before and after the known signal section. In addition, in a situation where packets are continuously received at a certain time interval, the power supply / stop timing is once determined, and thereafter, the power is supplied / stopped at a cycle in which the packets are received. May be. Here, the reception period of the packet can be detected as a detected period of the known signal section. Therefore, at the beginning of packet reception (for example, until the second or third time), the appearance period of the known signal section included in each packet is acquired without stopping the power supply, and then the power is supplied / You may make it stop. Furthermore, after a predetermined period, the timing and cycle for supplying / stopping power may be re-determined (corrected) from the detection result of the known signal section.

  Further, based on the detection result of the known signal section acquisition unit 40, the value of the symbol acquired by the symbol acquisition unit 22, or the extracted flag, the non-reception period prediction unit 34 determines the reception period and / or non-reception period of the packet. Can be predicted. Then, in the predicted non-reception period of the packet, the power supply control unit 30 performs the RF signal processing, IF signal processing, and baseband signal processing as well as the detection unit 18 (that is, power supply control). The power supply to the entire demodulation processing unit excluding a part of the unit and the like can be stopped. In this case as well, in a situation where packets are continuously received at a certain time interval, the timing of power supply / stop is once determined, and thereafter, the power is supplied / You may make it stop. In this case, the timing and cycle for supplying / stopping power may be re-determined (corrected) from the detection result of the known signal section again after a predetermined period has elapsed. A margin period for supplying power may be set before and after the packet reception period.

  FIG. 7 is an example of a timing chart in the case where the power ON / OFF of the integrated block 24 (known signal section detecting unit 26 and error detecting unit 28) and the detecting unit 18 is controlled based on the detection result of the known signal section. FIG. In the example of FIG. 7, after the first and second packets 50a and 50b are received, error correction is performed based on the result (error) obtained for the known signal section (TS) in the packets 50a and 50b. And the power on / off of the integrated block 24 and the detector 18 are controlled after the second packet 50b.

  By the way, since the known signal (training sequence signal) is a periodic signal, the average value in the I symbol period (a multiple of I = 4 in the AIS) of the detection signal is substantially constant within the known signal period. Therefore, when the fluctuation of the average value in the I symbol period of the detection signal is observed within a predetermined period (a period corresponding to the length of the known signal period) and the fluctuation is extremely small, the known signal period is detected. can do.

  FIG. 10 is a block diagram illustrating an example of a known signal section detection unit 26a that detects a known signal section based on the change in the average value. The known signal section detection unit 26a includes an average value acquisition unit 52, a difference acquisition unit 54, an average value fluctuation determination unit 56, and a known signal section acquisition unit 40b in addition to the DFT unit 36 and the intensity acquisition unit 38. The known signal section detection unit 26a can be used in place of the known signal section detection unit 26 described above.

  The average value acquisition unit 52 acquires an average value in the I symbol section of the detection signal at each timing t. Note that the DC component acquired by the DFT unit 36 may be used as an average value.

  In this example, the difference acquisition unit 54 includes a delay circuit 58 that delays by L samples and a subtraction circuit 60, and acquires a difference value between the average value before L samples and the average value at the current timing.

  FIG. 11 is a diagram illustrating a detection signal having the same frequency as the repetition frequency of the known signal, its average value, and a difference value. FIG. 12 is a detection signal having a frequency different from the repetition frequency of the known signal, its average value, and difference value. FIG. As can be seen from these figures, when the frequency of the detection signal is the same as the repetition frequency of the known signal, the average value and the difference value do not change, and when the frequency of the detection signal is different from the repetition frequency of the known signal, It can be seen that both the average value and the difference value fluctuate.

  In order to capture such fluctuations, first, the first determination unit 62 of the average value fluctuation determination unit 56 sets the magnitude (absolute value) of the difference value acquired at each timing t to a predetermined threshold (for example, the amplitude of the detection signal). When the difference value is equal to or smaller than the threshold value, “0” is obtained as the determination value at each timing t, and “1” is obtained otherwise. To do. Note that the determination may be made based on whether or not the difference value is within a predetermined range instead of using the absolute value.

  Next, the second determination unit 64 of the average value variation determination unit 56 sums a predetermined number of determination values at each timing t (for example, 12 times before the current timing when the known signal section is 16T). The value is compared with a predetermined threshold value (for example, 0 when the predetermined number is 12). If the total value is equal to or smaller than the threshold value, “0” is set as the final determination value, otherwise "1" is acquired for.

  The known signal section acquisition unit 40b has the intensity acquired by the intensity acquisition unit 38 equal to or exceeds the predetermined threshold over a predetermined number of times (the output in this case is set to “0”), and the average value fluctuation It is assumed that the known signal section is detected when the determining unit 56 determines that the magnitude of the average value fluctuation is within the predetermined range. The known signal section acquisition unit 40b that performs such an operation can be configured by an AND gate 66, a counting circuit 68, and a determination circuit 70 as shown in FIG.

  By performing the determination based on the magnitude of the fluctuation of the average value as described above, it is possible to further suppress erroneous detection of the known signal section.

  The preferred embodiments of the present invention have been described above, but the present invention is not limited to the above-described embodiments, and can be implemented in various equivalent forms.

It is a block diagram which shows an example of the receiver concerning embodiment of this invention. It is a block diagram which shows an example of the integrated block containing the known signal area detection part and error detection part which are contained in the receiver concerning embodiment of this invention. It is a figure which shows an example of the structure of the packet in an AIS system. It is a figure which shows an example of the waveform of the signal (a) output from the detection part concerning embodiment of this invention, and the signal (b) output from an intensity | strength acquisition part. It is a figure which shows an example of the relative relationship of a phase error and a timing error. It is a figure which shows an example of the timing error correction | amendment part contained in the receiver concerning embodiment of this invention. It is a timing chart which shows an example of ON / OFF of the power supply of each part in the receiver concerning embodiment of this invention. It is a block diagram which shows another example of the receiver concerning embodiment of this invention. It is a block diagram which shows another example of the integrated block containing the known signal area detection part and error detection part which are contained in the receiver concerning embodiment of this invention. It is a figure which shows another example of the known signal area detection part contained in the receiver concerning embodiment of this invention. It is a figure which shows an example of the detection value of the same frequency as the repetition frequency of a known signal, the average value acquired with the receiver concerning embodiment of this invention with respect to the detection signal, and a difference value. It is a figure which shows an example of the detection value of the frequency different from the repetition frequency of a known signal, the average value acquired with respect to the detection signal by the receiver concerning embodiment of this invention, and a difference value.

Explanation of symbols

  10, 10a receiver, 12 antenna, 14 RF processing circuit, 16 IF filter, 18 detection unit, 20, 20a correction unit, 22 symbol acquisition unit, 24 integrated block, 26, 26a known signal section detection unit, 28 error detection unit , 30, 32 Power control unit, 34 Non-reception period prediction unit, 36 Discrete Fourier transform unit (DFT unit), 38, 38a Intensity acquisition unit, 40, 40a, 40b Known signal section acquisition unit, 42 Phase error acquisition unit, 44 Timing error acquisition unit, 44a shift register, 46 offset error acquisition unit, 50, 50a, 50b, 50c, 50d packet, 52 average value acquisition unit, 54 difference acquisition unit, 56 average value variation determination unit, 58 delay circuit, 60 subtraction Circuit, 62 first determination unit, 64 second determination unit, 66 AND gate, 68 counting circuit, 7 0 Judgment circuit.

Claims (14)

A discrete Fourier transform unit that performs a discrete Fourier transform for a predetermined period shorter than a known signal section in the received signal at each timing with respect to the detected signal obtained by detecting the received signal;
At each timing, an intensity acquisition unit that acquires the intensity of a component corresponding to the frequency of the change of the symbol value in the known signal section of the output from the discrete Fourier transform unit;
A known signal section acquisition unit for acquiring a known signal section of a received signal based on the intensity obtained at a plurality of timings;
A known signal section detection circuit comprising:   The known signal section acquisition unit, when the intensity is equal to or exceeds a predetermined threshold at a predetermined number of consecutive times, sets a period corresponding to the timing as a known signal section. The known signal section detection circuit according to 1.   The known signal section acquisition unit sets a period corresponding to the timing as a known signal section when the intensity is equal to or exceeds a predetermined threshold at a predetermined number of times within a predetermined period. The known signal section detection circuit according to claim 1, wherein: further,
A second intensity acquisition unit that acquires the intensity of a component having a frequency different from the component corresponding to the frequency of the change in the symbol value in the known signal section of the output from the discrete Fourier transform unit at each timing;
The said known signal area acquisition part further detects the known signal area of a received signal based on the said intensity | strength acquired at the several intensity | strength in the 2nd intensity | strength acquisition part. The known signal section detection circuit according to any one of the above. A known signal section detection circuit according to any one of claims 1 to 4,
Based on the detection result of the known signal section acquisition unit, at least a part of the operation of the known signal section detection circuit is stopped at a timing other than the reception period of the known signal section. circuit. A known signal section detection circuit according to any one of claims 1 to 5,
The known signal section detection circuit, wherein at least a part of the known signal section detection circuit is stopped at a timing of a data section in the received signal.   The known signal according to claim 1, wherein the intensity acquisition unit acquires the intensity as a sum of an absolute value of an in-phase component and an absolute value of a quadrature component of discrete Fourier transform. Section detection circuit. further,
An average value acquisition unit that acquires an average value of the detection signal for a predetermined period shorter than the known signal section in the received signal;
A difference acquisition unit that acquires a difference value between the average value acquired by the average value acquisition unit and the average value acquired previously by a predetermined number of timings;
And detecting a known signal section of a received signal based on a magnitude of a difference value acquired by the difference acquisition section. Detection circuit. The known signal section detection circuit according to any one of claims 1 to 8,
A timing error detection unit that detects an error of a device reference timing with respect to a received signal based on an output signal from the discrete Fourier transform unit;
An error detection circuit comprising:   The error detection circuit according to claim 9, wherein the timing error detection unit outputs, as a detection result, an error with respect to the received signal at the device reference timing acquired at a predetermined timing within the detected known signal section. .   The timing error detection unit includes a shift register, sequentially stores timing errors acquired at each timing when the intensity exceeds a threshold value in the shift register, and when a known signal section is detected, the shift register The error detection circuit according to claim 10, wherein the timing error stored in the predetermined stage is output as a detection result. The timing error detection unit calculates a timing error corresponding to a phase error θ (= tan ⁻¹ (Im / Re)) obtained from the in-phase component Re and the quadrature component Im in the discrete Fourier transform result obtained by the discrete Fourier transform unit. It outputs as a detection result, The error detection circuit as described in any one of Claims 9-11 characterized by the above-mentioned.   A receiving device that corrects device reference timing based on a timing error detected by the error detection circuit according to claim 9, wherein the known signal interval is detected by the known signal interval acquisition unit. A receiving apparatus that corrects the apparatus reference timing when it is performed. A receiving device that detects a received signal and generates a detected signal,
A non-reception period prediction unit that predicts a non-reception period of a received signal based on the known signal period detected by the known signal period detection circuit according to any one of claims 1 to 8,
The receiving apparatus characterized in that at least a part of operations of the receiving apparatus is stopped during the non-receiving period.

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