JP2005202218A - Image data processing system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image data processing system capable of reducing the processing burden of software by a CPU while suppressing a cost increase as far as possible. <P>SOLUTION: A CPU 12 conducts coordinate calculation for displaying image data on a display by the software and writes the address and data which are the results of the calculation into a FIFO 14. When the address and data are written into the FIFO 14, a blend processing circuit 15 conducts a read modify write cycle of reading the data of the same address out of a memory 17 and mixing the read out data and the data written into the FIFO 14, then rewriting the same into the memory 17. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an image data processing apparatus for processing data when displaying other image data superimposed on predetermined display image data.

  For example, many images displayed on the display of a car navigation device have a pattern in which various character information is superimposed and displayed with map data as a background image. When two pieces of image data are displayed so as to overlap with each other in this way, an alias having a jagged shape at the boundary between the two images may occur, making it difficult to see the characters. In order to avoid such a problem, it is effective to perform data processing (so-called blend processing) that multi-tones the boundary portion between the two. Such a blending process is also used when displaying a background image in a state where characters are watermarked.

However, if the CPU tries to perform blend processing by software for all the superimposed image data displayed on the screen, the processing capability of the CPU will be greatly reduced. As a result, it is assumed that the screen display speed decreases and other processing speeds performed by the CPU also decrease.
For example, Patent Document 1 discloses an image processing system that performs the blending process as described above without imposing a burden on the CPU as much as possible. FIG. 4 is a block diagram showing the schematic configuration. That is, the graphic processor 3 is interposed between the CPU 1 and the memory 2 so that the graphic processor 3 is burdened with arithmetic processing necessary for image display as much as possible.

The CPU 1 sets a command for performing character drawing and blending processing (anti-aliasing processing) in the command area 4 and also sets character data, coordinate data, and the like necessary for executing the command. Then, the graphic processor 3 performs coordinate calculation for image display in the coordinate calculation unit 5 based on those commands and data, and performs calculation necessary for blend processing in the blend calculation unit 6. Then, the image data subjected to necessary processing is written into the memory 2 via the memory controller 7.
JP 2003-6665 A

According to the technique disclosed in Patent Document 1, the processing load on the CPU 1 is certainly greatly reduced. However, since a considerable cost increase is assumed to configure the graphic processor 3, it cannot be said that the technology can be applied to any product.
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an image data processing apparatus capable of reducing the software processing burden of the CPU while suppressing an increase in cost.

  According to the image data processing apparatus of the present invention, the CPU performs coordinate calculation for displaying image data on the display means by software (program), and writes the address and data of the coordinate calculation result in the buffer. Then, when the address and data are written in the buffer, the data processing circuit reads the data at the same address from the image memory, mixes the read data and the data written in the buffer at a predetermined ratio, and then reads the image. Write back to memory.

  That is, the CPU performs coordinate calculation by software, and the process of mixing two image data at a predetermined ratio and writing them back to the image memory is performed by a data processing circuit that is external hardware. Therefore, since the configuration of the data processing circuit is relatively simple, it is possible to reduce the software processing load by the CPU while suppressing an increase in cost.

  Hereinafter, an embodiment in which the present invention is applied to an image data processing apparatus that displays image data on a display (display means) of a vehicle navigation apparatus will be described with reference to FIGS. FIG. 1 is a block diagram showing the configuration of the image data processing apparatus. The image data processing device 11 includes a CPU 12, a CPU interface (IF) 13, a FIFO (First In First Out, buffer) 14, a blend processing circuit (data processing circuit) 15, a memory controller 16 and a memory (image memory) 17. ing.

  The CPU 12 performs coordinate calculation for displaying image data on a display (not shown), and writes the address and image data, which are the calculation results, to the FIFO 14 via the CPU interface 13. The FIFO 14 includes an address FIFO 14A, a data FIFO 14D, and a FIFO controller 14C. The address FIFO 14A holds a plurality of write addresses output by the CPU 12, and the data FIFO 14D holds a plurality of write data output by the CPU 12. The FIFO controller 14C is hardware that controls output of addresses and data from the FIFO 14 side to the blend processing circuit 15 and the memory controller 16 side.

  The blend processing circuit 15 includes an offset address register (offset address) 18, blend value registers 19 and 20, adders 21 and 22, multipliers 23 and 24, and a limiter 25. The offset address register 18 is a register for setting an offset address value in order to reduce the bit width of the address FIFO 14A. The offset address value and the address value output from the address FIFO 14A are added by the adder 21. Are output to the memory 17 side.

  As will be described later, the blend value registers 19 (Blend value 1) and 20 (Blend value 2) output, for example, the background image data stored in the memory 17 and the CPU 12 superimposing it on the background image data for display. It is a register for setting a blend ratio with image data of character information to be performed. For example, as conceptually shown in FIG. 2, when the blend ratio is α%, data “α / 100” is set in the register 19 and data “(100−α) / 100” is stored in the register 20. set. For example, when the bit width of the registers 19 and 20 is 8 bits, the above “100” is “255” (of course, α is also a value corresponding to 8-bit data).

  The data read from the data FIFO 14D (character information data in the above example) is multiplied by the blend value set in the register 19 by the multiplier 23. The data read from the memory 17 (background image data in the above example) is multiplied by the blend value set in the register 20 by the multiplier 24. Then, the output data of the multipliers 23 and 24 are output to the adder 22 and added, and then output as write data to the memory 17 via the limiter 25. When the calculation result of the adder 22 overflows the set bit width, the limiter 25 functions to clip the calculation result with the maximum value of the set bit width.

  The memory 17 is composed of, for example, a DRAM, and the memory controller 16 is hardware that performs address multiplex processing and refresh management for the memory 17 and controls read / write cycles. The memory controller 16 also reads out image data written in the memory 17 and performs access arbitration with a drawing control circuit (hardware) for displaying on the display via the drive circuit.

  Next, the operation of the present embodiment will be described with reference to FIG. FIG. 3 is a sequence diagram showing a flow of processing when the CPU 12 superimposes and displays image data such as character information on the background image data already written in the memory 17. First, the CPU 12 writes an offset address value in the offset address register 18 in the blend processing circuit 15 (a). Subsequently, data corresponding to the blend ratio of the superimposed image data is set in the blend value registers 19 and 20 as described above (b).

  Next, the CPU 12 performs coordinate calculation for displaying the image data (c). When the calculation is completed, the superimposed image data (1) is written in the FIFO 14 at an address obtained by subtracting the offset address from the calculated result address (d). ). Further, the CPU 12 performs coordinate calculation for the next image data (2), and writes the superimposed image data (2) in the FIFO 14 at the address of the calculation result. These processes are sequentially repeated until a predetermined data amount (x) corresponding to the display image is reached.

  When the superimposed image data (1) is written into the FIFO 14 by the CPU 12, the FIFO controller 14C reads out the address written in the address FIFO 14A, outputs it to the blend processing circuit 15, and reads / modifies / writes to the memory controller 16. (RMW) A request to start a cycle (request) is output (e). At this time, the blend processing circuit 15 adds the address value of the offset address register 18 to the address value read from the address FIFO 14A, and outputs it to the memory controller 16 side. The FIFO controller 14C also outputs the data written in the data FIFO 14D to the blend processing circuit 15 (f).

  In response to the RMW start request from the FIFO controller 14C, the memory controller 16 performs a read cycle for the memory 17 (g). The read data is supplied to the multiplier 24 of the blend processing circuit 15 (h), and blend (mixing) processing is executed (i). That is, the output results of the multipliers 23 and 24 are added by the adder 22. The addition result is output as write data to the memory controller 16 side via the limiter 25, and a write request command is output to the memory controller 16 (j). In response to the request command, the memory controller 16 writes data to the memory 17 (k).

  Thereafter, the memory controller 16 returns an acknowledge signal (1) indicating that the RMW cycle is completed to the FIFO 14 (l). Then, the FIFO controller 14C reads the next address and data (2) written in the address FIFO 14A and the data FIFO 14D by the CPU 12, and executes a process similar to the above.

  Thereafter, the FIFO controller 14C (and the blend processing circuit 15 and the memory controller 16) sequentially processes the remaining addresses and data written in the address FIFO 14A and the data FIFO 14D. When the acknowledge signal (x) indicating that the RMW cycle for the last data (x) is completed from the memory controller 16 (m), the FIFO controller 14C has finished writing all data to the CPU 12. An interrupt indicating that this occurs is generated (n). Thus, a series of operations is completed. The image data written in the memory 17 is read out by the drawing circuit via the memory controller 16 and output to the drive circuit of the display for image display.

  When it is not necessary to superimpose image data, for example, when writing background image data into the memory 17, the blend rate of dummy data is set to “0” and the same RMW cycle as described above is performed. May be. Alternatively, a separate control register may be provided to stop the function of the blend processing circuit 15 and perform only the write cycle.

  As described above, according to this embodiment, the CPU 12 performs coordinate calculation for displaying image data on the display by software (program), and writes the address and data of the coordinate calculation result to the FIFO 14. Then, when the address and data are written in the FIFO 14, the blend processing circuit 15 reads the data at the same address from the memory 17, and mixes the read data and the data written in the FIFO 14 at a predetermined ratio, and then the memory. The RMW cycle to write back to 17 was performed.

  That is, the CPU 12 performs coordinate calculation by software, and the process of mixing the two image data at a predetermined ratio and writing it back to the memory 17 is performed by the blend processing circuit 15 which is external hardware. Therefore, the configuration of the blend processing circuit 15 is relatively simple, and it is possible to reduce the software processing load on the CPU 12 while suppressing an increase in cost as much as possible.

The present invention is not limited to the embodiments described above and illustrated in the drawings, and the following modifications or expansions are possible.
The offset address register 18 and the limiter 25 may be provided as necessary by individual design.
The image memory is not limited to a DRAM, and an SRAM may be used.

  The present invention is not limited to the processing of image data to be displayed on the display of the vehicle navigation device, and can be widely applied as long as two types of image data are mixed and displayed at a predetermined ratio.

The block diagram which shows one Example at the time of applying this invention to the image data processing apparatus which displays image data on the display of a navigation apparatus for vehicles, and shows the structure of an image data processing apparatus The figure explaining notionally the blend processing of two image data Sequence diagram showing the flow of processing when the CPU displays other image data superimposed on background image data already written in the memory Functional block diagram showing schematic configuration of conventional technology

Explanation of symbols

In the drawing, 11 is an image data processing device, 12 is a CPU, 14 is a FIFO (buffer), 15 is a blend processing circuit (data processing circuit), and 17 is a memory (image memory).

Claims (1)

A CPU for calculating coordinates for displaying image data on the display means;
An image memory in which the image data is written;
A buffer for holding addresses and data output by the CPU to the image memory;
When the address and data are written to the buffer, the data at the same address is read from the image memory, the data written to the buffer and the data read from the image memory are mixed at a predetermined ratio, and An image data processing circuit device comprising: a data processing circuit for processing to write back to an image memory.

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