JP2005197865A - Standby power reducing circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a standby power reducing circuit which is low in power consumption by a simple structure without using a microcomputer etc., and has no delay of reception resuming when an intermittent operation is required. <P>SOLUTION: The device has a digital transmission apparatus 1 provided with a pulse output terminal 1B for receiving an analog or digital signal and outputting a digital pulse signal during receiving this signal, and an enable/disable terminal 1A; and a detection generating circuit 2 using the digital pulse signal as an input for performing pulse detection for this input and level generation, and transmitting a control signal to the enable/disable signal terminal 1A of the apparatus 1. The circuit 2 generates a control signal for determining the presence or absence of the digital pulse signal, and bringing an operation of the apparatus 1 into an enable state if the digital pulse signal is present and into a disable state if the signal is not present. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a standby power reduction circuit, and more particularly to a standby power reduction circuit of an infrared communication device.

  Infrared communication devices have been standardized by standardization by standards organizations such as IrDA (Infrared Data Association), and various devices have been commercialized as one of the short-range wireless communication systems. In these short-range wireless applications, the terminal device itself is portable, and severe power saving is often required. In view of the above circumstances, as a method for reducing power consumption, for example, “Low power consumption information system, low power consumption peripheral device and low power consumption IrDA Control dongle” described in Patent Document 1 is available.

The specific configuration content of Patent Document 1 is premised on the use according to the physical layer standard of IrDA. As shown in FIG. 13, the IrDA device 100 according to Patent Document 1 intermittently operates the infrared transceiver unit 103 on the assumption that power is supplied from a USB (Universal Serial Bus) terminal 101 and the microcomputer unit 102 is used. The outline of the operation is as follows. The microcomputer unit 102 performs active sleep of the infrared transceiver unit 103 including the transmission unit 103 </ b> A and the reception unit 103 </ b> B at a predetermined interval using the control line 106. As a result, when the infrared transceiver unit 103 operates intermittently and the receiving unit 103B of the infrared transceiver unit 103 detects a signal, the microcomputer unit 102 activates the operation of the infrared transceiver unit 103 constantly. Data transmitted / received by the infrared transceiver unit 103 is transmitted / received to / from the microcomputer unit 102 via the hardware logic unit 107.
JP 2000-284867 A

  The conventional techniques described above have the following problems. It is a relatively high-function device, and even if a microcomputer is used, it is good if the volume and cost of the device meet the requirements. However, when it is desired to realize this part as simply as possible and at a reduced cost without using a microcomputer or the like, it is necessary to use a technique for reducing standby power with as few parts as possible.

  Moreover, although the power consumed by the apparatus can be reduced by the intermittent operation, the power is still consumed slightly. Even if the value is uA order, when a small coin battery having an electric capacity of only about 20 to 30 mAh is used, the value cannot be ignored. Depending on the use of the device, it may be better not to perform intermittent operation when no received signal is detected or when no operation is required.

  In addition, when the target receiving device itself does not require real-time performance such as data transfer, there is a case where even intermittent operation has an effect of power saving. However, there are cases where real-time characteristics such as reception of voice and images are required. On the other hand, the transmission means such as infrared rays has directivity, and the receiving apparatus repeats on / off operation at intermittent operation intervals. In such a state, a user with a receiving device may move between a signal receivable position and an impossible position. If the device goes out of the reception area even for a moment, the signal cannot be received again unless waiting for the interval of the worst intermittent operation, and QoS (Quality of Service) is lowered. In order to avoid this, if the intermittent operation interval is shortened, the original power saving effect is reduced.

  The present invention provides a standby power reduction circuit that solves the above-described problems, has a simple configuration that does not use a microcomputer or the like, has low power consumption, and has no delay in resuming reception when intermittent operation is required. There is.

In order to solve the above problems, the invention of claim 1 includes a pulse output terminal for receiving an analog or digital signal and transmitting a digital pulse signal during reception of the signal, and an enable / disable terminal. A digital transmission device; and a detection generation circuit that receives the digital pulse signal as input, performs pulse detection and level generation for the input, and sends a control signal to the enable / disable terminal of the digital transmission device, The generation circuit determines whether or not the digital pulse signal is present, and generates the control signal that enables the operation state of the digital transmission device when the digital pulse signal is present and disables the digital pulse signal when the digital pulse signal is absent. This is a standby power reduction circuit.
According to a second aspect of the present invention, in the standby power consumption reduction circuit according to the first aspect, the detection generation circuit inputs the digital pulse signal to a gate terminal, and connects a source terminal to the GND of the circuit, and the NMOSFET A first resistor connected between the drain terminal and the power supply voltage; a capacitor connected between the drain terminal and the GND of the circuit; and the drain terminal as an input, and an output as the enable disable. And an inverter serving as the control signal to the terminal.
According to a third aspect of the present invention, in the standby power consumption reduction circuit according to the first aspect, the detection generation circuit inputs the digital pulse signal to the gate terminal, and connects the source terminal to the GND of the circuit; A first resistor connected between the drain terminal of the NMOSFET and the power supply voltage; a capacitor connected between the drain terminal and the GND of the circuit; and the drain terminal as an input; An inverter serving as the control signal to the enable / disable terminal; a second and a third connected between the power supply terminal of the inverter and the power supply voltage; and between the GND terminal of the inverter and the GND of the circuit; It is characterized by having a resistor.
According to a fourth aspect of the present invention, in the standby power consumption reduction circuit according to any one of the first to third aspects of the present invention, the standby power consumption reduction circuit includes a pulse generator that inverts a level for a predetermined period every predetermined period, and a two-input OR circuit The control signal to the enable / disable terminal is the first input of the two-input OR circuit, the output from the pulse generator is the second input of the two-input OR circuit, and the output of the two-input OR circuit is The signal is sent to the enable / disable terminal.

  According to the present invention, a standby power reduction circuit having a simple configuration that automatically stops operation after a set time when a signal to be received is no longer detected without using a microcomputer or the like is realized. If intermittent operation is required, a timer configured with a one-shot multi that can be configured with simple logic instead of a microcomputer will be used. When the operation is automatically stopped later and the received signal is detected again, it is possible to automatically shift to the steady operation mode. In addition, during a certain period, the steady operation mode can be maintained even if the reception signal is interrupted, and the delay in resuming reception can be eliminated.

  Also, the circuit configuration of the part that detects the received signal and turns on / off the entire circuit based on it is materialized at the component level such as transistor, resistor, capacitor, inverter, etc. However, it is possible to reduce even components that flow to increase the power consumption of the entire circuit.

Next, an embodiment of the present invention will be described.
[Embodiment 1]
As shown in FIG. 1, the standby power reduction circuit according to the present embodiment includes an infrared communication device 1 and a detection generation circuit 2.

  The infrared communication device 1 is one of digital transmission devices, and transmits and receives analog signals and digital signals by infrared rays. In the present embodiment, an analog signal or a digital signal transmitted by infrared rays is a transmission signal S, and an analog signal or a digital signal received by infrared rays is a transmission signal R. The infrared communication device 1 includes an enable / disable terminal 1A and a pulse output terminal 1B. For example, when a high-level enable / disable signal a is supplied as a control signal to the enable / disable terminal 1A, the infrared communication device 1 enters a sleep mode. In this sleep mode, the infrared communication device 1 consumes little power. Conversely, when the low level enable / disable signal a is applied to the enable / disable terminal 1A, the infrared communication apparatus 1 enters the normal active mode. In this state, the infrared communication device 1 can receive the reception signal R. In the present embodiment, the high level is the power supply voltage (Vcc) supplied to the infrared communication device 1, and the low level is the ground (GND) level.

  When receiving the reception signal R in the active mode, the infrared communication device 1 outputs the digital pulse signal b from the pulse output terminal 1B to the detection generation circuit 2. That is, the infrared communication device 1 continues to output the digital pulse signal b from the pulse output terminal 1B while receiving the reception signal R.

  The detection generation circuit 2 performs pulse detection and level generation. That is, as shown in FIG. 2, when the digital pulse signal b is added from the infrared communication device 1, the detection generation circuit 2 detects the digital pulse signal b and generates a low-level enable / disable signal a. Then, the detection generation circuit 2 outputs the enable / disable signal a to the infrared communication device 1. When the digital pulse signal b is not output from the infrared communication device 1, the detection generation circuit 2 outputs a high level enable / disable signal a.

  For example, as shown in FIG. 3, the detection generation circuit 2 includes a pulse detection circuit 2A and a level generation circuit 2B. The pulse detection circuit 2A detects the presence or absence of the digital pulse signal b. When the pulse detection circuit 2A detects the digital pulse signal b, the level generation circuit 2B outputs a low-level enable / disable signal a to the infrared communication device 1. The level generation circuit 2B outputs a high level enable / disable signal a when the pulse detection circuit 2A stops receiving the digital pulse signal b.

  As described above, according to the present embodiment, the enable / disable terminal 1A remains at a low level during a period in which the digital pulse signal b is output. However, if the reception signal R is lost and the digital pulse signal b is not output, If inverted to high level, the standby power consumption of the infrared communication device 1 can be reduced by utilizing the sleep / active operation of the infrared communication device 1. In addition, in order to resume the operation of the infrared communication apparatus 1 once in the sleep mode, a trigger for setting the enable / disable terminal 1A to a low level for a moment during the signal reception period may be added.

  Thus, according to the present embodiment, the power consumption can be suppressed only when the reception signal R is not detected and it is meaningless even if the circuit itself operates, and a significant reduction in standby power consumption can be realized.

[Embodiment 2]
The standby power reduction circuit according to the present embodiment includes an infrared communication device 1 and a detection generation circuit 10 as shown in FIG. In the following embodiments, components that are considered to be the same as or the same as those of the above-described embodiment are denoted by the same reference numerals, and description thereof is omitted.

  In this embodiment, the basic concept of operation is the same as that of the first embodiment, but in this embodiment, the detection generation circuit 10 is used instead of the detection generation circuit 2 of the first embodiment. Here, the pulse detection circuit and the level generation circuit in the first embodiment are configured as a circuit using specific electronic components. As shown in FIG. 5, the detection generation circuit 10 includes an NMOSFET (N-type Metal Oxide Field Effect Transistor) 11, a resistor 12, a capacitor 13, an inverter 14, an input terminal 15, and an output terminal 16. Has been.

  The NMOSFET 11 is a transistor that is turned on / off by a digital pulse signal b applied to the input terminal 15. The digital pulse signal b is applied to the gate (G) terminal of the NMOSFET 11. The source terminal (S) of the NMOSFET 11 is connected to the GND (ground) of the circuit. The resistor 12 is for determining a charging time when charging the capacitor, that is, the capacitor 13. The resistor 12 is connected between the power supply voltage (Vcc) and the drain terminal (D) of the NMOSFET 11, and the capacitor 13 is connected between the drain terminal (D) of the NMOSFET 11 and the GND of the circuit. The inverter 14 outputs an enable / disable signal c having a high level or a low level in accordance with the charging of the capacitor 13. In other words, the detection generation circuit 10 uses the RC time constant using the charging of the capacitor 13 as a timer to determine the time interval until it is disabled.

  A digital pulse signal b in the order of kHz to MHz is input to the input terminal 15 of the detection generation circuit 10 in accordance with the reception signal R of the infrared communication device 1. In this case, the response speed is slowed by the time constant on the output side of the NMOSFET 11 and apparently the NMOSFET 11 can be kept on at all times. Therefore, the potential at the point P becomes low level (GND). The P point potential is also the enable / disable signal a in FIG. However, the received signal R is not detected, and the level of the digital pulse signal b is fixed at a low level. As a result, the NMOSFET 11 is turned off, and the capacitor 13 is connected to the power supply voltage (Vcc) via the resistor 12, so that it is charged over time. As a result, the P point potential approaches the power supply voltage (Vcc) with time, and finally reaches the power supply voltage (Vcc). The time to reach the power supply voltage (Vcc) depends on the time constant determined by the product of the value R1 of the resistor 12 and the value C1 of the capacitor 13, and these values are selected to meet the purpose of the operation. The operation described above naturally matches the behavior of FIG. 2 described above.

  In the configuration of the timer using the RC time constant, the output voltage changes with a very gentle slope. For this reason, depending on the circuit components, an intermediate potential that does not satisfy the specification allowed as a predetermined logic level is passed, and depending on the circuit configuration of the subsequent stage, a through current flows from the power source to GND, etc. Electricity consumption may increase. Therefore, in this embodiment, an inverter 14 is added, and it is determined whether or not the input level of the inverter 14 exceeds a certain threshold by RC charge / discharge, the level is clamped as the output of the inverter 14, and the level is steep. An enable disable signal c (waveform in the upper right of FIG. 5) that rises to the power supply voltage (Vcc) is generated. Then, the detection generation circuit 10 outputs the enable / disable signal c from the output terminal 16 so as to return to the enable / disable terminal 1A of the infrared communication device 1, and the level sharply changes from the high level to the low level. Therefore, it has no intermediate potential.

  With such a configuration, each of the NMOSFET 11, the resistor 12, and the capacitor 13, and the inverter 14 is one component, and includes a timer and a reception signal detection unit, and an enable / disable signal c is output. The function to be generated can be realized. Here, since the inverter 14 is inserted, the logic level that determines enable / disable in the infrared communication device 1 is the opposite specification to that of the first embodiment. That is, it is enabled at a high level and disabled at a low level.

  Thus, according to the present embodiment, when the reception signal R is no longer detected, the operation of the entire circuit is stopped (disable mode). However, the reception signal R is limited only during the period determined by the RC time constant. Even in the case of applications that require real-time performance, such as voice and images, there is no delay in the start of reception, so there is no “jump” of sound or images. Can be reduced.

In addition, with a configuration with very few parts such as one transistor, one resistor, one capacitor, and one inverter,
(1) Detection of received signal,
(2) Timer,
(3) Level generation and output,
Thus, the standby power consumption can be reduced.

Furthermore, the enable / disable terminal output can be passed to the subsequent stage as a high / low logic level signal in which a logic amplitude is secured, instead of an intermediate potential, by level clamping by an inverter.
[Embodiment 3]
The standby power reduction circuit according to the present embodiment includes an infrared communication device 1 and a detection generation circuit 20, as shown in FIG. In the present embodiment, a detection generation circuit 20 is used instead of the detection generation circuit 10 of the second embodiment. Here, the part which expands the function of the detection generation circuit 10 of Embodiment 2 is demonstrated.

  In the detection generation circuit 10 shown in the second embodiment, an RC time constant using charging of a capacitor (capacitor 13) is used as a timer to determine a time interval from when the received signal R is no longer detected until it is disabled. The inverter 14 is used for level clamping. These points are the same in the detection generation circuit 20 of the present embodiment. When the inverter 14 is configured by a CMOS inverter or the like, depending on the circuit configuration with the connection destination of the output terminal of the inverter 14, a current that passes through the Vcc side or the GND side flows during the period when the input of the inverter 14 passes through the intermediate potential. There is.

  Therefore, in this embodiment, as shown in FIG. 7, the high resistance 21 is inserted as the first resistor in the power supply terminal portion of the inverter 14 supplying Vcc so as not to reduce the standby current reduction effect. The high resistor 22 is inserted as a second resistor in the portion of the GND terminal that grounds the inverter 14. As a result, the current passing through the power source / GND can be minimized while ensuring the operation as the inverter 14.

  Thus, according to the present embodiment, in Embodiments 1 and 2, a through current may flow between the power supply or GND for a moment depending on the relationship between the output of the inverter 14 and the peripheral connection circuit in the subsequent stage. In the embodiment, there is an effect that even instantaneous power related thereto can be reduced.

[Embodiment 4]
As shown in FIG. 8, the standby power reduction circuit according to this embodiment includes an infrared communication device 1, a detection generation circuit 20, an intermittent pulse generator 31, and an OR circuit 32.

  The intermittent pulse generator 31 serves as a trigger for intermittent operation, and is a pulse generator such as a timer that generates an intermittent pulse d having a width t at a period T as shown in FIG. The intermittent pulse generator 31 can be realized by a component having a simple configuration such as a one-shot multi composed of several transistors.

  The OR circuit 32 is a two-input OR circuit, and is provided between the output terminal 16 of the detection generation circuit 20 that outputs the enable / disable signal c and the enable / disable terminal 1A of the infrared communication device 1. The OR circuit 32 calculates the logical sum of the enable / disable signal c from the detection generation circuit 20 and the intermittent pulse d from the intermittent pulse generator 31, and generates a new enable / disable signal e. The disable signal e is output to the enable / disable terminal 1A of the infrared communication device 1.

  The configuration according to this embodiment is as described above. With this configuration, it is assumed that the enable / disable specification of the infrared communication device 1 is enabled when the level is high and disabled when the level is low. In this state, when the reception signal R is not detected, the entire module is enabled once in the period T by the width of t as shown in FIG. At this time, when the receiving unit of the infrared communication device 1 receives the signal and the digital pulse signal b is output, the NMOSFET 11 continues to be turned on and the output terminal 16 becomes high level. For this reason, when the output of the OR circuit 32 becomes high level and the reception signal R is present, the infrared communication device 1 of the detection generation circuit 20 continues to operate.

  On the other hand, when the reception signal R is no longer detected, the NMOSFET 11 is turned off and the level of the enable / disable terminal 1A becomes low, so that the infrared communication device 1 is shut down during the period (Tt) in FIG. It will be on only during the period.

  By repeating the above operation, the standby power reduction circuit according to the present embodiment is continuously enabled only when the reception signal R is detected, and the stable operation is continued. When the reception signal R is no longer detected, only the timer (intermittent pulse generator 31) performs the monitoring operation and consumes very little power.

  Here, the consumed power will be described using a specific example. The average current consumption of the intermittent pulse generator 31 is 10 μA, and the current consumption of the entire standby power reduction circuit is 1100 μA. Further, the enable state maintaining period (operation mode holding period) is set to 20 seconds. The enable state maintaining period is a period from when the reception signal R is no longer detected until the disable mode is entered. An example of a change in current consumption that occurs in such a state is as follows. As shown in FIG. 10 (a), when the high resistances 21 and 22 that are limiting resistances are not present in the inverter 14, as shown in FIG. 10 (b), when the received signal R is not detected at time M1, the point P In response to a gradual change due to the RC time constant of the potential, the current consumption changes in a “mountain” shape.

  On the other hand, as shown in FIG. 11A, when the high resistances 21 and 22 are in the inverter 14, as shown in FIG. 11B, if the reception signal R is not detected at time M1, The current consumption changes stepwise from the operation period to the operation mode holding period and the standby period.

When the consumption current that changes in a “mountain” shape in FIG. 10B is approximated by a triangle, if the peak value of the consumption current that changes in the “mountain” shape is 1500 μA, the consumption current amount during this transition is
70 seconds × 1500 μA × 0.5 = 53 mA seconds. On the other hand, the current consumption in the case of FIG.
20 seconds × 500 μA = 10 mA seconds.

Further, the influence of current consumption at the time of transition when the reception signal R changes from on to off is such that the unit operation time, that is, the time until the reception signal R is turned off is shortened as the unit operation time is repeated. Become prominent. Here, the capacity of the battery used is 55 mAh taking the value of a typical lithium coin battery as an example, and as described above, the current consumption value during continuous operation (steady operation) of the entire circuit is 1.1 mA. And the current consumption during standby is 10 μA. The continuous operation operation of the lithium coin battery can be sustained when the value of the current consumption during the transition is 53 mA seconds (without limiting resistance) calculated previously and 10 mA seconds (with limiting resistance). FIG. 12 shows the result of trial calculation. The calculation formula without limiting resistor is
Continuous operation time = (55-55 × (53 / ( X + 53)) / 1. 1
It is. The calculation formula when there is a limiting resistor is
Continuous operation time = (55−55 × (10 / (X + 10)) / 1 _.
It is. In these equations, the unit of the unit operation time X is second.

  Thus, it can be seen that the effect is significant when the unit operation time is 10 minutes or less. For example, when the unit operation time is 2 minutes, the continuous operation time can be extended by 11 hours when there is a limiting resistance compared to when there is no limiting resistance.

  In the present embodiment, as an example, the intermittent pulse generator 31 makes its output intermittently high, and the NMOSFET 11 has a configuration in which the output becomes low when the input is at low level, and the enable / disable signal c and the intermittent pulse d Although the OR circuit 32 is used to synthesize logic, naturally, if the logic of enable / disable is reversed, a logic circuit unit other than the OR circuit may be used so as to realize the above operation. The purpose is to realize a logic that shifts to a continuous stable operation when the intermittent pulse generator 31 detects a received signal within a period of enabling the infrared communication device 1 for a moment.

  Thus, according to the present embodiment, each of the transistor, the capacitor, the resistor, and each of the two inverters includes the operation time maintaining timer and the reception signal detection unit, and the function of generating the enable / disable signal. Can be provided. As a result, when the reception signal is not detected, the intermittent operation mode is entered. However, when the reception signal is detected again, the infrared communication device 1 is enabled, transitions to a stable operation state, and is further determined by a time constant. Only during the period, even if the received signal is not detected, the stable operation (enable) state can be maintained, so even applications that require real-time performance, such as audio and images, can be received within the enable state maintenance period. Since there is no delay in the start, it is possible to reduce “jumping” such as sounds and images.

1 is a configuration diagram illustrating a standby power reduction circuit according to Embodiment 1. FIG. It is a wave form diagram explaining the operation | movement corresponding to the presence or absence of the reception signal of an enable disable signal. 2 is a configuration diagram illustrating an example of a detection generation circuit according to Embodiment 1. FIG. FIG. 6 is a configuration diagram illustrating a standby power reduction circuit according to a second embodiment. FIG. 6 is a circuit diagram illustrating a detection generation circuit according to a second embodiment. FIG. 6 is a configuration diagram illustrating a standby power reduction circuit according to a third embodiment. FIG. 6 is a circuit diagram illustrating a detection generation circuit according to a third embodiment. FIG. 6 is a configuration diagram illustrating a standby power reduction circuit according to a fourth embodiment. It is a wave form diagram explaining operation | movement of the intermittent pulse generator of Embodiment 4. It is explanatory drawing explaining the consumption current when there is no limiting resistance. It is explanatory drawing explaining the consumption current in case there exists a limiting resistance. It is a graph which shows continuous operation time. It is explanatory drawing which shows the outline | summary of an example of a prior art.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Infrared communication apparatus 1A Enable disable terminal 1B Pulse output terminal 2 Detection generation circuit 2A Pulse detection circuit 2B Level generation circuits 10 and 20 Detection generation circuit 11 NMOSFET
DESCRIPTION OF SYMBOLS 12 Resistance 13 Capacitor 14 Inverter 15 Input terminal 16 Output terminal 21, 22 High resistance 31 Intermittent pulse generator 32 OR circuit

Claims (4)

A digital transmission device (1) having a pulse output terminal (1B) for receiving an analog or digital signal and transmitting a digital pulse signal during reception of the signal; and an enable / disable terminal (1A);
A detection generation circuit (2) that receives the digital pulse signal as input, performs pulse detection and level generation for the input, and sends a control signal to the enable / disable terminal (1A) of the digital transmission device (1); And
The detection generation circuit (2) determines the presence / absence of the digital pulse signal, and when the digital pulse signal is present, enables the operation state of the digital transmission device (1), and disables the control signal when the digital pulse signal is absent. Generating a standby power reduction circuit. The detection generation circuit includes:
An NMOSFET (11) for inputting the digital pulse signal to a gate terminal and connecting a source terminal to a circuit GND;
A first resistor (12) connected between a drain terminal of the NMOSFET (11) and a power supply voltage;
A capacitor (13) connected between the drain terminal and the GND of the circuit;
An inverter (14) having the drain terminal as an input and an output as the control signal to the enable / disable terminal (1A);
The standby power consumption reduction circuit according to claim 1, comprising: The detection generation circuit includes:
An NMOSFET (11) for inputting the digital pulse signal to the gate terminal and connecting the source terminal to the GND of the circuit;
A first resistor (12) connected between the drain terminal of the NMOSFET (11) and the power supply voltage;
A capacitor (13) connected between the drain terminal and the GND of the circuit;
An inverter (14) having the drain terminal as an input and an output as the control signal to the enable / disable terminal (1A);
Second and third resistors (21, 22) connected between the power supply terminal of the inverter (14) and the power supply voltage, and between the GND terminal of the inverter (14) and the GND of the circuit, respectively. When,
The standby power consumption reduction circuit according to claim 1, comprising: A pulse generator (31) whose level is inverted only for a predetermined period every predetermined period;
A two-input OR circuit (32),
The control signal to the enable / disable terminal (1A) is the first input of the two-input OR circuit (32), and the output from the pulse generator (31) is the second input of the two-input OR circuit (32). The standby power consumption reduction circuit according to any one of claims 1 to 3, wherein the standby input power consumption reduction circuit (1) is configured to send the output of the two-input OR circuit (32) to the enable / disable terminal (1A).

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