JP2005197622A - Method and device for designing semiconductor integrated circuit, method for evaluating current value relative variation characteristic of semiconductor integrated circuit, method for evaluating resistance value relative variation characteristic of semiconductor integrated circuit, manufacturing method of semiconductor integrated circuit, control program and readable record medium - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To carry out circuit design by deciding the division number of a field effect transistor which is optimum to maximize characteristic relative accuracy and using the obtained optimum division number. <P>SOLUTION: The semiconductor integrated circuit to be designed is constituted by arranging a paired field effect transistor consisting of a first field effect transistor and a second field effect transistor of the same conductivity type and the same gate electrode size in a semiconductor substrate, and connecting a plurality of field effect transistor elements parallel mutually. The paired field effect transistors are divided each in the widthwise direction of a gate electrode. When the division number of the field effect transistor is decided, current value relative variation between the first field effect transistor and the second field effect transistor caused by dispersion in manufacturing is expressed by the function of the division number, the division number which minimizes the current value relative variation is derived numerically, and the circuit is designed by using the obtained optimum division number. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor integrated circuit for reducing an influence caused by manufacturing variations of a field effect transistor pair and a resistor element pair that require high characteristic relative accuracy in an analog type or a mixed analog / digital type semiconductor integrated circuit. Circuit design device, semiconductor integrated circuit design method, semiconductor integrated circuit current value relative variation characteristic evaluation method, semiconductor integrated circuit resistance value relative variation characteristic evaluation method, semiconductor integrated circuit manufacturing method, and control for causing a computer to execute these The present invention relates to a program and a readable recording medium on which the program is recorded.

  Circuits that require a field effect transistor pair having such a high characteristic relative accuracy include a differential amplifier circuit and a current mirror circuit formed on a semiconductor substrate.

  FIG. 9 is a circuit diagram showing a main configuration of a conventional typical MOSFET differential amplifier.

  As shown in FIG. 9, the MOSFET differential amplifier 100 includes a constant current source I1, N-type field effect transistors Mn1 and Mn2, and P-type field effect transistors Mp1 and Mp2. The P-type field effect transistor Mp1 and the N-type field effect transistor Mn1, and the P-type field effect transistor Mp2 and the N-type field effect transistor Mn2 are respectively connected in series, and these series circuits are connected to the output side of the constant current source I1. And a ground potential (ground). The input side of the constant current source I1 is connected to the power supply voltage VDD. The input voltage Vi1 is connected to the gate electrode of the P-type field effect transistor Mp1, and the input voltage Vi2 is connected to the gate electrode of the P-type field effect transistor Mp2. Further, the gate electrodes of the N-type field effect transistors Mn1 and Mn2 are commonly connected to a connection portion between the P-type field effect transistor Mp1 and the n-type field effect transistor Mn1. An output voltage is output from a connection portion between the P-type field effect transistor Mp2 and the n-type field effect transistor Mn2.

  In the differential amplifier circuit of MOSFET differential amplifier 100, N-type field effect transistors Mn1 and Mn2 and P-type field effect transistors Mp1 and Mp2 are field effect transistor pairs that require high characteristic relative accuracy, respectively. This is because in the MOSFET differential amplifier 100, important circuit characteristics such as the input offset voltage are determined by the characteristic relative accuracy of these field effect transistor pairs.

  Conventionally, in order to increase the characteristic relative accuracy of a field effect transistor pair, as disclosed in Patent Documents 1 to 5, for example, a first field effect transistor and a second field effect transistor that constitute the field effect transistor pair Is used, and a plurality of divided field effect transistor elements are connected in parallel to each other. As a result, the characteristic variations of the individual field effect transistors after the division are canceled out, and the characteristic relative accuracy of the field effect transistor pair is improved because it acts to approach the center value.

  Further, as a layout technique for improving the characteristic relative accuracy of a pair of field effect transistors, Patent Document 4 discloses that each of a first field effect transistor and a second field effect transistor forming a plurality of pairs is divided by a center of gravity. A layout technique has been disclosed in which the positions are symmetrically arranged so that the positions are common.

  As an example, FIG. 10 shows an arrangement example when the number of divisions is “2”.

  In the circuit example shown in FIG. 10, the gate electrode width of the first field effect transistor is divided into two to form field effect transistors M1a and M1b, and the gate electrode width of the second field effect transistor is divided into two. Thus, field effect transistors M2a and M2b are configured. The first field effect transistor M1a and the second field effect transistor M2b are formed on the left and right sides with a common source electrode S therebetween, and the drain electrodes D1 and D2 are formed on both outer sides. Below that, a second field-effect transistor M2a and a first field-effect transistor M1b are formed on the left and right sides with a common source electrode S interposed therebetween, and the drain electrodes D2 and D1 are provided on both sides. Is formed. Thus, the first field effect transistors M1a and M1b and the second field effect transistors M2a and M2b are arranged point-symmetrically, respectively.

  As a layout technique for improving the characteristic relative accuracy of a pair of field effect transistors, Patent Document 5 discloses a first field effect in which, after division, the sum of position coordinate values in the gate electrode length direction of a field effect transistor forms a pair. A layout technique in which the transistors and the second field effect transistors are arranged to be equal to each other is disclosed.

  Generally, when configuring a differential amplifier circuit, a current mirror circuit, etc. in a semiconductor integrated circuit, the characteristic relative accuracy of the field effect transistor pair is poor, and the first field effect transistor and the second field effect transistor forming a pair If a large difference occurs in the current value between the two, the circuit performance deteriorates, and further, the yield of the semiconductor integrated circuit is reduced. In order to avoid this, there are methods in which the gate electrode length and the gate electrode width are designed to be large. However, these methods have a problem of increasing the area occupied by the circuit.

The layout technique disclosed in Patent Document 5 is a technique that overcomes the above-described problem, and does not increase the total gate electrode area of a pair of field effect transistors, and the field effect transistors can be arranged by dividing each field effect transistor. The characteristic relative accuracy of the transistor pair is improved.
JP-A-4-73961 JP-A-5-243865 JP-A-8-116222 JP 2000-91504 A JP 2000-36582 A

  In the above-described prior art, in order to improve the characteristic relative accuracy of each field effect transistor pair that plays an important role in stabilizing the circuit characteristics, the first field effect transistor and the second field effect that form a pair are used. Each of the divided field effect transistors is arranged so that each transistor is divided and connected in parallel to each other and has symmetry in the adjacent distance.

  In general, increasing the total gate electrode area of each field effect transistor pair has the effect of improving the relative accuracy of characteristics, but causes a problem of increasing the area occupied by the field effect transistor on the semiconductor integrated circuit. Therefore, it is desirable to divide the total gate electrode area as a fixed value determined in advance by circuit operation, circuit area, power consumption, etc., and to arrange the divided field effect transistors.

  Actually, when designing these circuits, it is necessary to determine the number of divisions of the field effect transistor or to determine the gate electrode width as a division unit. However, the number of field effect transistor divisions or the gate electrode width as a division unit can be determined by a method in which a circuit designer specifies only the smallest divided gate electrode width, or the occupied area efficiency after layout for a given arrangement region. It is determined by the method of dividing considering the above.

  However, when determining the number of field-effect transistor divisions and the gate electrode width as the division unit by these methods, the relative variations in characteristics of field-effect transistor pairs due to manufacturing variations and the variations in circuit characteristics of the target circuit In consideration of the influence on the gate electrode, there is a problem that the gate electrode width is not necessarily the optimum number of divisions or division units of the field effect transistor.

  Also, with respect to the resistor element pair constituting the semiconductor integrated circuit, the relative characteristic accuracy tends to be improved by designing the length of the resistor element and the width of the resistor element to be large as in the case of the field effect transistor pair. Also in this case, in order to prevent the area occupied by the resistance elements on the semiconductor integrated circuit, the layout technique in which the first resistance elements and the second resistance elements constituting the resistance element pair are divided into a plurality of parts and are alternately arranged. Is used. Therefore, it is necessary to determine the number of divisions for this resistive element pair, and the same problem as in the case of the field effect transistor pair arises.

  The present invention solves the above-described conventional problems, and provides an optimum field effect that provides the highest characteristic relative accuracy for each field effect transistor pair that requires high characteristic relative accuracy in a semiconductor integrated circuit. Semiconductor integrated circuit design apparatus, semiconductor integrated circuit design method, semiconductor integrated circuit current value relative variation characteristic evaluation method, semiconductor integrated circuit, which determines transistor division number and automatically performs circuit design using the obtained division number An object of the present invention is to provide a resistance value relative variation characteristic evaluation method, a semiconductor integrated circuit manufacturing method, a control program for causing a computer to execute these, and a readable recording medium on which the control program is recorded.

  In the semiconductor integrated circuit design method of the present invention, a field effect transistor pair including a first field effect transistor and a second field effect transistor having the same conductivity type and the same gate electrode size is disposed on a semiconductor substrate, Each of the field effect transistor and the second field effect transistor is a computer integrated with a semiconductor integrated circuit configured by connecting n field effect transistor elements (n is an integer of 1 or more) divided in the gate electrode width direction in parallel. A semiconductor integrated circuit design method for automatically designing using a first and second field effect transistors caused by manufacturing variations when determining the number of divisions of the field effect transistors The current value relative variation between and is expressed as a function of the number of divisions, and the number of divisions that minimizes the current value relative variation is calculated. Management unit is derived mathematically, automatically designing a semiconductor integrated circuit by using the division number derived, the objects can be achieved.

  According to a method for evaluating a current value relative variation characteristic of a semiconductor integrated circuit according to the present invention, a field effect transistor pair including a first field effect transistor and a second field effect transistor having the same conductivity type and the same gate electrode size is provided on a semiconductor substrate. Each of the first field effect transistor and the second field effect transistor is configured by connecting in parallel n (n is an integer of 1 or more) field effect transistor elements divided in the gate electrode width direction. A semiconductor integrated circuit current value relative variation characteristic evaluation method for automatically evaluating a current value relative variation characteristic for a semiconductor integrated circuit using a computer, wherein the semiconductor substrate includes an N-type field effect transistor pair and a P-type When at least one of the pair of field effect transistors is formed, the N-type and P-type field effects For at least one of the pair of transistors, a current value relative variation between the first field effect transistor and the second field effect transistor under a certain power supply voltage condition, and a value obtained by dividing 1 by the square root of the gate electrode area The graph indicating the relationship is approximated by the arithmetic processing unit using the following formula (1) to model the current value relative variation characteristics, thereby achieving the above object.

Where σ _Ids : current value relative variation (standard deviation value),
α, β: Variables (fitting parameters) to match the measured characteristic values
L: gate electrode length,
W: The gate electrode width.

  Preferably, at least one of the N-type and P-type field effect transistor pairs in the current value relative variation characteristic evaluation method for a semiconductor integrated circuit according to the present invention, the first field effect transistor and the second field effect transistor are used. The fitting parameter β in the equation (17) is expressed as follows for a plurality of graphs showing the relationship between the current value relative variation between and the value obtained by dividing 1 by the square root of the gate electrode area for each power supply voltage condition. The current value relative variation characteristic is modeled by approximating the fixed value by changing only the fitting parameter α.

  Preferably, in the semiconductor integrated circuit design method of the present invention, at least one of the N-type and P-type field effect transistor pairs using the current value relative variation characteristic evaluation method for a semiconductor integrated circuit according to claim 2. In this case, the fitting parameter β is extracted by the above equation (1), and at least one of the N-type and P-type field effect transistor pairs has a current value relative variation when the division number is 1, and a plurality of The ratio of the current value relative variation in the case of division is expressed by the following equation (2) using the number of divisions and the extracted fitting parameter β as a variable, and the number of divisions at which the ratio is maximum The number of divisions that minimizes the current value relative variation is determined.

Where R (N): a function representing a ratio of relative variations in current value with the number of divisions N as a variable,
N: the number of divisions related to the gate electrode width, an integer of 1 or more,
σ _{Ids, 1} : current value relative variation (standard deviation value) without division,
σ _{Ids, N} : current value relative variation (standard deviation value) when divided into N pieces,
β: fitting parameter,
L: gate electrode length,
W: The gate electrode width.

  Preferably, for at least one of the N-type and P-type field effect transistor pairs in the semiconductor integrated circuit design method of the present invention, a real value is obtained using the gate electrode area and the extracted fitting parameter β. If the real value is 1 or less, the number of divisions is 1. When the real value is greater than 1, the smallest integer greater than or equal to the real value and the maximum less than or equal to the real value By substituting an integer into the formula (2), the integer with the larger result of the current value relative variation ratio is determined as the division number that minimizes the current value relative variation.

Where M is a real number,
N _i , N _{i + 1} : integer,
β: fitting parameter,
S: gate electrode area,
L: gate electrode length,
W: The gate electrode width.

  According to the semiconductor integrated circuit design method of the present invention, a resistive element pair consisting of a first resistive element and a second resistive element having the same size is disposed on a semiconductor substrate, and the first resistive element and the second resistive element Is a semiconductor integrated circuit design method for automatically designing, using a computer, a semiconductor integrated circuit in which n resistance elements (n is an integer of 1 or more) divided in the length direction of the resistance elements are connected in series Then, when determining the number of divisions of the resistance element, the relative variation in resistance value between the first resistance element and the second resistance element caused by the manufacturing variation is a function of the number of divisions. The arithmetic processing unit mathematically derives the division number that minimizes the relative variation of the resistance value, and automatically designs the semiconductor integrated circuit using the derived division number, thereby achieving the above object.

  According to the semiconductor integrated circuit resistance value variation characteristic evaluation method of the present invention, a resistance element pair consisting of a first resistance element and a second resistance element having the same size is disposed on a semiconductor substrate, and the first resistance element and Relative variation in resistance value with respect to a semiconductor integrated circuit in which n resistance elements (n is an integer of 1 or more) divided in the length direction of the resistance elements are connected in series. A resistance-relative variation characteristic evaluation method for a semiconductor integrated circuit that automatically evaluates a characteristic using a computer, wherein the resistance element pair is between a first resistance element and a second resistance element under a certain power supply voltage condition. Is approximated using the following equation (4) by the arithmetic processing unit to a graph showing the relationship between the relative resistance value variation and the value obtained by dividing 1 by the square root of the area of the resistance element. For characteristic modeling the above-described object can be achieved.

However, σ _R : Relative variation of resistance value (standard deviation value),
α, β: Variables (fitting parameters) to match the measured characteristic values
L: length of the resistance element,
W: The width of the resistance element.

  Preferably, for the resistance element pair in the resistance value variation characteristic evaluation method for a semiconductor integrated circuit according to the present invention, the resistance value relative variation between the first resistance element and the second resistance element, and 1 is the resistance element. Approximating the relationship with the value divided by the square root of the area for each of the power supply voltage conditions by changing only the fitting parameter α, with the fitting parameter β in the equation (4) as a fixed value. By doing so, the resistance value relative variation characteristic is modeled.

  Preferably, in the method for designing a semiconductor integrated circuit according to the present invention, the resistance element pair is fitted by the equation (4) using the resistance value relative variation characteristic evaluation method of the semiconductor integrated circuit according to claim 7. The parameter β is extracted, and the ratio between the resistance value relative variation when the number of divisions is 1 and the resistance value relative variation when divided into a plurality of the resistance element pairs is extracted as the number of divisions. The fitting parameter β is used to represent the number of divisions as a variable by the following equation (5), and the number of divisions having the maximum ratio is determined as the number of divisions that minimizes the relative resistance variation. Semiconductor integrated circuit design method.

Where R (N): a function representing the ratio of relative variation in resistance value with the number of divisions N as a variable,
N: the number of divisions relating to the length of the resistance element, an integer of 1 or more
σ _{R, 1} : Resistance value relative variation (standard deviation value) without division,
σ _{R, N} : Resistance value relative variation (standard deviation value) when divided into N pieces,
β: fitting parameter,
L: length of the resistance element,
W: The width of the resistance element.

  Preferably, for the resistor element pair in the semiconductor integrated circuit design method of the present invention, a real value is obtained by the following equation (6) using the area of the resistor element and the extracted fitting parameter β. When the numerical value is 1 or less, the number of divisions is set to 1. When the real value is greater than 1, the smallest integer that is greater than or equal to the real value and the largest integer that is less than or equal to the real value are substituted into the equation (5). Thus, the integer with the larger result of the resistance value relative variation ratio is determined as the division number that minimizes the resistance value relative variation.

Where M is a real number,
Ni, Ni + 1: integer,
β: fitting parameter,
S: area of the resistance element,
L: length of the resistance element,
W: The width of the resistance element.

  The control program of the present invention is a program for causing a computer to execute the processing procedure of the method according to any one of claims 1 to 10, thereby achieving the above object.

  A readable recording medium of the present invention is a computer-readable recording medium in which the control program according to claim 11 is recorded, whereby the above object is achieved.

  The method of manufacturing a semiconductor integrated circuit according to the present invention includes circuit information reflecting the number of divisions obtained by the processing procedure of the semiconductor integrated circuit design method according to any one of claims 1, 4, 5, 6, 9, and 10. Based on this, a semiconductor integrated circuit is manufactured, thereby achieving the above object.

  The semiconductor integrated circuit design apparatus of the present invention requires characteristic relative accuracy from circuit information including a circuit configuration of a semiconductor integrated circuit to be designed and at least one element size of each field effect transistor element and resistor element. Circuit information reflecting the division number obtained by using the semiconductor integrated circuit design method according to at least one of claims 1 and 6 is generated for at least one of all field effect transistor pairs and resistor element pairs. An arithmetic processing unit is provided, thereby achieving the above object.

  The operation of the present invention will be described below with the above configuration.

  In the semiconductor integrated circuit design method of the present invention, a field effect transistor pair including a first field effect transistor and a second field effect transistor having the same conductivity type and the same gate electrode size is disposed on a semiconductor substrate. Each of the first field effect transistor and the second field effect transistor of the transistor pair includes a plurality of field effect transistors divided in the gate electrode width direction, connected in parallel to each other, or one field effect without being divided. In designing a semiconductor integrated circuit composed of transistors, when determining the number of divisions, the standard deviation of the current difference between the first field effect transistor and the second field effect transistor due to manufacturing variations is determined. A value (hereinafter referred to as a current value relative variation characteristic) is expressed as a function of the number of divisions. The number of divisions that minimizes the current value relative variation is mathematically derived, and the circuit design is performed using the obtained optimum number of divisions.

  Specifically, for each of the N-type field effect transistor pair and the P-type field effect transistor pair, the current value relative variation between the first field-effect transistor and the second field-effect transistor is approximated using a mathematical formula. To model the current value relative variation characteristics. Using the gate electrode area of the target field effect transistor pair and the fitting parameters extracted from the model formula, obtain the number of divisions that minimize the relative variation in current value from the formula, and design the circuit using the obtained number of divisions. Do.

  Similarly, in the method of designing a semiconductor integrated circuit according to the present invention, a resistor element pair having the same size and formed of a first resistor element and a second resistor element formed on a semiconductor substrate is disposed. Each of the first resistive element and the second resistive element is composed of a plurality of resistive elements divided in the length direction of the resistive elements, which are connected in series to each other, or are constituted by a single resistive element without being divided. In designing a semiconductor integrated circuit, when determining the number of divisions, the standard deviation value of the resistance difference between the first resistance element and the second resistance element due to manufacturing variations (hereinafter referred to as resistance value relative variation characteristics). Is expressed as a function of the number of divisions. The number of divisions that minimizes the relative variation in resistance value is mathematically derived, and circuit design is performed using the obtained optimum number of divisions.

  Specifically, for each of the resistance element pairs, the resistance value relative variation between the first resistance element and the second resistance element is modeled by approximating using a mathematical formula, and the resistance value relative variation characteristic is expressed. evaluate. Using the area of the target resistance element and the fitting parameter extracted from the model equation, the number of divisions that minimizes the relative variation in resistance value is obtained by an equation, and the circuit design is performed using the obtained number of divisions.

  In the semiconductor integrated circuit design apparatus of the present invention, the circuit configuration and each electric field are determined using the semiconductor integrated circuit design method for determining the optimum number of divisions that minimizes the relative variation between the field effect transistor pair and the resistor element pair. For the input circuit information in which the size of the effect transistor element and the resistance element is determined, for each field effect transistor pair and the resistance element pair that require characteristic relative accuracy, It is possible to divide by the optimum division number and generate circuit information reflecting the division number.

  According to the present invention, mathematical operations are performed based on the relative characteristic variations of the N-type and P-type field effect transistor pairs inherent in the semiconductor integrated circuit manufactured by the production factory and the manufacturing process and the characteristic relative variations of the resistance element pairs. A statistically optimal number of partitions is determined. As a result, the influence due to the manufacturing variation is reduced, the circuit characteristic variation is small, and a stable semiconductor integrated circuit can be obtained.

  According to the present invention, based on the characteristic relative variation of each of the N-type and P-type field effect transistor pairs inherent in the semiconductor integrated circuit manufactured by the production factory / manufacturing process and the characteristic relative variation of the resistance element pairs, It is possible to determine the number of divisions of each element pair that minimizes the relative variation characteristic, and to design a circuit using the obtained optimum number of divisions. Further, it is possible to realize a semiconductor integrated circuit design apparatus that can automatically divide field effect transistor pairs and resistor element pairs by an optimum division number by using the semiconductor integrated circuit design method of the present invention. As a result, it is possible to reduce the influence on the circuit characteristics due to the manufacturing variation, to obtain a semiconductor integrated circuit in which the circuit characteristic variation is small and the operation is stable, and the yield can be improved.

Hereinafter, a semiconductor integrated circuit design method and a semiconductor integrated circuit current evaluation method of a semiconductor integrated circuit according to a first embodiment of the present invention, a semiconductor integrated circuit design apparatus according to a second embodiment of the present invention using the method, and a further Embodiment 3 of a semiconductor integrated circuit design method and a semiconductor integrated circuit resistance value relative variation characteristic evaluation method will be sequentially described with reference to the drawings.
(Embodiment 1)
In this first embodiment, an embodiment of a method for designing a semiconductor integrated circuit and a method for evaluating a current value relative variation characteristic of a semiconductor integrated circuit according to the present invention will be described.

  FIG. 1 is a flowchart showing an outline of a processing procedure of a semiconductor integrated circuit design method and a current value relative variation characteristic evaluation method of a semiconductor integrated circuit according to the present embodiment.

  Hereinafter, each processing procedure of the semiconductor integrated circuit design method and the current value relative variation characteristic evaluation method of the semiconductor integrated circuit according to the first embodiment will be described in order with reference to the flowchart of FIG. 1 indicates a preparatory stage for carrying out the semiconductor integrated circuit design method and the current value relative variation characteristic evaluation method of the semiconductor integrated circuit of the first embodiment, and the solid line B in FIG. The portions enclosed by the squares indicate the processing procedures of the semiconductor integrated circuit design method and the current value relative variation characteristic evaluation method of the semiconductor integrated circuit according to the first embodiment.

  First, a preparation stage for carrying out the semiconductor integrated circuit design method of the first embodiment and the current value relative variation characteristic evaluation method of the semiconductor integrated circuit, which is a portion surrounded by a broken line A in FIG. 1, will be described.

  As shown in FIG. 1, first, in step S11, as a relative accuracy evaluation circuit, a plurality of types of N-type / P-type field effect transistor pairs of gate electrode lengths and gate electrode widths are used, as shown in FIG. A current mirror circuit 10 is fabricated on the same semiconductor substrate. In the current mirror circuit 10 of FIG. 2, a first field effect transistor M1 and a second field effect transistor M2 of the same conductivity type are connected between an input terminal of a power supply voltage VDD and a connection terminal of a ground potential (ground). The gate electrodes of the commonly connected field effect transistors M1 and M2 are connected to a connection point between the power supply voltage side terminal and the power supply voltage input terminal of the first field effect transistor M1.

  Next, in step S12, the current values of the first field effect transistor M1 and the second field effect transistor M2 are set for each evaluation circuit fabricated in step S11 under a plurality of power supply voltage (VDD) conditions. taking measurement. For each of the N-type / P-type field effect transistors forming a pair, the current value relative variation characteristics in the field effect transistor pair of each gate electrode size are represented by the reciprocal of the square root of the gate electrode area of the field effect transistor pair as the X axis. The evaluation is performed by plotting the current value relative variation on the graph using the Y axis.

  On the other hand, circuit information of the semiconductor integrated circuit to which the semiconductor integrated circuit design method and the semiconductor integrated circuit current value relative variation characteristic evaluation method of the first embodiment are applied is prepared as follows.

  First, in step S21, the circuit configuration of the semiconductor integrated circuit is determined. Specifically, connection information such as a field effect transistor element, a resistance element, and a capacitor element is determined.

  Next, in step S22, circuit simulation is performed on the semiconductor integrated circuit whose circuit configuration has been determined. Based on the circuit simulation result, the gate electrode length and the gate electrode width of each field effect transistor element constituting the target circuit are determined so that the circuit characteristics satisfy the design specification. Hereinafter, the gate electrode length and the gate electrode width of each field effect transistor element are collectively referred to as “size information”.

  Further, in step S23, size information is acquired only for element pairs that have an influence on circuit operation and circuit characteristics and require relative accuracy from among the size information of all elements constituting the target circuit.

  The above processing steps are the processing procedure relating to the preparation stage for determining the number of divisions that minimize the characteristic relative variation in the semiconductor integrated circuit design method of the first embodiment.

  Next, each processing procedure relating to the semiconductor integrated circuit design method of the first embodiment and the current value relative variation characteristic evaluation method of the semiconductor integrated circuit, which is a portion surrounded by a solid line B in FIG.

  FIG. 3 shows an example of the results of evaluating the current value relative variation characteristics of a field effect transistor pair of each gate electrode size under the condition that the applied power supply voltage (Vdd) is constant for the N-type field effect transistor pair. It is a graph to show. The X axis in FIG. 3 represents the reciprocal of the square root of the gate electrode area of the field effect transistor pair, and the Y axis represents the current value relative variation (standard deviation value).

  As shown in FIG. 3, the measured current value relative variation characteristic can be modeled by approximating it using the following equation (1).

  However, σIds: current value relative variation (standard deviation value), α, β: fitting parameter, L: gate electrode length, W: gate electrode width.

Where σ _Ids : current value relative variation (standard deviation value),
α, β: Variables (fitting parameters) to match the measured characteristic values
L: gate electrode length,
W: The gate electrode width.

  In step S30 in FIG. 1, the fitting parameters α and β shown in the above equation (1) are extracted for each of the N-type / P-type field effect transistor pairs. Generally, when the power supply voltage (Vdd) condition is changed, the current value relative variation characteristic also changes. However, the dependence on the power supply voltage (Vdd) can be increased by using only the fitting parameter α shown in the above equation (1). Can be combined. Accordingly, the fitting parameter β is uniquely determined for an arbitrary power supply voltage (Vdd), and the value of the fitting parameter β is determined for each of the N-type and P-type field effect transistor pairs.

  FIG. 4 is a graph showing an example of the result of evaluating the current value relative variation characteristics of a field effect transistor pair of each gate electrode size for a plurality of power supply voltage (Vdd) conditions for an N-type field effect transistor pair. . The X axis in FIG. 4 represents the reciprocal of the square root of the gate electrode area of the field effect transistor pair, and the Y axis represents the current value relative variation (standard deviation value). The plurality of curves shown in FIG. 4 match the dependency of the current value relative variation characteristics on the power supply voltage (Vdd) by varying the fitting parameter α with the fitting parameter β shown in the above equation (1) as a fixed value. It is complicated.

  Next, the principle of the semiconductor integrated circuit design method of the first embodiment will be described before describing the division number determination process in step S40 of FIG.

  In general, the reason why each of the paired first and second field effect transistors is divided and connected in parallel to each other is that the variation in characteristics of the individual field effect transistors after the division is offset, and the central value thereof This is because the characteristic relative accuracy of the field effect transistor pair is improved as a result.

  Hereinafter, the division of the field effect transistor and the relative variation characteristics thereof will be described with reference to FIG.

  FIG. 5A is a perspective view showing the field effect transistor before division, and the gate electrode length is L and the gate electrode width is W. FIG.

FIG. 5B is a diagram showing the field effect transistor after the field effect transistor shown in FIG. 5A is divided into N pieces. The length of the gate electrode of each field effect transistor is L, and the width of each gate electrode is W _N. It is. However, W _N = W / N.

C of FIG. 5 is a diagram showing a field effect transistor serving as a structural unit shown by B in FIG. 5, the gate electrode length L, the gate electrode width is W _N.

Here, current value relative variations (standard deviation values) σ _{A to} σ _C in a current mirror circuit in which a field effect transistor pair is configured by the field effect transistors A to C shown in FIG. 5 will be described.

In the current mirror circuit in which the field effect transistor pair is configured by the field effect transistor of A shown in FIG. 5, the current value relative variation σ _A can be expressed by the following equation (7).

However, ΔIds: current difference between the first and second field effect transistors.

Similarly, in the current mirror circuit in which the field effect transistor pair is configured by the C field effect transistor shown in FIG. 5, the current value relative variation σ _cC can be expressed by the following equation (8).

Similarly, in the current mirror circuit in which the field effect transistor pair is configured by the field effect transistor of B shown in FIG. 5, the current value relative variation σ _B can be expressed by the following equation (9).

Where S _ii : the dispersion value of the current value of the i-th field effect transistor,
S _ij : A covariance value of the current value of the i-th field effect transistor and the current value of the j-th field effect transistor.

In general, each of N field effect transistors is arranged at an adjacent distance (for example, a distance of 10 μm or less of an element isolation region between adjacent elements) in the same chip on the same semiconductor substrate. It may be assumed that the effect transistors vary in current value without correlation with each other. Therefore, S _ij = 0 (1 ≦ i, j ≦ N). Further, since each N field effect transistors have the same gate electrode size, it may be assumed that the dispersion values of the current values of the N field effect transistors are all equal. Therefore, S ₁₁ = S ₂₂ =... = S _ii =... = S _NN (1 ≦ i, j ≦ N). Therefore, the above equation (9) can be approximated as the following equation (10) using the above equation (8).

Next, a processing procedure for obtaining the number of divisions that minimizes the relative variation in the current value of the field effect transistor pair in step S40 of FIG. 1 will be described.

  First, a function represented by the following formula (2), where the ratio between the current value relative variation before the division of the field effect transistor and the current value relative variation after the field effect transistor is divided into N pieces, is defined with the division number N as a variable. Expressed by the formula. Since the current value relative variation before the division is a fixed value, the ratio function R (N) becomes the maximum when the current value relative variation after the N division becomes the minimum. What is necessary is just to obtain | require the division | segmentation number N.

However, R (N): a function representing a ratio of current value relative variation with the number of divisions N as a variable,
N: the number of divisions related to the gate electrode width, an integer of 1 or more,
σ _{Ids, 1} : current value relative variation (standard deviation value) without division,
σ _{Ids, N} : current value relative variation (standard deviation value) when divided into N pieces,
β: fitting parameter,
L: gate electrode length,
W: The gate electrode width.

  FIG. 6 shows an example in which the gate electrode length L = 2 [um], the gate electrode width W = 40 [um], and the fitting parameter β = 5 in the N-type field effect transistor pair, and the division number N is taken as the X axis. The graph which made the value of ratio function R (N) the Y-axis is shown.

  From the graph of FIG. 6, it can be seen that the ratio function R (N) is maximized when N = 3, and the division number N = 3 that minimizes the relative variation of the current value of the field effect transistor pair is obtained. Further, since the value of the ratio function R (N) at that time is about 1.15, it can be said that the current value relative variation after the division is reduced to 87% as compared with that before the division. Further, as in the prior art shown in FIG. 10 described above, by applying a layout technique in which each field effect transistor constituting the field effect transistor pair is arranged point-symmetrically so as to have a common center of gravity, further current can be obtained. It is possible to reduce the relative variation of values.

  Next, in order to obtain mathematically the division number N that minimizes the relative variation in the current value of the field effect transistor pair, a first-order differentiation with respect to the variable N is performed on the ratio function R (N) of the above equation (2). Then, a primary differential function R ′ (N) of the ratio function R (N) shown in the following formula (11) is obtained.

When the primary differential function of the above equation (11) is R ′ (N) = 0, the ratio function R (N) is maximized.

Here, since the obtained division number N is not necessarily an integer, the division number N is replaced with a real number M as shown in the following formula (3).

Where M is a real number,
N _i , N _{i + 1} : integer,
β: fitting parameter,
S: gate electrode area,
L: gate electrode length,
W: The gate electrode width.

When the real number M is 1 or less, the division number N is set to 1. When the real number M is greater than 1, the smallest integer N _{i + 1} that is greater than or equal to the real number M and the largest integer N _i that is less than or equal to the real number M are substituted into the functional expression shown in the above equation (2). Then, the integer with the larger result of the current value relative variation ratio is determined as the division number N that minimizes the current value relative variation.

  FIG. 7 is a graph of a primary differential function R ′ (N), which is a result of primary differentiation of the graph of the ratio function R (N) shown in FIG. 6, and the ratio function R (N) with the division number N as the X axis. Is the Y-axis.

From the graph shown in FIG. 7, when the division number N is replaced with the real number M, it can be seen that the primary differential function R ′ (N) becomes “0” when M = 3.2. The minimum integer Ni + 1 = 4 that is greater than or equal to the real value M, and the maximum integer Ni = 3 that is less than or equal to the real value M, satisfying N _i ≦ M ≦ N _{i + 1} , is assigned to the functional equation shown in the above equation (2). As a result, since the value of the ratio function R (N) is larger when N = 3, the number of divisions N = 3 that minimizes the current value relative variation is determined in step S40.

  According to the method for deriving the division number N described above, the fitting parameter β is extracted using the above equation (1), which is a model equation approximating the actually measured current value relative variation characteristics, and the relative accuracy is obtained from the target circuit. It is necessary to acquire element size information (gate electrode length and gate electrode width) of a field effect transistor pair that requires By substituting those information into the above equation (3), the real number M that is the basis for determining the optimum division number N in circuit design can be obtained by a very simple calculation process. Therefore, it is possible to determine the optimum number of divisions for all element pairs that require relative accuracy in a very short calculation processing time.

  Next, in step S50, it is confirmed whether or not the obtained division number N is 2 or more. In other words, it is confirmed whether or not the division number N is 1. The division number N is 1 when the real number M obtained from the above equation (3) is 1 or less, or when the real number M is 1 or more and 2 or less, and the integers 1 and 2 are set as above. As a result of substituting for (2), the ratio function R (N) is larger when N = 1. In any case, it can be said that the field effect transistor size before the division is too small because the relative variation increases by dividing the field effect transistors constituting the field effect transistor pair into two or more. Therefore, when the obtained division number N is 1, each element constituting the target circuit is performed by considering the influence on the circuit operation and the circuit characteristics by returning to step S22 and executing the circuit simulation. The size of the needs to be reviewed. If the obtained division number N is 2 or more, the process proceeds to the next step S60.

Finally, in step S60, the target circuit (circuit information) has optimum division number information by reflecting the information on the division number N obtained in step S50 on each element pair. Thereby, the processing of the semiconductor integrated circuit design method of the first embodiment is completed.
(Embodiment 2)
In the second embodiment, a semiconductor integrated circuit design apparatus having a function of dividing a field effect transistor constituting a field effect transistor pair by an optimum division number using the semiconductor integrated circuit design method described in the first embodiment will be described. To do.

  FIG. 8 is a block diagram showing a schematic configuration of the semiconductor integrated circuit design apparatus according to the second embodiment. In FIG. 8, the solid line arrows indicate the flow of data, and the broken line arrows indicate the instruction output from the control unit 2 using a keyboard and a mouse, or the like on the screen of the display unit 3 that performs display using a CRT, a liquid crystal display, or the like. Indicates the output of the processing result.

  In FIG. 8, the semiconductor integrated circuit design apparatus 1 is configured by a computer system, and is processed by a control unit 2 that outputs an operation command input by a circuit designer as a control instruction using a keyboard, a mouse, or the like, and a CRT or a liquid crystal display. A data input unit 4 including a display unit 3 for displaying the result on a screen, a network interface such as LAN and GPIB, an interface such as USB, and an interface of a readable storage medium such as a magnetic disk (FD) and an optical disk (CD). And a data output unit 5 and an arithmetic processing unit 6 that performs arithmetic processing by a CPU (central processing unit). The data input unit 4 and the data output unit 5 may be the same interface.

  The arithmetic processing unit 6 includes a fitting parameter (α, β) extracting unit 61, an element pair size information acquiring unit 62, based on a control program and its data in a storage means (ROM) as a readable recording medium (not shown). Each function of the division number (N) calculation unit 63 and the circuit information synthesis unit 64 is executed. The storage means (ROM) is composed of a hard disk, a magnetic disk (FD), an optical disk (CD), and the like, from which a control program and its data in the storage means (ROM) are read out via a data reproducing device. By storing the data in the work memory (RAM), the arithmetic processing unit 6 including a CPU executes the functions of the respective units using the control program and data in the RAM.

  The fitting parameter (α, β) extraction unit 61 minimizes an error between the current value relative variation characteristic at each gate electrode size of the field effect transistor pair and the current value relative variation characteristic obtained from the above equation (1). The values of the fitting parameters α and β are extracted.

  The element pair size information acquisition unit 62 acquires element pair size information that requires relative accuracy in terms of circuit characteristics.

  The division number (N) calculation unit 63 obtains a real value M that minimizes the relative variation of the current value from the fitting parameter β and the size information (gate electrode area) of the element pair using the above equation (3). . Further, in the division number (N) calculation unit 63, when the real value M is 1 or less, the division number is set to 1, and when the real value M is greater than 1, the smallest integer greater than or equal to the real value M and the real value thereof. Substituting the maximum integer less than or equal to M into Equation (2), the integer with the larger result of the current value relative variation ratio is determined as the division number N that minimizes the current value relative variation.

  The circuit information synthesis unit 64 reflects the division number N of each element pair from the division number (N) calculation unit 63 in the information on the gate electrode width W of the first and second field effect transistors constituting each element pair. Let

  The operation of the semiconductor integrated circuit design apparatus 1 according to the second embodiment will be described with the above configuration.

  First, each N-type / P-type field effect transistor pair having a plurality of types of gate electrode sizes was measured under a plurality of power supply voltage (Vdd) conditions. The current value relative variation characteristic information is transmitted from the data input unit 4 in the semiconductor integrated circuit design device 1 to the fitting parameter (α, β) extraction unit 61.

  In the fitting parameter (α, β) extraction unit 61, the variable range of each value of the fitting parameters α and β in the above equation (1) is input from the control unit 2, and is applied to each N-type / P-type field effect transistor pair. On the other hand, in the variable range input from the control unit 2, the measured current value relative variation characteristic at each gate electrode size of the field effect transistor pair and the current value relative variation characteristic obtained from the above equation (1) The values of the fitting parameters α and β are extracted so that the error is minimized.

  The extraction result information is output on the display screen of the display unit 3, and the accuracy is checked by the design checker. When the error between the measured relative variation characteristics under a plurality of power supply voltage (Vdd) conditions and the current value relative variation characteristics obtained from the above equation (1) is sufficiently small (for example, 3% or less), then The values of the fitting parameters α and β in the above equation (1) are determined for each power supply voltage (Vdd) condition of the N-type / P-type field effect transistor. However, the value of the fitting parameter β is constant for each power supply voltage (Vdd) condition.

  On the other hand, circuit information (connection information of each element and size information of each element) of the target circuit in which the circuit configuration and the size of each element are determined is transferred from the data input unit 4 in the semiconductor integrated circuit design device 1 to the element pair. This is transmitted to the size information acquisition unit 62.

  In the element pair size information acquisition unit 62, an element pair that requires relative accuracy in terms of circuit characteristics is selected from all the elements of the target circuit by the circuit designer and input from the control unit 2. The size information of the selected element pair is supplied from the size information of all elements of the target circuit. Further, the size information of the element pair that requires relative accuracy in terms of circuit characteristics is displayed on the display screen of the display unit 3 and is confirmed by the circuit designer.

  In the division number (N) calculation unit 63, the information about the fitting parameter β output from the fitting parameter (α, β) extraction unit 61 and the size information acquisition unit 62 of the element pair are selected by the circuit designer. The size information of the element pair thus transmitted is transmitted to the division number (N) calculation unit 63.

  The division number (N) calculation unit 63 obtains a real number M as a basis for calculating the optimum division number N using the above equation (3) for the size information of each selected element pair. At this time, when the real number M is 1 or less, the division number N is set to 1. When the real number M is greater than 1, the smallest integer Ni + 1 that is greater than or equal to the real number M and the largest integer Ni that is less than or equal to the real number M. Is substituted into the function equation shown in the above equation (2), and the division number is determined by setting the integer with the larger current value relative variation ratio as the division number N that minimizes the current value relative variation. . Thus, the optimum division number N is automatically calculated.

  Further, the division number (N) calculation unit 63 determines whether or not the value of each division number corresponding to each element pair is 2 or more, and there is an element pair whose division number N is 1. In this case, the size information of the element pair whose division number N is 1 is displayed on the display unit 3 and is confirmed by the circuit designer. In this case, it is necessary to review the size of each element constituting the target circuit in consideration of the influence on circuit operation and circuit characteristics by executing circuit simulation.

  Further, when the division number (N) calculation unit 63 determines that the division number N of all the element pairs is 2 or more, the division number (N) calculation unit 63 determines the relative accuracy on the circuit characteristics. The required division number N of each element pair and the information of the divided gate electrode width are transmitted to the circuit information synthesis unit 64.

In the circuit information synthesis unit 64, the division number N of each element pair supplied from the division number (N) calculation unit 63 is obtained from the circuit information (elements) of all elements in the target circuit obtained via the data input unit 4. The connection information and element size information) are reflected. Specifically, in the circuit information (element connection information and element size information) of all elements in the target circuit obtained through the data input unit 4, each of the element pairs selected by the size information acquisition unit 62 is selected. For only the element pair, the division number N of each element pair from the division number (N) calculation unit 63 is reflected in the information on the gate electrode width W of the first and second field effect transistors constituting each element pair. Is done. Accordingly, the first and second field effect transistors constituting each element pair have information that N field effect transistors each having a gate electrode width W _N (W _N = W / N) exist. Is replaced by The final circuit information (element connection information and element size information) after being reflected in the circuit information synthesis unit 64 is displayed by the display unit 3 and the division number N is reflected by the circuit designer. It is confirmed whether or not it is circuit information.

  Finally, the finally generated circuit information reflecting the division number N of the target circuit is output from the circuit information synthesis unit 64 in the arithmetic processing unit 6 via the data output unit 5.

  Thus, the operation of the semiconductor integrated circuit design device 1 according to the second embodiment is completed.

In the first and second embodiments, the example in which the present invention is applied to determine the division number of the field effect transistor pair in the semiconductor integrated circuit has been described. However, the present invention is not limited to the resistor element pair in the semiconductor integrated circuit. It is applicable to. In the resistor element pair, as in the case of the field effect transistor pair, the characteristic relative accuracy tends to be improved by designing the length of the resistor element and the width of the resistor element to be large. In order to avoid an increase in the area occupied by the element pair, a layout technique is used in which the first resistance element pair and the second resistance element pair are divided into a plurality of parts and arranged alternately. The processing procedure of the semiconductor integrated circuit design method of the present invention is basically the same for the case of the field effect transistor pair and the case of the resistor element pair. In the field effect transistor pair, the relative accuracy of the characteristic is confirmed based on the standard deviation value (current value relative variation characteristic) of the current difference between the first field effect transistor pair and the second field effect transistor pair. Determine the number of divisions. On the other hand, in the resistance element pair, the characteristic relative accuracy is confirmed based on the standard deviation value (resistance value relative variation characteristic) of the resistance difference between the first resistance element pair and the second resistance element pair. To determine the number of divisions.
(Embodiment 3)
In the third embodiment, a semiconductor integrated circuit design method and a resistance value relative variation characteristic evaluation method of the semiconductor integrated circuit of the present invention will be described. Since it is basically the same as the semiconductor integrated circuit design method and the current value relative variation characteristic evaluation method of the semiconductor integrated circuit of the first embodiment, the difference between the case of the field effect transistor pair and the case of the resistor element pair is here. Only will be described using the flowchart shown in FIG.

  First, in step S11, as a relative accuracy evaluation circuit, a circuit having resistance element pairs of a plurality of types (lengths and widths) is manufactured on the same semiconductor substrate.

  Next, in step S12, the resistances of the first resistance element and the second resistance element constituting each resistance element pair are evaluated for each evaluation circuit manufactured in step S11 under a plurality of power supply voltage (VDD) conditions. Measure the value. For each of the resistor elements forming a pair, a graph showing the resistance value relative variation characteristics of the resistor element pairs of each element size with the reciprocal of the square root of the area of the resistor element pair as the X axis and the resistance value relative variation as the Y axis. Plot and evaluate.

  On the other hand, first, in step S21, the circuit configuration of the semiconductor integrated circuit is determined. Specifically, connection information such as a field effect transistor element, a resistance element, and a capacitor element is determined.

  In step S22, a circuit simulation is performed on the semiconductor integrated circuit whose circuit configuration has been determined. Based on the circuit simulation result, the size (element area) of each resistance element constituting the target circuit is determined so that the circuit characteristics satisfy the design specifications.

  In step S23, the size information is acquired only for the element pairs that have an influence on the circuit operation and the circuit characteristics and require the relative accuracy from the size information of all the elements constituting the target circuit.

  The processing steps up to the above are the processing procedures related to the preparation for determining the number of divisions that minimizes the characteristic relative variation in the semiconductor integrated circuit design method of the third embodiment.

  Next, processing procedures relating to the semiconductor integrated circuit design method and the resistance value relative variation characteristic evaluation method of the semiconductor integrated circuit according to the third embodiment will be described in order.

  The actually measured resistance value relative variation characteristic can be modeled by approximation using the following equation (4).

However, σ _R : Relative variation of resistance value (standard deviation value),
α, β: Variables (fitting parameters) to match the measured characteristic values
L: length of the resistance element,
W: The width of the resistance element.

  In step S30 of FIG. 1, the fitting parameters α and β shown in the above equation (4) are extracted for each resistance element pair.

  Next, in step S40 of FIG. 1, the number of divisions that minimizes the relative variation in the current value of the resistance element pair is obtained.

  First, the ratio between the resistance value relative variation before dividing the resistance element and the resistance value relative variation after dividing the resistance element into N pieces is expressed by a functional expression shown in the following equation (5) using the division number N as a variable. Represent. Since the resistance value relative variation before division is a fixed value, the ratio function R (N) is maximized when the resistance value relative variation after division into N is minimized. What is necessary is just to obtain | require the division | segmentation number N.

Where R (N): a function representing the ratio of relative variation in resistance value with the number of divisions N as a variable,
N: the number of divisions related to the length of the resistance element, an integer of 1 or more,
σ _{Ids, 1} : resistance value relative variation (standard deviation value) without division,
σ _{Ids, N} : Resistance value relative variation (standard deviation value) when divided into N pieces,
β: fitting parameter,
L: length of the resistance element,
W: The width of the resistance element.

  Next, in order to obtain the division number N that minimizes the resistance value relative variation of the resistance element pair mathematically, a first-order differentiation with respect to the variable N is performed on the ratio function R (N) of the above equation (5), A primary differential function R ′ (N) of the ratio function R (N) shown in the following formula (11) is obtained.

When the primary differential function of the above equation (11) is R ′ (N) = 0, the ratio function R (N) is maximized.

Here, since the obtained division number N is not necessarily an integer, the division number N is replaced with a real number M as shown in the following formula (6).

Where M is a real number,
N _i , N _{i + 1} : integer,
β: fitting parameter,
S: area of the resistance element,
L: length of the resistance element,
W: The width of the resistance element.

When the real number M is 1 or less, the division number N is set to 1. When the real number M is larger than 1, the smallest integer N _{i + 1} that is greater than or equal to the real number M and the largest integer N _i that is less than or equal to the real number M are substituted into the functional expression shown in the above equation (5). Then, the integer with the larger result of the resistance value relative variation ratio is determined as the division number N that minimizes the resistance value relative variation.

  According to the method for deriving the division number N described above, the fitting parameter β is extracted using the above equation (4), which is a model equation approximating the actually measured resistance value relative variation characteristic, and the relative accuracy is obtained from the target circuit. It is necessary to acquire element size information (resistance element length and resistance element width) of a resistance element pair that requires. By substituting such information into the above equation (6), the real number M that is the basis for determining the optimum division number N in circuit design can be obtained by a very simple calculation process. Therefore, it is possible to determine the optimum number of divisions for all element pairs that require relative accuracy in a very short processing time.

  In step S50, it is confirmed whether or not the obtained division number N is 2 or more. In other words, it is confirmed whether or not the division number N is 1. The division number N is 1 when the real number M obtained from the above equation (6) is 1 or less, or when the real number M is 1 or more and 2 or less, and the integers 1 and 2 are set as above. As a result of substituting into (5), the ratio function R (N) is larger when N = 1. In any case, dividing the resistive elements constituting the resistive element pair into two or more pieces increases the relative variation, so that it can be said that the size of the resistive element before the division is too small. Therefore, when the obtained division number N is 1, each element constituting the target circuit is performed by considering the influence on the circuit operation and the circuit characteristics by returning to step S22 and executing the circuit simulation. The size of the needs to be reviewed. When the obtained division number N is 2 or more, the process proceeds to the next step S60.

  Finally, in step S60, the target circuit (circuit information) has optimum division number information by reflecting the information on the division number N obtained in step S50 on each element pair. Thereby, the processing of the semiconductor integrated circuit design method of the third embodiment is completed.

  As described above, according to the first to third embodiments, the first field effect transistor and the second field effect transistor (or / and the first resistance element) having the same conductivity type and the same gate electrode size are formed on the semiconductor substrate. Field effect transistor pairs (or / and resistor element pairs) each including a second resistor element are arranged, and each field effect transistor pair (or / and resistor element pair) is arranged in the gate electrode width direction (or / and resistor element), respectively. In a semiconductor integrated circuit design method for designing a semiconductor integrated circuit in which a plurality of field effect transistor elements (or / and resistance elements) divided in the direction of the length are connected in parallel to each other, a field effect transistor ( Or / and the first electric field effect caused by manufacturing variations when determining the number of divisions of the resistance element) The current value relative variation between the transistor and the second field effect transistor (or / and the first resistance element and the second resistance element) is expressed as a function of the number of divisions, and the current value relative variation is minimized. The circuit is designed using the optimal number of divisions derived numerically. Thus, for each field effect transistor pair (or / and resistor element pair) that requires high characteristic relative accuracy in the semiconductor integrated circuit, the optimum field effect transistor (or the characteristic relative accuracy is highest) (or / And resistance elements) can be determined, and circuit design can be performed using the obtained optimal number of divisions.

  Although the field effect transistor element pair is described in the first embodiment and the resistance element pair is described in the third embodiment, the present invention is not limited to this, and the first and third embodiments may be combined.

  As mentioned above, although this invention has been illustrated using preferable Embodiment 1-3 of this invention, this invention should not be limited and limited to these Embodiment 1-3. It is understood that the scope of the present invention should be construed only by the claims. It is understood that those skilled in the art can implement an equivalent range based on the description of the present invention and the common general technical knowledge from the description of specific preferred embodiments 1 to 3 of the present invention. Patents, patent applications, and documents cited herein should be incorporated by reference in their entirety, as if the contents themselves were specifically described herein. Understood.

  The present invention relates to a semiconductor integrated circuit for reducing an influence caused by manufacturing variations of a field effect transistor pair and a resistor element pair that require high characteristic relative accuracy in an analog type or a mixed analog / digital type semiconductor integrated circuit. Field effect transistor pairs caused by manufacturing variations in the field of circuit design methods, semiconductor integrated circuit current value relative variation characteristic evaluation methods, semiconductor integrated circuit resistance value relative variation characteristic evaluation methods, and semiconductor integrated circuit design devices It is possible to reduce the influence on the circuit characteristics of the current value relative variation between the resistor elements and the resistance value relative variation between the pair of resistance elements. For this reason, a semiconductor integrated circuit with small variations in circuit characteristics and stable operation can be obtained, and the yield can be improved. Therefore, the present invention is widely used in analog type or mixed analog / digital type semiconductor integrated circuits that require a field effect transistor pair and a resistor element pair having high relative accuracy such as a differential amplifier circuit and a current mirror circuit. be able to.

4 is a flowchart for explaining each processing procedure of the semiconductor integrated circuit design method and the current value relative variation characteristic evaluation method of the semiconductor integrated circuit according to the first embodiment. FIG. 3 is a circuit diagram showing a configuration example of a current mirror circuit manufactured as a relative accuracy evaluation element in the current value relative variation characteristic evaluation method for the semiconductor integrated circuit according to the first embodiment. 6 is a graph showing modeling results (constant power supply voltage conditions) related to electrical characteristics in the current value relative variation characteristic evaluation method for the semiconductor integrated circuit according to the first embodiment. 5 is a graph showing modeling results (power supply voltage multiple conditions) regarding electrical characteristics in the current value relative variation characteristic evaluation method for the semiconductor integrated circuit according to the first embodiment. It is a perspective view for demonstrating the division | segmentation of the field effect transistor of this Embodiment 1. FIG. FIG. 5 is a diagram for explaining a relative variation ratio function in the semiconductor integrated circuit design method according to the first embodiment. FIG. 5 is a diagram for explaining a first-order differential function of a relative variation ratio function in the semiconductor integrated circuit design method of Embodiment 1. It is a block diagram which shows schematic structure of the semiconductor integrated circuit design apparatus of this Embodiment 2. It is a circuit diagram which shows an example of the conventional differential amplifier. It is a layout for demonstrating the common gravity center arrangement | positioning layout for aiming at the conventional characteristic stabilization.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor integrated circuit design apparatus 2 Control part 3 Display part 4 Data input part 5 Data output part 6 Arithmetic processing part 61 Fitting parameter ((alpha), (beta)) extraction part 62 Element pair size information acquisition part 63 Division | segmentation number (N) calculation part 64 Circuit information synthesis unit

Claims (14)

A field effect transistor pair including a first field effect transistor and a second field effect transistor having the same conductivity type and the same gate electrode size is disposed on a semiconductor substrate, and the first field effect transistor and the second field effect transistor are arranged. Semiconductor integrated circuit design for automatically designing a semiconductor integrated circuit in which n transistors (n is an integer of 1 or more) divided in the gate electrode width direction are connected in parallel using a computer A method,
When determining the division number of the field effect transistor, the current value relative variation between the first field effect transistor and the second field effect transistor caused by the manufacturing variation is expressed as a function of the division number. A semiconductor integrated circuit design method in which an arithmetic processing unit mathematically derives the number of divisions that minimizes the current value relative variation and automatically designs a semiconductor integrated circuit using the derived number of divisions. A field effect transistor pair including a first field effect transistor and a second field effect transistor having the same conductivity type and the same gate electrode size is disposed on a semiconductor substrate, and the first field effect transistor and the second field effect transistor are arranged. A computer shows a current value relative variation characteristic for a semiconductor integrated circuit in which n (n is an integer of 1 or more) field effect transistor elements each of which is divided in the gate electrode width direction are connected in parallel. A method for evaluating a current value relative variation characteristic of a semiconductor integrated circuit to be automatically evaluated by using,
When at least one of an N-type field effect transistor pair and a P-type field effect transistor pair is formed on the semiconductor substrate,
For at least one of the N-type and P-type field effect transistor pairs, the current value relative variation between the first field effect transistor and the second field effect transistor under a certain power supply voltage condition, and 1 as a gate The current value of the semiconductor integrated circuit that models the current value relative variation characteristics by approximating the graph showing the relationship with the value divided by the square root of the electrode area using the following equation (1) by the arithmetic processing unit Relative variation characteristic evaluation method.
Where σ _Ids : current value relative variation (standard deviation value),
α, β: Variables (fitting parameters) to match the measured characteristic values
L: gate electrode length,
W: The gate electrode width.   For at least one of the N-type and P-type field effect transistor pairs, the current value relative variation between the first field effect transistor and the second field effect transistor, and 1 divided by the square root of the gate electrode area. The current value is obtained by approximating the relationship with the measured value with respect to a plurality of graphs showing each power supply voltage condition, with the fitting parameter β in the above equation (1) as a fixed value and changing only the fitting parameter α. The method for evaluating a relative variation characteristic of a current value of a semiconductor integrated circuit according to claim 2, wherein the relative variation characteristic is modeled. A fitting parameter β is extracted from the equation (1) for at least one of the N-type and P-type field effect transistor pairs by using the current value relative variation characteristic evaluation method for a semiconductor integrated circuit according to claim 2. ,
For at least one of the N-type and P-type field effect transistor pairs, the ratio of the current value relative variation when the number of divisions is 1 and the current value relative variation when divided into a plurality of divisions is determined as the number of divisions. And the extracted fitting parameter β, the number of divisions is expressed as a variable by the following formula (2), and the number of divisions that maximizes the ratio is determined as the number of divisions that minimizes the relative variation in current value. 2. The semiconductor integrated circuit design method according to 1.
Where R (N): a function representing a ratio of relative variations in current value with the number of divisions N as a variable,
N: the number of divisions related to the gate electrode width, an integer of 1 or more,
σ _{Ids, 1} : current value relative variation (standard deviation value) without division,
σ _{Ids, N} : current value relative variation (standard deviation value) when divided into N pieces,
β: fitting parameter,
L: gate electrode length,
W: The gate electrode width. For at least one of the N-type and P-type field effect transistor pairs, a real value is obtained by the following equation (3) using the gate electrode area and the extracted fitting parameter β, and the real value is 1 In the following cases, the number of divisions is set to 1. When the real value is larger than 1, the smallest integer greater than or equal to the real value and the largest integer less than or equal to the real value are substituted into the equation (2), and the current 5. The method of designing a semiconductor integrated circuit according to claim 4, wherein an integer having a larger value relative variation ratio result is determined as a division number that minimizes the current value relative variation.
Where M is a real number,
N _i , N _{i + 1} : integer,
β: fitting parameter,
S: gate electrode area,
L: gate electrode length,
W: The gate electrode width. A resistive element pair consisting of a first resistive element and a second resistive element having the same size is disposed on the semiconductor substrate, and the first resistive element and the second resistive element are respectively arranged in the length direction of the resistive element. A semiconductor integrated circuit design method for automatically designing, using a computer, a semiconductor integrated circuit configured by connecting n divided (n is an integer of 1 or more) resistance elements in series,
When determining the number of divisions of the resistance element, the relative resistance value variation between the first resistance element and the second resistance element caused by the manufacturing variation is expressed as a function of the number of divisions. A semiconductor integrated circuit design method in which an arithmetic processing unit mathematically derives the number of divisions that minimizes value relative variation and automatically designs a semiconductor integrated circuit using the derived number of divisions. A resistive element pair consisting of a first resistive element and a second resistive element having the same size is disposed on the semiconductor substrate, and the first resistive element and the second resistive element are respectively arranged in the length direction of the resistive element. Resistance value of a semiconductor integrated circuit that automatically evaluates a resistance value relative variation characteristic with respect to a semiconductor integrated circuit configured by serially connecting n divided resistance elements (n is an integer of 1 or more) using a computer A relative variation characteristic evaluation method,
The relationship between the resistance element relative variation between the first resistance element and the second resistance element under a certain power supply voltage condition and the value obtained by dividing 1 by the square root of the area of the resistance element for the resistance element pair A resistance value relative variation characteristic evaluation method for a semiconductor integrated circuit, in which a resistance value relative variation characteristic is modeled by approximating a graph using the following equation (4) by an arithmetic processing unit.
However, σ _R : Relative variation of resistance value (standard deviation value),
α, β: Variables (fitting parameters) to match the measured characteristic values
L: length of the resistance element,
W: The width of the resistance element.   For the resistance element pair, the relationship between the relative resistance value variation between the first resistance element and the second resistance element and the value obtained by dividing 1 by the square root of the area of the resistance element is determined for each power supply voltage condition. 8. The resistance value relative variation characteristic is modeled by approximating the plurality of graphs shown in the equation (4) with the fitting parameter β as a fixed value and changing only the fitting parameter α. For evaluating the relative variation characteristics of resistance of semiconductor integrated circuits. Using the resistance value relative variation characteristic evaluation method for a semiconductor integrated circuit according to claim 7, the fitting parameter β is extracted from the resistor element pair according to the equation (4),
For the resistance element pair, the ratio between the resistance value relative variation when the number of divisions is 1 and the resistance value relative variation when the number of divisions is divided into a plurality of values is used using the number of divisions and the extracted fitting parameter β. The method of designing a semiconductor integrated circuit according to claim 6, wherein the division number is represented by the following formula (5) using a variable, and the division number that maximizes the ratio is determined as the division number that minimizes the relative resistance variation.
Where R (N): a function representing the ratio of relative variation in resistance value with the number of divisions N as a variable,
N: the number of divisions related to the length of the resistance element, an integer of 1 or more,
σ _{R, 1} : Resistance value relative variation (standard deviation value) without division,
σ _{R, N} : Resistance value relative variation (standard deviation value) when divided into N pieces,
β: fitting parameter,
L: length of the resistance element,
W: The width of the resistance element. For the resistance element pair, a real value is obtained by the following equation (6) using the area of the resistance element and the extracted fitting parameter β, and when the real value is 1 or less, the division number is set to 1. When the real value is larger than 1, the smallest integer greater than or equal to the real value and the largest integer less than or equal to the real value are substituted into the equation (5), and the result of the resistance value relative variation ratio becomes larger. 10. The method of designing a semiconductor integrated circuit according to claim 9, wherein the integer is determined as the number of divisions that minimizes the relative variation in resistance value.
Where M is a real number,
Ni, Ni + 1: integer,
β: fitting parameter,
S: area of the resistance element,
L: length of the resistance element,
W: The width of the resistance element.   The control program for making a computer perform the process sequence of the method in any one of Claims 1-10.   A computer-readable recording medium on which the control program according to claim 11 is recorded.   12. A semiconductor integrated circuit for manufacturing a semiconductor integrated circuit based on circuit information reflecting the number of divisions obtained by the processing procedure of the semiconductor integrated circuit design method according to claim 1, Manufacturing method. From the circuit information including the circuit configuration of the semiconductor integrated circuit to be designed and at least one element size of each field effect transistor element and resistor element, all field effect transistor pairs and resistor element pairs that require characteristic relative accuracy are required. A semiconductor integrated circuit design apparatus having an arithmetic processing unit for generating circuit information reflecting the number of divisions obtained by using the semiconductor integrated circuit design method according to at least one of claims 1 and 6 .