JP2005197551A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for performing the forming of a through-hole pattern wherein its lighting condition can be optimized independently of the denseness and rareness of the through-hole pattern, and it is made simple and stable since the correction of any mask used in it is not required. <P>SOLUTION: The method has a process for forming on an interlayer insulation film 3 to form therein a through hole 8 a mask film 4 to become an etching stopper, a process for removing then previously the portion of the mask film wherein the through hole is to be formed, a process for so forming thereafter by usual lithography processes the pattern of a resist 5 which comprises only a dense pattern as to perform the etching of the through holes, a process for removing thereafter the resist film, and a process for removing the mask film, if necessary. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device in which fine through holes are formed.

With the miniaturization of large-scale LSIs, the formation of fine through holes is required. In the lithography process, ArF exposure from KrF exposure, have been F ₂ exposure and shorter wavelength, and it has become necessary to form a small pattern than this wavelength, improvement of the mask, the improvement of the exposure apparatus, a resist material Improvements have been made.
Improvements in the mask in order to obtain a fine pattern include application of a halftone mask and introduction of an auxiliary pattern. As an improvement in the exposure apparatus, high NA and modified illumination are applied. Furthermore, improvements in resist materials include the development of high-resolution resists, hard mask processes for the purpose of resist thinning, and multilayer resist processes.

  Hereinafter, a conventional through hole forming method will be described with reference to FIG. 6 which is a sectional view of the process. In the conventional through hole forming method, an interlayer insulating film 3 is formed on a substrate on which a base pattern 2 such as a gate electrode or a lower layer wiring is formed on a silicon substrate 1. A through hole opening resist pattern 61 is formed thereon.

  In this method, there is a difference in the size of the through hole between a portion having a sparse layout and a portion having a dense layout depending on illumination conditions. That is, when the desired through-hole layout is as shown in FIG. 5, the through-holes present in the sparse parts such as the through-holes 6 a and 6 b and the through-holes 6 d present in the dense part are: A difference will arise in the diameter. In general, when a fine through-hole pattern is formed in a resist film by lithography, a high NA illumination condition is used. In order to increase the exposure tolerance of an isolated pattern, a small σ condition is preferable. Under the condition of σ, there arises a contradiction that the exposure tolerance of the dense pattern decreases. This is shown in FIG. FIG. 7 shows focus direction exposure tolerance (DOF) and dose direction exposure tolerance (EL) when a 120-nm through hole is formed with an ArF exposure machine under illumination conditions of NA = 0.75 and σ = 0.5. In the simulation results, a pattern in which through-holes are in close contact (corresponding to a curve denoted as “1: 1 120 nmCH” in FIG. 7) and an isolated pattern (expressed as “iso 120 nmCH” in FIG. 7). It is clear that there is a big difference in the curve). Further, by changing the illumination conditions (NA = 0.75, σ = 0.8), the exposure tolerance of the dense pattern can be increased as shown in FIG. It is falling.

Optimization of lighting conditions is important for stable resist pattern formation, but in actual patterns, there are dense patterns with close through holes to isolated patterns, making it difficult to set lighting conditions. . In addition, due to the proximity effect, the pattern size depends on density. This density dependency is corrected to the mask by the OPC technique, but it is complicated and time-consuming to apply to the mask pattern such as rule making and data processing.

JP 2002-057084 A

As described above, in the formation of through holes in the conventional semiconductor device manufacturing, there is a density dependence of the pattern diameter, and in order to solve this, it was necessary to correct a complex mask pattern, An object of the present invention is to solve the dependence on the density of the pattern diameter and to form a stable through-hole pattern with simple means.

The present invention includes a step of forming an interlayer insulating film on a substrate;
Forming a mask film on the surface of the interlayer insulating film, which serves as an etching stopper when etching the interlayer insulating film to open a through hole;
Etching and removing a region corresponding to the through hole of the mask film;
Forming a resist film on the mask film surface and on the surface of the interlayer insulating film exposed on the surface after the mask film is removed by etching;
Forming a resist pattern in which dummy patterns are arranged so that through holes are regularly arranged in the resist film;
A method of manufacturing a semiconductor device comprising at least a step of forming a through hole by etching the interlayer insulating film using a resist film on which the dummy pattern is formed.

  In the present invention, in the step of etching and removing the region corresponding to the through hole of the mask film, the region to be etched of the mask film is rectangular, and the length of one side thereof is larger than the diameter of the through hole. Is also big.

  In the present invention, all the dummy patterns formed on the resist film may be arranged at one of two intersecting points orthogonal to the lattice at the same pitch on the resist film plane.

  In the present invention, all the dummy patterns formed on the resist film are arranged at one of the intersections in two directions orthogonal to the grid pattern at the same pitch on the resist film plane, or at an intermediate point between the two intersections. The centers of all through-hole patterns including two adjacent dummy patterns can be separated by a distance of 1 or 1.5 times the pitch.

The mask film is preferably formed of a silicon nitride film, a silicon oxynitride film, or a carbon-based organic film.

According to the method for manufacturing a semiconductor device of the present invention, it is easy to select an optimal illumination condition in a lithography process, and the exposure tolerance of a fine through hole can be widened.

(Embodiment 1)
DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, a first embodiment of the invention will be described with reference to the drawings. FIG. 1 is a cross-sectional view showing a process of a semiconductor device manufacturing method according to the first embodiment of the present invention.

  As shown in FIG. 1A, first, a lower layer pattern 2 such as a gate electrode or a lower layer wiring is formed on a silicon substrate 1.

Next, as shown in FIG. 1B, an interlayer insulating film 3 is formed thereon. As the interlayer insulating film, for example, a known material such as a SiO ₂ film can be employed.

  Next, as shown in FIG. 1C, a mask film 4 is formed on the surface. This mask film 4 is used to function as an etching stopper when the interlayer insulating film 3 is etched to form a through hole, and a material having etching resistance is used when the interlayer insulating film 3 material is etched. That is, as the mask film material, the mask film 4 may be either an inorganic film or an organic film as long as an etching selection ratio can be ensured between the interlayer insulating film 3 and the mask film 4.

Specifically, as the inorganic mask film material, when a SiO ₂ film is used for the interlayer insulating film 3, the mask film 4 is made of silicon such as Si _x N _y or Si _x O _y N _z. A nitride film or a silicon oxynitride film can be used.

  Further, as the carbon-based organic material that can be used as the mask film material, any organic polymer material that is resistant to an etchant that etches the interlayer insulating film material can be used.

Next, as shown in FIG. 1D, the mask film 4 in the region corresponding to the through hole formed in the interlayer insulating film 3 is etched away after forming a resist pattern by a lithography process, and the mask film opening 4b is formed. Form.
In this process, when the actual through-hole layout formed in the interlayer insulating film 3 has through-holes arranged at the required positions in a lattice form as shown in FIG. As a mask for processing the mask film 4, a pattern as shown in FIG. 2 is obtained by connecting a pattern that is twice as large as a desired through-hole diameter R and is opened in a rectangular shape as shown in FIG. 3. Use as a mask. In FIG. 2, the rectangular part and the convex part are mask film openings 4b. Since the resist pattern for etching the mask film can be opened larger than the actually required through hole, the exposure tolerance in the lithography process is large.

  Next, as shown in FIG. 1E, a resist 5 is applied and formed on the surface of the mask film 4 where the mask film opening 4b is formed.

  Next, as shown in FIG. 1 (f), the resist 5 is exposed and developed to form resist openings 7a to 7e (these are called dummy patterns) and 6 in a regular pattern. An example of this pattern is shown in FIG. As seen in FIG. 4, this pattern is a pattern regularly and densely arranged in a lattice pattern.

  When the interlayer insulating film 3 is etched with respect to the structure thus obtained, the interlayer insulating film 3 is formed only in the region where the opening of the resist 5 and the opening 4b of the mask film 4 coincide, that is, the resist opening 6. Etching is removed to form a through hole, while the interlayer insulating film 3 corresponding to the resist openings 7a to 7e, which are dummy patterns whose positions do not coincide with the mask opening 4b, is blocked by the mask film 4 and etched. Therefore, no through hole is formed in that portion (FIG. 1 (g)).

  In the above process, the mask film 4 may be left as a part of the interlayer insulating film as long as the influence on the characteristics such as the dielectric constant of the interlayer insulating film 3 is small. If it is desirable, the through hole is etched and then removed.

  According to the method for manufacturing a semiconductor device of the present embodiment, it becomes easy to select an optimal illumination condition in the lithography process, and the exposure margin of the fine through hole can be widened. This is shown in FIG. It can be seen that by setting the illumination condition to a large σ condition suitable for a dense pattern (here, σ = 0.8), the exposure tolerance of the 1: 1 pattern is widened as compared with FIG. Further, according to the present invention, since the optical proximity effect is eliminated, complicated pattern correction becomes unnecessary.

  Furthermore, according to the method of the present embodiment, it is possible to easily apply a shrink process and a reflow process for forming fine through holes by making the resist pattern a dense pattern and making the resist coverage uniform. It has.

(Embodiment 2)
Hereinafter, a second embodiment of the present invention will be described. This embodiment relates to a method for optimizing the arrangement of dummy patterns for a layout having a plurality of through-hole patterns. In other words, the arrangement of the through hole pattern and the dummy pattern should be regular and uniform, so that it is possible to easily set the illumination condition. The optimum arrangement of the dummy pattern for that purpose is determined. It is about the method.

  Hereinafter, a description will be given with reference to FIG. 9, which is an example of modeling the layout of dummy patterns. In FIG. 9, a plurality of line segments indicated by dotted lines extend in two directions orthogonal to each other in a lattice shape, and the intervals between the plurality of line segments arranged in parallel in the same direction are all the same interval (pitch). . The intersection of the line segments represents the position of the through hole when the through holes are arranged 1: 1. The through hole and the dummy pattern are arranged at the intersection of the perpendicular line segments or between two adjacent intersections.

  In FIG. 9, a circle 6 that is hatched represents a through-hole pattern, and a circle 7 that is not hatched represents a dummy pattern. The line segments extending in the horizontal direction with the reference numerals 1: 1, 1: 2,..., That is, the line segments in the row direction, indicate a specific positional relationship of the through-hole pattern. is there. The positional relationship indicated by reference numeral 1: 1 indicates that a through-hole pattern exists at two adjacent intersections of line segments that intersect in a lattice pattern at the same interval. The positional relationship indicated by reference numeral 1: 2 indicates that the distance between the two through holes (the distance indicated by the reference A in FIG. 9) is two times the distance of the diameter of the through hole. Is meant to be placed. Hereinafter, 1: 3, 1: 4,... Indicate that the through-hole interval is three times or four times when the size of the through hole is 1.

  In this embodiment, the layout of the through hole pattern and the dummy pattern can be made regular by arranging the through holes including the dummy pattern so that the interval is the same as or twice the size of the through hole. In addition, the through-hole density including the dummy pattern can be uniformly arranged as a whole, which makes it easy to select the illumination condition and makes the dimensional difference of the obtained pattern almost uniform. Moreover, even if it becomes necessary to correct the mask dimension, rule creation becomes easier than before.

  In the above description, as shown in FIGS. 2 and 3, it has been described on the assumption that the interval between adjacent through holes (interval between the centers of the through holes) is twice the diameter of the through holes. However, the lithography margin is further expanded. Alternatively, the through hole may be opened largely in consideration of the etching conversion difference.

Thus, when the through hole resist pattern is formed in a dense pattern, the selection of illumination conditions is facilitated, and the exposure margin of the fine through hole can be widened. Further, since there is no difference in density due to the optical proximity effect, there is an effect that mask correction related to pattern density is unnecessary.

FIG. 5 is a process cross-sectional view illustrating the manufacturing process of the semiconductor device according to the first embodiment. FIG. 6 is a mask layout pattern for mask film patterning used in the first embodiment. The figure which shows the relationship of the dimension of the mask layout in FIG. The through-hole layout figure which shows 1st Embodiment. FIG. 3 is a through-hole layout diagram required in the first embodiment. Sectional drawing of the semiconductor device which shows a prior art. The graph which shows the exposure tolerance simulation result on the small (sigma) conditions of a 120 nm through hole. The graph which shows the exposure tolerance simulation result on the large (sigma) conditions of a 120 nm through hole. The through-hole layout figure which shows 2nd Embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Silicon substrate 2 ... Base pattern 3 ... Interlayer insulation film 4 ... Mask film 5 ... Resist film 6 ... Through-hole pattern 7 ... Dummy pattern 8 ... Through-hole pattern 61 opened to base pattern ... Through-hole pattern

Claims (5)

Forming an interlayer insulating film on the substrate;
Forming a mask film on the surface of the interlayer insulating film, which serves as an etching stopper when etching the interlayer insulating film to open a through hole;
Etching and removing a region corresponding to the through hole of the mask film;
Forming a resist film on the mask film surface and on the surface of the interlayer insulating film exposed on the surface after the mask film is removed by etching;
Forming a resist pattern in which dummy patterns are arranged so that through holes are regularly arranged in the resist film;
A method of manufacturing a semiconductor device, comprising: a step of forming a through hole by etching the interlayer insulating film using a resist film on which the dummy pattern is formed.   In the step of etching and removing the region corresponding to the through hole of the mask film, the region to be etched of the mask film is rectangular, and the length of one side thereof is at least larger than the diameter of the through hole. The method of manufacturing a semiconductor device according to claim 1, wherein:   2. The semiconductor according to claim 1, wherein all the dummy patterns formed on the resist film are arranged at one of intersections in two directions orthogonal to the grid pattern at the same pitch on the resist film plane. Device manufacturing method.   All the dummy patterns formed on the resist film are arranged at one of the intersections in two directions orthogonal to the grid pattern at the same pitch on the resist film plane, or at an intermediate point between the two intersections. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the centers of all through-hole patterns including the two dummy patterns are spaced apart by a distance of 1 or 1.5 times the pitch. The method of manufacturing a semiconductor device, wherein the mask film is a silicon nitride film, a silicon oxynitride film, or a carbon-based organic film.

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