JP2005197425A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which can obtain a non-volatile memory having higher integration density. <P>SOLUTION: A first trench is formed on the surface of a semiconductor substrate, and a second trench is formed on the bottom surface of the first trench. A first active region is formed on the surface of the semiconductor substrate, a second active region on the bottom surface of the first trench, and a third active region on the bottom surface of the second trench, respectively. Moreover, an insulating film covering the side surface and the bottom surface of the first and second trenches is formed and a conductive material covering the insulating film is also formed. A part covering the side surface of the second trench of the insulating film is defined as a gate insulating film (for example, ONO film) of a first MIS transistor and a part covering the side surface of the first trench of the insulating film is defined as a gate insulating film of a second MIS transistor. The gate insulating films of the first and second MIS transistors are controlled to function as charge holding portions which can hold charges. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device used for a nonvolatile memory.

  One of semiconductor devices used for a nonvolatile memory is a MONOS (Metal Oxide Nitride Oxide Semiconductor) transistor having a structure shown in Patent Document 1 and Non-Patent Document 1 below. This MONOS transistor is a kind of MIS (Metal Insulator Semiconductor) transistor, and is formed on a source region and a drain region formed in a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, and a gate insulating film. And a gate electrode.

  Among these, the gate insulating film is a laminated film (ONO: Oxide Nitride Oxide film) in which a silicon oxide film, a silicon nitride film, and a silicon oxide film are laminated in this order. When a program (write) operation is performed on the MONOS transistor as a memory cell, an appropriate voltage is applied to each part of the semiconductor substrate, the gate electrode, the source region, and the drain region, so that, for example, electrons are formed on the drain region side in the silicon nitride film. Trap the charges. On the other hand, also in the erase (erase) operation, the trapped charge is extracted by applying an appropriate voltage to each of the above portions. Note that in a nonvolatile memory including MONOS transistors, a source region and a drain region function as bit lines, and a gate electrode functions as a word line.

  When charge is trapped, the threshold voltage of the MONOS transistor changes compared to when it is not trapped. Therefore, by detecting this change in threshold voltage, it can be determined whether 1-bit information is stored in the memory cell.

  In addition to the above-described Patent Document 1 and Non-Patent Document 1, there are the following other prior art document information related to the invention of this application.

US Pat. No. 5,768,192 JP 2001-77219 A JP-A-5-75133 I. Bloom et al., `` NROM a new non-volatile memory technology: from device to products '' Microelectronic Engineering 59 (2001), pp.213-223 B. Goebel et al., `` Vertical N-Channel MOSFETs for Extremely High Density Memories: The Impact of Interface Orientation on Device Performance '' IEEE Transactions On Electron Devices, VOL.48, NO.5, MAY 2001 J. De Blauwe et al., `` Si-Dot Non-Volatile Memory Device '' Extended Abstracts of the 2001 International Conference on Solid State Devices and Materials, Tokyo, 2001, pp. 518-519

  In the MONOS transistor, as shown in FIG. 1. (a) of Non-Patent Document 1, charges can be trapped on both the drain region side and the source region side of the silicon nitride film. Is possible. Accordingly, 2-bit information can be stored in one memory cell, and high integration of the memory element can be realized.

  However, the nonvolatile memory is required to be able to store more information. That is, it is required to realize a non-volatile memory with a higher degree of integration.

  The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a semiconductor device capable of realizing a highly integrated nonvolatile memory.

  The present invention provides a semiconductor substrate having a surface, a first trench formed on the surface of the semiconductor substrate and having a bottom surface and at least one side surface, formed on the bottom surface of the first trench, and having a bottom surface and at least one surface. A second trench having a side surface; an insulating film covering the bottom surface and at least one side surface of the first trench; an insulating film covering the bottom surface and at least one side surface of the second trench; and a conductive material covering the insulating film; A first active region formed adjacent to the first trench on the surface of the semiconductor substrate; a second active region formed adjacent to the second trench on the bottom surface of the first trench; A third active region formed on the bottom surface of the second trench, and the at least one side surface of the second trench of the insulating film. The covering portion, the conductive material, the second active region, and the third active region are each one of a gate insulating film, a gate electrode, a source and drain region of a first MIS (Metal Insulator Semiconductor) transistor, and The other of the source and drain regions, the portion of the insulating film covering the at least one side surface of the first trench, the conductive material, the first active region, and the second active region, The second MIS transistor constitutes one of the gate insulating film, the gate electrode, the source and drain regions, and the other of the source and drain regions, and each of the gate insulating films of the first and second MIS transistors holds charges. This is a semiconductor device that functions as a charge holding portion that can be used.

  According to the present invention, the first and second MIS transistors in which the gate insulating film functions as a charge holding portion are included in at least one side surface of the second and first trenches, respectively. Therefore, the first and second trenches include at least two (four in the case of both side surfaces) MIS transistors functioning as memory elements, and a semiconductor capable of realizing a highly integrated nonvolatile memory. A device is obtained. Further, according to this semiconductor device, the depth of the first trench and the depth of the second trench can be made different. Thereby, for example, the second trench can be formed shallow to shorten the channel length of the first MIS transistor, while the first trench can be formed deep to increase the channel length of the second MIS transistor. The reverse is also possible. Therefore, it is possible to design a transistor with a high degree of freedom.

<Embodiment 1>
The present embodiment is a semiconductor device in which a plurality of MONOS transistors are included in trenches (grooves) formed in two stages.

  FIG. 1 is a perspective view showing an example of a specific structure of a nonvolatile memory 101A having a semiconductor device according to the present embodiment. FIG. 2 is a circuit diagram of the nonvolatile memory 101A.

  In the nonvolatile memory 101A, a plurality of MONOS transistors are formed inside a trench formed in two stages on the surface of the semiconductor substrate 110. In each of the MONOS transistors, the drain regions 113 and 114 function as bit lines, the source regions 111, 112, and 115 function as source lines, and the gate electrode 130 functions as a word line. An element isolation region 140 made of a silicon oxide film or the like is formed above the source regions 111 and 112 between adjacent trenches. A gate insulating film 120 is formed on the surface of the two-stage trench, and the gate insulating film 120 is covered with the gate electrode 130. In FIG. 1, the interlayer insulating film 150 formed on the trench is shown transparent so as not to obstruct the display of the lower structure.

  In the nonvolatile memory 101A, the two-stage formed trench, the drain regions 113 and 114, the source regions 111, 112, and 115, the gate insulating film 120, and the element isolation region 140 extend in the direction in which the source line and the bit line extend (FIG. 1). Then, it is continuous in the depth direction from the paper surface and corresponding to the channel width direction). Further, the gate electrode 130 is continuous in the direction in which the word line extends (in FIG. 1, the direction is parallel to the paper surface and corresponds to the channel length direction).

  FIG. 3 is a cross-sectional view showing a plurality of MONOS transistors Tr1 to Tr4 in the two-stage formation trench of FIG. 1, which is the semiconductor device of the present embodiment. As shown in FIG. 3, in this semiconductor device, a first-stage trench TR1a having a bottom surface and both side surfaces is formed on the surface of a semiconductor substrate 110 such as a silicon substrate. Then, a second-stage trench TR1b having a bottom surface and both side surfaces is formed on the bottom surface of the trench TR1a.

  The opening width of the trench TR1a is set to 0.3 μm, for example, and the depth from the surface of the semiconductor substrate 110 is set to 0.2 μm, for example. Further, the opening width of the trench TR1b is set to 0.1 μm, for example, and the depth from the bottom surface of the trench TR1a is set to 0.2 μm, for example. The channel width defined by the width of the gate electrode 130 is set to 0.2 μm, for example.

  On the surface of semiconductor substrate 110, source regions 111 and 112 as active regions are formed so as to sandwich trench TR1a adjacent to trench TR1a. On the bottom surface of trench TR1a, drain regions 113 and 114 as active regions are formed so as to sandwich trench TR1b adjacent to trench TR1b. A source region 115 as an active region is formed on the bottom surface of the trench TR1b.

  On the bottom surface and both side surfaces of trench TR1a and on the bottom surface and both side surfaces of trench TR1b, gate insulating film 120 is formed so as to cover them. Note that the gate insulating film 120 extends to the surface of the semiconductor substrate 110 and also covers the surface of the semiconductor substrate 110.

  Then, gate electrode 130 is formed so as to fill trenches TR1a and TR1b and cover gate insulating film 120. The gate insulating film 120 is a laminated film in which a silicon oxide film 121, a silicon nitride film 122, and a silicon oxide film 123 are laminated in this order, and the gate electrode 130 is made of a conductive material such as polysilicon. Is done.

  Here, the portion of the gate insulating film 120 that covers one side surface of the trench TR1b, the portion 130f of the gate electrode 130 in the trench TR1b, the drain region 113, and the source region 115 are the gate insulating film of the MONOS transistor Tr1, respectively. , A gate electrode, a drain region, and a source region.

  In addition, the portion of the gate insulating film 120 that covers the other side surface of the trench TR1b, the portion 130f of the gate electrode 130 in the trench TR1b, the drain region 114, and the source region 115 are the gate insulating film of the MONOS transistor Tr2, respectively. A gate electrode, a drain region, and a source region are formed.

  In addition, the portion of the gate insulating film 120 that covers one side surface of the trench TR1a, the portion 130e of the gate electrode 130 in the trench TR1a, the drain region 113, and the source region 111 are respectively a gate insulating film of the MONOS transistor Tr3, A gate electrode, a drain region, and a source region are formed.

  Further, the portion of the gate insulating film 120 that covers the other side surface of the trench TR1a, the portion 130e of the gate electrode 130 in the trench TR1a, the drain region 114, and the source region 112 are respectively formed of the gate insulating film of the MONOS transistor Tr4, A gate electrode, a drain region, and a source region are formed.

  In each of the gate insulating films of the MONOS transistors Tr1 to Tr4, the respective portions of the silicon nitride film 122 on the source region side and the drain region side function as charge holding portions capable of holding charges. . FIG. 3 shows a case where in the MONOS transistors Tr1 to Tr4, charges CH1 to CH8 such as electrons are trapped in the charge holding part on the source region side and the charge holding part on the drain region side of each transistor, respectively. .

  As shown in FIG. 2, each of the MONOS transistors Tr1 to Tr4 functions as a memory cell of the nonvolatile memory 101A. When a program operation, a read operation, and an erase operation are performed on these MONOS transistors Tr1 to Tr4, appropriate voltages are applied to the semiconductor substrate 110, the gate electrode 130, the source regions 111, 112, 115, and the drain regions 113, 114. To do so.

  For example, when the charge CH5 program operation is performed on the MONOS transistor Tr1, the ground potential 0 [V] is applied to the semiconductor substrate 110, the drain regions 113 and 114, and the source regions 111 and 112, and the ground potential is applied to the source region 115 and the gate electrode 130. A channel may be formed in one side surface of the trench TR1b by applying a higher potential (for example, 5 [V] to the source region 115 and 9 [V] to the gate electrode 130). By applying a voltage to each of these parts, charge (for example, electrons) CH5 moves from the drain region 113 toward the source region 115 as channel hot electrons. Then, it is trapped in the charge holding portion in the silicon nitride film 122 in the vicinity of the pinch-off point of the channel.

  Similarly, when the charge CH7 is programmed in the MONOS transistor Tr1, the ground potential 0 [V] is applied to the semiconductor substrate 110, the drain region 114, and the source regions 111, 112, and 115, and the drain region 113 and the gate electrode Information may be written by applying a potential higher than the ground potential to 130 (for example, 5 [V] to the drain region 113 and 9 [V] to the gate electrode 130) to form a channel in one side surface of the trench TR1b. .

  On the other hand, the reading operation of the charge CH5 trapped in the MONOS transistor Tr1 may be performed as follows. That is, a ground potential of 0 [V] is applied to the semiconductor substrate 110, the drain region 114, and the source regions 111, 112, and 115, and a potential higher than the ground potential is applied to the drain region 113 and the gate electrode 130 (for example, 1.6 to the drain region 113). [V] and 3.5 [V]) may be applied to the gate electrode 130 to form a channel in one side surface of the trench TR1b. In this way, a sense amplifier (not shown) can sense the current flowing through the MONOS transistor Tr1.

  The same applies to the read operation of the charge CH7 trapped in the MONOS transistor Tr1. The ground potential 0 [V] is applied to the semiconductor substrate 110, the drain regions 113 and 114, and the source regions 111 and 112, and the source region 115 and the gate electrode 130. A channel higher than the ground potential (for example, 1.6 [V] to the source region 115 and 3.5 [V] to the gate electrode 130) may be applied to form a channel in one side surface of the trench TR1b.

  Further, when performing the erase operation of the charge CH5 trapped in the MONOS transistor Tr1, for example, the potential applied to the source region 115 is 8 [V], the semiconductor substrate 110, the drain regions 113 and 114, the source regions 111 and 112, and the gate The potential applied to the electrode 130 may be 0 [V]. Alternatively, the potential applied to the source region 115 is 5 [V], the potential applied to the semiconductor substrate 110, the drain regions 113 and 114 and the source regions 111 and 112 is 0 [V], and the potential applied to the gate electrode 130 is −6 [V]. And it is sufficient.

  Further, when performing the erase operation of the charge CH7 trapped in the MONOS transistor Tr1, for example, the potential applied to the drain region 113 is 8 [V], the semiconductor substrate 110, the drain region 114, the source regions 111, 112, 115 and the gate. The potential applied to the electrode 130 may be 0 [V]. Alternatively, the potential applied to the drain region 113 is 5 [V], the potential applied to the semiconductor substrate 110, the drain region 114 and the source regions 111, 112, and 115 is 0 [V], and the potential applied to the gate electrode 130 is −6 [V]. And it is sufficient.

  If the potentials of the source regions 111, 112, 115 and the drain regions 113, 114 are set in a floating state and a predetermined potential difference is applied between the gate electrode 130 and the semiconductor substrate 110, the charges CH5 trapped in the MONOS transistor Tr1. CH7 can be extracted to the gate electrode 130 or the semiconductor substrate 110 on the channel side all at once, which is convenient for batch erasure.

  When performing the program operation, the read operation, and the erase operation for the other MONOS transistors Tr2 to Tr4, the same operation as that for the charges CH5 and CH7 may be performed. The charges CH1 to CH8 trapped in the MONOS transistors Tr1 to Tr4 are not limited to electrons, and may be holes, for example.

  4 to 7 are cross-sectional views showing each manufacturing process of the semiconductor device according to the present embodiment.

  First, as shown in FIG. 4, a mask 201 is formed on a semiconductor substrate 110 with a photoresist, a silicon oxide film, a silicon nitride film, or the like, and an opening OP1 is provided in this to form a trench TR1a on the surface of the semiconductor substrate 110. It is formed by anisotropic etching.

  Subsequently, as shown in FIG. 5, a mask 202 is formed of a photoresist, a silicon oxide film, a silicon nitride film or the like on the semiconductor substrate 110 and a part of the bottom surface of the trench TR1a, and an opening OP2 is provided in the mask 202. A trench TR1b is formed on the bottom surface of the trench TR1a by anisotropic etching.

  Next, as shown in FIG. 6, impurity implantation IP <b> 1 is performed to form source regions 111, 112, 115 and drain regions 113, 114.

  Then, as shown in FIG. 7, on the surface of the semiconductor substrate 110, the bottom surface and both side surfaces of the trench TR1a, and the bottom surface and both side surfaces of the trench TR1b, the silicon oxide film 121 and the silicon nitride film 122 are covered so as to cover them. Then, the silicon oxide film 123 is sequentially formed.

  Thereafter, if a conductive material such as polysilicon is buried in the trenches TR1a and TR1b so as to cover the silicon oxide film 123 on the silicon oxide film 123, the gate electrode 130 is formed, and the structure of FIG. 1 is obtained. It is done.

  According to the semiconductor device according to the present embodiment, the MONOS transistors Tr1 and Tr3 in which the gate insulating film functions as a charge holding portion are included in one side surface of the trenches TR1a and TR1b, respectively, and the charge holding portion is provided in the gate insulating film. The formed MONOS transistors Tr2 and Tr4 are included in the other side surfaces of the trenches TR1a and TR1b, respectively. Therefore, at least two MONOS transistors functioning as memory elements are included in the trench (in the case of this embodiment, two MONOS transistors are formed on both sides of the trenches TR1a and TR1b, so a total of four MONOS transistors). Thus, a semiconductor device capable of realizing a highly integrated nonvolatile memory can be obtained.

  Also, according to the semiconductor device of the present embodiment, any part of gate insulating film 120 that covers both side surfaces of trenches TR1a and TR1b is silicon oxide film 121, silicon nitride film 122, and silicon oxide film 123. The silicon nitride film 122 functions as a charge holding portion. Therefore, the MIS transistors formed on both side surfaces of the trenches TR1a and TR1b can be realized by MONOS transistors.

  Further, according to the semiconductor device according to the present embodiment, there are two portions functioning as charge holding portions in the gate insulating films of the MONOS transistors Tr1 to Tr4, respectively, the two being on the source region side and It is arranged on each side of the drain region. Therefore, each of the MONOS transistors Tr1 to Tr4 can store information for 2 bits (a total of 8 bits), and can achieve further high integration.

  Further, by freely designing the depths of the trenches TR1a and TR1b, for example, the channel lengths of the MONOS transistors Tr1 and Tr2 can be designed long, and the channel lengths of the MONOS transistors Tr3 and Tr4 can be designed short. The reverse is also possible. Furthermore, both trenches TR1a and TR1b can be set deeper or shallower. Therefore, it is possible to design a transistor with a high degree of freedom.

  For example, if the channel length of the MONOS transistor Tr1 is designed to be large by setting the depth of the trench TR1b to be large, when trapping the charge CH7 on the drain region side of the silicon nitride film 122, the charge CH5 already written on the source region side. The influence of the repulsion on the charge CH7 by the electric field (that is, the problem of defective writing of the charge CH7) can be avoided (when trapping the charge CH5, the electric field of the charge CH7 already written on the drain region side). The same applies to the effect of repulsion on the charge CH5).

  In addition, the charge distribution in the silicon nitride film 122 of the charges CH5 and CH7 trapped in the charge holding portion tends to spread in the channel length direction as time elapses after the trap. This makes it difficult to distinguish between the charges CH5 and CH7, and it may be difficult to store information of 2 bits (may store only 1 bit of information). However, by designing the channel length of the MONOS transistor Tr1 to be long, it is possible to avoid such difficulty in storing information of 2 bits.

  According to the structure of the semiconductor device according to the present embodiment, the trench TR1b can be deepened to increase the channel length of the MONOS transistor Tr1. Therefore, it is possible to suppress the spread of the trench width on the surface of the semiconductor substrate while increasing the channel length, and to achieve both improvement in integration, avoidance of writing failure, and avoidance of difficulty in storing information for 2 bits. The same applies to the other MONOS transistors Tr2 to Tr4.

  On the other hand, for example, if the depths of the trenches TR1a and TR1b are set to be small, the MONOS transistor can be used even when the element formation region on the substrate surface is shallow because the semiconductor substrate 110 is an SOI (Silicon On Insulator) substrate or the like. Tr1 to Tr4 can be formed.

<Embodiment 2>
The present embodiment is a modification of the semiconductor device according to the first embodiment, and the gate insulating film 120 is not formed on the surface of the semiconductor substrate 110 and the bottom surfaces of the trenches TR1a and TR1b without forming the silicon nitride film 122. This is a change to a laminated film of silicon oxide films 121 and 123.

  FIG. 8 shows a semiconductor device according to the present embodiment. In FIG. 8, the device configuration is the same as that of FIG. 3 except that a gate insulating film 120b is employed instead of the gate insulating film 120.

  The gate insulating film 120b will be described. As shown in FIG. 8, the gate insulating film 120b is a laminated film of silicon oxide films 121 and 123 that does not include the silicon nitride film 122 on the surface of the semiconductor substrate 110 and the bottom surfaces of the trenches TR1a and TR1b. . On the other hand, on both side surfaces of the trenches TR1a and TR1b, the gate insulating film 120b includes a silicon oxide film 121, a silicon nitride film 122a, a laminated film of a silicon oxide film 123, a silicon oxide film 121, a silicon nitride film 122b, and a silicon oxide film, respectively. A laminated film of the film 123, a laminated film of a silicon oxide film 121, a silicon nitride film 122c, a silicon oxide film 123, a laminated film of a silicon oxide film 121, a silicon nitride film 122d, and a silicon oxide film 123 are formed.

  Since other points are the same as those of the semiconductor device according to the first embodiment, description thereof is omitted.

  9 and 10 are cross-sectional views showing each manufacturing process of the semiconductor device according to the present embodiment.

  First, similarly to FIGS. 4 to 6, trenches TR <b> 1 a and TR <b> 1 b, source regions 111, 112, 115 and drain regions 113, 114 are formed in the semiconductor substrate 110.

  Next, as shown in FIG. 9, on the surface of the semiconductor substrate 110, the bottom surface and both side surfaces of the trench TR1a, and the bottom surface and both side surfaces of the trench TR1b, a silicon oxide film 121, a silicon nitride film are formed so as to cover them. 122 are formed sequentially.

  Then, as shown in FIG. 10, anisotropic etching ET1 is performed on the silicon nitride film 122 to remove the silicon nitride film 122 on the surface of the semiconductor substrate 110 and on the bottom surfaces of the trenches TR1a and TR1b, and the trench TR1a. The silicon nitride films 122a to 122d are left only on the side surfaces of TR1b.

  Thereafter, a silicon oxide film 123 is formed so as to cover the silicon oxide film 121 and the silicon nitride films 122a to 122d, and a conductive material such as polysilicon is formed on the silicon oxide film 123 so as to cover the silicon oxide film 123 in the trenches TR1a, If formed by embedding in TR1b, the gate electrode 130 is formed, and the structure of FIG. 8 is obtained.

  In the semiconductor device according to the present embodiment, the gate insulating film 120 b is a stacked film of the silicon oxide films 121 and 123 on the surface of the semiconductor substrate 110. Therefore, the silicon nitride film does not exist in the extended portion of the gate insulating film 120b on the surface of the semiconductor substrate 110, and the extended portion is used as the gate oxide film of another MIS transistor to be formed on the surface of the semiconductor substrate 110. can do.

<Embodiment 3>
The present embodiment is also a modification of the semiconductor device according to the first embodiment, and instead of the gate insulating film 120 in the first embodiment, a gate insulation having a plurality of island-shaped dots formed of silicon. A membrane is adopted.

  A technique for forming silicon dots in a silicon oxide film is described in Non-Patent Document 3, for example. In the present embodiment, a silicon oxide film including such silicon dots is used for the gate insulating film.

  FIG. 11 is a cross-sectional view showing the semiconductor device according to the present embodiment. In FIG. 11, a gate insulating film (for example, silicon oxide film) 220 including silicon dots DT is formed on the surface of the semiconductor substrate 110, on the bottom surface and both side surfaces of the trench TR1a, and on the bottom surface and both side surfaces of the trench TR1b. ing. That is, in this embodiment, MIS transistors Tr1 to Tr4 having the gate insulating film 220 including the silicon dots DT are employed instead of the MONOS transistors.

  The semiconductor device according to the present embodiment has the same structure as the semiconductor device according to the first embodiment, except that the gate insulating film 120 having the ONO structure is replaced with the gate insulating film 220 including the silicon dots DT. .

  In the case of the first embodiment, the charges CH1 to CH8 are held in the trap level in the silicon nitride film 122, but this trap level exists in a defect portion in the silicon nitride film 122. The trap level value is non-uniform depending on the location. Therefore, when the stored charges CH1 to CH8 are stored for a long period of time, the charges CH1 to CH8 may escape if there are fluctuations in energy. In particular, a charge trapped in a shallow level is likely to jump out compared to a charge trapped in a deep level.

  In the case of the silicon dot DT, since it has conductivity, the trap level is deeper than that of the silicon nitride film and is stable regardless of the location. In other words, compared to the case where the charge holding portion is a continuous film in the gate insulating film 120 as in the silicon nitride film 122 in the first embodiment, the movement of the held charge is less likely to occur and is more nonvolatile. This means that an excellent semiconductor device can be realized.

  A technique for forming a silicon nitride film in the form of dots in a silicon oxide film instead of silicon dots is described in, for example, Patent Document 3 (see FIG. 1 of the publication). Even if it is a silicon nitride film, if it is a dot shape, compared with the case where it is a film | membrane continuous in the gate insulating film 120, compared with the case where it is the film | membrane which hold | maintained, the movement of the held electric charge is less likely to occur. it is conceivable that. Therefore, a dot-like silicon nitride film may be employed instead of the silicon dots.

  As described above, if the dots DT, which are island-shaped regions formed in the gate insulating film 220, function as charge holding portions for the charges CH1 to CH8, they are continuously formed in the gate insulating film 120 like the silicon nitride film 122. As compared with the case where the film to be functioned as a charge holding portion, the movement of the held charge is less likely to occur, and a semiconductor device with higher non-volatility can be realized.

  Further, when a silicon oxide film, for example, is used for the gate insulating film 220, the energy level in the dot of the silicon or silicon nitride film is more stable than the energy level of the silicon oxide film. Therefore, if the dots are made of silicon or a silicon nitride film, the movement of the held charges hardly occurs, and a semiconductor device having excellent non-volatility can be realized.

<Modification>
In the first to third embodiments, the case where the trench is formed in two stages is shown, but the present invention is not limited to this.

  For example, as shown in FIG. 12, the semiconductor device of the first embodiment may be modified to further provide a third-stage trench TR1c at the bottom of the trench TR1b. The MONOS transistors Tr5 and Tr6 having the same structure as the MONOS transistors Tr1 to Tr4 may be formed on both side surfaces of the trench TR1c. In this way, higher integration can be achieved.

  In this case, source regions 115b and 115a (both corresponding to source region 115 in FIG. 3) formed adjacent to trench TR1c on the bottom surface of trench TR1b function as source regions for MONOS transistors Tr1 and Tr2, respectively. , And also functions as a source region for the MONOS transistors Tr5 and Tr6. Further, the drain region 116 formed on the bottom surface of the trench TR1c functions as the drain region of the MONOS transistors Tr5 and Tr6.

  A portion of the gate insulating film 120 that covers one side surface of the trench TR1c is a gate insulating film of the MONOS transistor Tr5 and functions as a charge holding portion for the charges CH9 and CH11. The portion of the gate insulating film 120 that covers the other side surface of the trench TR1c is the gate insulating film of the MONOS transistor Tr6, and functions as a charge holding portion for the charges CH10 and CH12.

  Such a structure can be easily obtained by performing mask formation and etching to form trench TR1c after the manufacturing process of FIG.

  In addition, it is good also as a multistage trench structure, such as forming a trench in four steps. In that case, further high integration can be achieved.

It is a perspective view which shows an example of the specific structure of a non-volatile memory. It is a circuit diagram of a non-volatile memory. 1 is a cross-sectional view showing a semiconductor device according to a first embodiment. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the first embodiment. FIG. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the first embodiment. FIG. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the first embodiment. FIG. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the first embodiment. FIG. FIG. 6 is a cross-sectional view showing a semiconductor device according to a second embodiment. 11 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the second embodiment. FIG. 11 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the second embodiment. FIG. FIG. 6 is a cross-sectional view showing a semiconductor device according to a third embodiment. FIG. 6 is a cross-sectional view showing a modification of the semiconductor device according to the first embodiment.

Explanation of symbols

110 Semiconductor substrate, 111, 112, 115 Source region, 113, 114 Drain region, 120, 120b, 220 Gate insulating film, 121, 123 Silicon oxide film, 122, 122a-122d Silicon nitride film, 130 Gate electrode, 140 Device isolation Region, 150 interlayer insulation film, 201, 202 photoresist, DT dot, CH1-CH8 charge.

Claims (6)

A semiconductor substrate having a surface;
A first trench formed on the surface of the semiconductor substrate and having a bottom surface and at least one side surface;
A second trench formed on the bottom surface of the first trench and having a bottom surface and at least one side surface;
An insulating film covering the bottom surface and at least one side surface of the first trench, and the bottom surface and at least one side surface of the second trench;
A conductive material covering the insulating film;
A first active region formed adjacent to the first trench on the surface of the semiconductor substrate;
A second active region formed adjacent to the second trench at the bottom surface of the first trench;
A third active region formed on the bottom surface of the second trench,
A portion of the insulating film covering the at least one side surface of the second trench, the conductive material, the second active region, and the third active region are each of a first MIS (Metal Insulator Semiconductor) transistor. Constituting one of the gate insulating film, the gate electrode, the source and drain regions, and the other of the source and drain regions,
A portion of the insulating film covering the at least one side surface of the first trench, the conductive material, the first active region, and the second active region are respectively a gate insulating film and a gate of the second MIS transistor. Configure one of the electrode, source and drain regions, and the other of the source and drain regions,
Each of the gate insulating films of the first and second MIS transistors is a semiconductor device that functions as a charge holding unit capable of holding charges. The semiconductor device according to claim 1,
A portion of the insulating film that covers the at least one side surface of the first and second trenches is laminated in the order of a first silicon oxide film, a silicon nitride film, and a second silicon oxide film. 1 laminated film,
A semiconductor device in which the silicon nitride film functions as the charge holding portion. The semiconductor device according to claim 2,
The insulating film extends to the surface of the semiconductor substrate and covers the surface of the semiconductor substrate;
On the surface of the semiconductor substrate, the insulating film is a second stacked film in which the first and second silicon oxide films are stacked in this order. The semiconductor device according to claim 1,
A plurality of island regions are formed in the gate insulating film,
A semiconductor device in which the island region functions as the charge holding portion. The semiconductor device according to claim 4,
The island region is a semiconductor device made of silicon or silicon nitride. The semiconductor device according to claim 1,
In the gate insulating films of the first and second MIS transistors, there are two portions functioning as the charge holding portions, respectively, and the two are arranged on the source region side and the drain region side, respectively. Semiconductor device.

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