JP2005196437A - Processor and development support system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize a processor having high compression efficiency for program trace information, and a development support device. <P>SOLUTION: When a direct branch command of a CPU 100 is executed, a flag for condition satisfied/unsatisfied of the branch is shifted-in to be accumulated in a shift register 800 for branch flags, and further when the branch is realized, a branch "taken" counter 900 is incremented to accumulate past branch information. The accumulated branch information determines which the branch flag or the branch "taken" counter value is shorter by use of the current number of branch flags 821 and the branch "taken" counter value 901 to output the trace information. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an information processing apparatus (processor) capable of observing a program execution state externally and a development support apparatus using the processor.

The “trace information output function” is a function for outputting the program execution state of the processor to a debugger operating on an external host computer. When the system detects any abnormal operation, the accumulated trace information is used so that the system developer can confirm the execution history going back from that point and identify the cause.
However, in the development support apparatus, a pin for outputting trace information must be added to the processor, and the number and operating frequency (bandwidth of trace information output) are limited. There is also a limit to the memory capacity for storing trace information. Therefore, it is necessary to compress the trace information in order to maximize the effects using the limited trace output bandwidth and trace memory capacity.

As an example of a conventional technique for compressing trace information, there is a trace information acquisition method called “branch trace” (for example, Non-Patent Document 1). In the branch trace, based on the following rules (1) and (2), information about a branch is output to the outside of the chip every time a branch occurs. Based on the output trace information, an external debugger analyzes it against the source program, so that the execution history can be restored without any branch destination address information.
(1) When a direct branch whose branch destination address is explicitly described in the source program is output, a message (Direct Branch Message) indicating that the branch has been executed is output
(2) When the branch destination address is not explicitly described in the source program and an indirect branch is determined at the time of execution, a branch message (Indirect Branch Message) including the branch destination address is output. Processor based on the above principle The execution history restoration software will be described as a conventional technique, and will be described below with reference to the drawings.

  FIG. 20 shows a configuration of a processor that outputs conventional trace information.

  When the condition at the time of execution of the direct branch instruction is satisfied, the CPU 100 simultaneously sets the direct branch instruction execution signal 102 and the condition satisfaction signal 104 at the time of execution of the branch instruction to “1”. When the condition at the time of execution of the direct branch instruction is not satisfied, the direct branch instruction execution signal 102 is “1”, and the condition satisfaction signal 104 at the time of execution of the branch instruction is “0”. When the condition at the time of execution of the indirect branch instruction is satisfied, the indirect branch instruction execution signal 103 and the condition satisfaction signal 104 at the time of execution of the branch instruction are simultaneously set to “1”. When the condition at the time of execution of the indirect branch instruction is not established, the indirect branch instruction execution signal 103 is “1”, and the condition establishment signal 104 at the time of execution of the branch instruction is “0”. When an interrupt or exception is accepted, the interrupt execution signal 105 becomes “1”, and the values of the direct branch instruction execution signal 102, the indirect branch instruction execution signal 103, and the condition establishment signal 104 at the time of branch instruction execution may be ignored.

  The trace message / packet control state machine (Type 0) 200 receives the direct branch instruction execution signal 102, the indirect branch instruction execution signal 103, the condition establishment signal 104 when the conditional branch instruction is executed, and the interrupt execution signal 105 from the CPU 100. As shown in the state table of the trace message / packet control state machine, a sequence is created from the input signal and the internal state, and the MSEO [1: 0] output (Type0) 201 and the MDO [7: 0] output selection signal (Type0 ) 202 is generated. The MSEO [1: 0] output (Type0) 201 is output to the trace state output terminal (MSEO [1: 0]) 1010 as it is.

The branch take + exception detection circuit 320 receives the direct branch instruction execution signal 102, the indirect branch instruction execution signal 103, the conditional branch instruction condition establishment signal 104, and the interrupt execution signal 105 from the CPU 100 as inputs. The logical product of the branch instruction condition establishment signal 104, the logical product of the indirect branch instruction execution signal 103 and the conditional branch instruction condition establishment signal 104, and the logical sum of the three terms of the interrupt execution signal 105 are taken. A branch take + exception signal 321 signifying that it is executed is output.
The branch destination address update detection circuit 310 receives the indirect branch instruction execution signal 103, the condition establishment signal 104 of the conditional branch instruction, and the interrupt execution signal 105 from the CPU 100, and receives the indirect branch instruction execution signal 103 and the condition establishment signal of the conditional branch instruction. The logical product of 104 and the logical sum of the three terms of the interrupt execution signal 105 are taken, and a branch destination address update signal 311 is output, which means that a branch requiring address output has been executed.

  The sequential instruction execution counter (Type 0) 500 receives the instruction completion signal 101 from the CPU 100 as a count enable, and is synchronously cleared by the branch take + exception signal 321. The count value of the sequential instruction execution counter (Type0) 500 is loaded into the sequential instruction execution counter value holding means (Type0) 510 by the branch take + exception signal 321 to prepare for output of trace information.

  The branch destination address holding means 600 receives and holds the branch destination address 110 from the CPU 100 when the branch destination address update signal 311 is asserted.

  The MDO [7: 0] output multiplexer (Type0) 700 includes a header fixed value “0x03” output circuit 410 output, a header fixed value “0x04” output circuit 420 output, and sequential instruction execution counter value holding means ( The output of Type 0) 510 and the signal obtained by dividing the output of branch destination address holding means 600 into 8-bit units are input as signals to be selected for 7 groups, and MDO [7: 0] output selection signal (Type 0) 202 To select one of the seven groups and output it as an MDO [7: 0] output signal (Type 0) 701. The MD0 [7: 0] output signal (Type0) 701 is output to the trace data output terminal (MDO [7: 0]) as it is.

  FIG. 22 shows assignment of TCODE which is an ID of a trace message output by the system of FIG. FIG. 23 shows a message format of Program Trace and Direct Branch Message, and FIG. 24 shows a message format of Program Trace and Direct Branch Message. The MDO [7: 0] output and the MSEO [1: 0] output are changed in synchronization with the reference clock of the trace output not described here. MSEO [1: 0] is particularly important because it means the beginning and end of messages and packets.

As shown in the trace message / packet control state machine state table in FIG. 21, when the condition for direct branching is satisfied (when the direct branching instruction execution signal 102 and the branching instruction execution condition signal 104 are simultaneously “1”), the IDLE state → A transition is made from the DIR_HEAD state to the DIR_ICNT state to the IDLE state, and the sequence output shown in the message format of Program Trace and Direct Branch Message in FIG. 23 is obtained by the MDO output selection signal output and the MSEO output signal. When an indirect branch instruction condition is satisfied (the indirect branch instruction execution signal 103 and the condition establishment signal 104 at the time of branch instruction execution are simultaneously “1”) or when an interrupt occurs (the interrupt execution signal 105 is “1”), the IDLE state → Transition is made from IND_HEAD state → IND_ICNT state → IND_UADR0 state → IND_UADR1 state → IND_UADR2 state → IND_UADR3 state → IDLE state, and a trace output as shown in the message format of Program Trace and Indirect Branch Message in FIG. 24 is obtained. Originally, there is a possibility that the next branch instruction may be executed between each sequence, and it is necessary to be designed to accept them, but this is omitted for the sake of simplicity. . The length of U-ADDR is a protocol that does not need to output the upper bits if the upper address does not change, but this is also controlled by outputting a fixed length of 32 bits for simplicity. Please note the points explained.
FIG. 19 shows an overall configuration diagram of a development support apparatus using this processor.

  The trace information storage device 2 receives the trace status signal 1011 and the trace data signal 1021 from the processor 1, and the trace memory control 1210 controls the trace memory control signal 1211 and the trace memory write data 1212, whereby memory access to the trace memory 1230 is performed. Are stored in the trace memory 1230 as trace information. The host computer 3 outputs a trace memory read request 1301 to the trace information storage device 2, accesses the trace memory via the trace memory control 1210, and acquires the trace memory output 1231.

  Next, how the trace data is acquired from the processor 1 configured as described above and the execution history is restored will be described by taking the program of FIG. 26 as an example. When executed from the address 0x50000000 in FIG. 26, in the direct branch of (3), the number of sequential instruction executions is 2 so far, so “PTDB I-CNT = 2” is output. In the direct branch of (6) and (9), the number of sequential instruction executions before that is 2, but they are collectively output as “PTDB I-CNT = 2, I-CNT = 2”. In the following (12), because it was not-taken, the sequential instruction execution count was carried forward until the appearance of the indirect branch in (17), I-CNT = 7, and the indirect branch was taken. PTIB I-CNT = 7, U-ADDR = 0x50000300 ”is output. Similarly, since the “ret” instruction in (20) is regarded as an take of an indirect branch, “PTIB I-CNT = 2, U-ADDR = 0x50000034” is output. The trace information acquired in this way is as shown in FIG.

  Next, a description will be given of a procedure in which the host computer 3 restores the execution history according to the algorithm shown in FIG. 25 when the source program of FIG. 26 and the trace information of FIG. 27 are given.

  In step 2001, IP is set to address 0x50000000, TP is set to address 0, and ETP is set to address 4.

  Since TP ≠ ETP, 2002 is skipped, and the trace message of TP = 0 is “PTDB I-CNT = 2”. Therefore, the process proceeds to step 2003 and step 2004, and the instruction “command 1” at IP = 0x50000000, IP = 0x50000004 The instruction “address 2” at the address is displayed, the instruction “bra loop_A” at the address IP = 0x50000008 is displayed at step 2005, and the direct branch destination address 0x50000014 (loop_A) is set to IP. In step 2006, since the I-CNT packet of this message is completed, the process proceeds to step 2050 and TP is incremented.

  At the next TP = 1, “TPDB I-CNT = 2, I-CNT = 2” is processed, but since TP ≠ ETP, 2002 is skipped, and the process proceeds to Step 2003 and Step 2004, where IP = 0x50000014, IP = The instruction of 0x50000018 is displayed, “bne loop_A” is displayed in step 2005, and the IP is set to 0x50000014 (loop_A) again. Since there are two I-CNT packets, the same loop is repeated once again, and TP is incremented to 2 in step 2050.

  At the next TP = 2, “PTIB I-CNT = 7, U-ADDR = 0x50000300” is processed, but this is also TP ≠ ETP, so 2002 is skipped, proceeding to N in step 2003, proceeding to Y in step 2013 . In Step 2014, from “loop_A: Instruction 3” with IP = 0x50000014, “Instruction 4” with IP = 0x50000018, “bne loop_A” with IP = 0x5000001c, “Instruction 5” with IP = 0x50000020, “Instruction 6 with IP = 0x50000024” “Instruction 7” with IP = 0x50000028 and “mov Sub_C, a0” with IP = 0x5000002c are displayed in order. Subsequently, in step 2015, the indirect branch instruction “call (a0)” of IP = 0x50000030 is displayed, and in step 2016, IP is set to the address 0x50000300 indicated by U-ADDR. In step 2050, TP is incremented to 3.

At the next TP = 3, “PTIB I-CNT = 2, U-ADDR = 0x5000034” is processed, but this is also TP ≠ ETP, so 2002 is skipped, proceeding to N in step 2003, proceeding to Y in step 2013 . In step 2014, “Sub_C: Command 9” with IP = 0x50000300 and “Command 10” with IP = 0x50000304 are sequentially displayed. Subsequently, in step 2015, the indirect branch instruction “ret” with IP = 0x50000308 is displayed, and in step 2016, IP is set to address 0x50000034 indicated in U-ADDR. In step 2050, TP is incremented to 4.
At the next TP = 4, it is determined in step 2002 that TP == ETP, so the execution history restoration ends. The execution history thus obtained is shown in FIG.
IEEE-ISTO 5001 (TM) -1999, “The Nexus 5001 Forum (TM) Standard for a Global Embedded Processor Debug Interface”

  However, the conventional technique has a problem that the compression rate of the trace information is low. In other words, in the prior art, the condition failure of the conditional branch instruction is counted in sequential instruction execution, and the sequential instruction execution count must be output every time the condition of branch (direct branch or indirect branch) is satisfied (branch execution). Don't be. In addition, it takes at least one trace output clock to output the number of sequential instruction executions, and the ratio between the CPU operating frequency and the trace clock (the trace output clock is usually 1/2, 1/4 of the CPU clock, etc.) If the operating frequency that can be transmitted to the outside of the chip is selected with the divided frequency), the output rate of the trace information is lower than the generation rate of the trace information, such as when branch instructions are continuous, and the appropriate capacity Even if the buffer is prepared, the trace output becomes impossible immediately. In other words, the compression rate of the trace information output is lower than the actual operation of the CPU.

  In view of such problems, an object of the present invention is to provide means for highly compressing trace information to such an extent that high-speed CPU operations can be reliably captured externally.

  To solve the above problem, the invention according to claims 1 and 4 of the present application does not include the failure of the branch instruction in the sequential instruction execution condition, and sets the success bit when the CPU branch instruction condition is satisfied, and the branch is not satisfied. The problem is solved by shifting the unsuccessful bits into the shift register and outputting a branch status message that summarizes all the bits stored in the shift register and information on the number of valid bits.

  Further, in order to increase the trace information compression rate under a specific condition, the branch taken count message including the value of the counter for counting the number of establishments when the CPU branches are successively established according to the inventions of claims 2 and 5 of the present application. To solve the problem.

  Further, in order to always output trace information with the optimum compression rate, according to the inventions of claims 3 and 6 of the present application, it is determined which one of the branch status message and the branch take count message is shorter, and is selected and output. , To solve the problem.

  According to the processor and the development support apparatus according to the first and fourth aspects of the present invention, since one packet is conventionally required every time a branch occurs, only one bit in the packet can be used. The compression ratio of information is estimated to be about 1/8.

  Furthermore, according to the processor and the development support apparatus according to the third and sixth aspects of the present invention, when the same branch continues, the information compression rate can be further increased to 1/32.

  Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of the processor in the first embodiment of the present invention.
When the condition at the time of execution of the direct branch instruction is satisfied, the CPU 100 simultaneously sets the direct branch instruction execution signal 102 and the condition satisfaction signal 104 at the time of execution of the branch instruction to “1”. When the condition at the time of execution of the direct branch instruction is not satisfied, the direct branch instruction execution signal 102 is “1”, and the condition satisfaction signal 104 at the time of execution of the branch instruction is “0”. When the condition at the time of execution of the indirect branch instruction is satisfied, the indirect branch instruction execution signal 103 and the condition satisfaction signal 104 at the time of execution of the branch instruction are simultaneously set to “1”. When the condition at the time of execution of the indirect branch instruction is not established, the indirect branch instruction execution signal 103 is “1”, and the condition establishment signal 104 at the time of execution of the branch instruction is “0”. When an interrupt or exception is accepted, the interrupt execution signal 105 becomes “1”, and the values of the direct branch instruction execution signal 102, the indirect branch instruction execution signal 103, and the condition establishment signal 104 at the time of branch instruction execution may be ignored.

  The trace message / packet control state machine (Type 2) 220 includes a direct branch instruction execution signal 102, an indirect branch instruction execution signal 103, a condition establishment signal 104 when executing a conditional branch instruction, an interrupt execution signal 105, and a branch flag counter 820. Branch flag counter value 821 is received, a sequence is generated from the input signal and the internal state, as shown in the state table of the trace message / packet control state machine in FIG. 2, and MSEO [1: 0] output (Type 2) 221 , MDO [7: 0] output selection signal (Type2) 222 is generated. The MSEO [1: 0] output (Type2) 221 is output to the trace state output terminal (MSEO [1: 0]) 1010 as it is.

  The branch take detection circuit 350 receives the direct branch instruction execution signal 102, the indirect branch instruction execution signal 103, and the condition establishment signal 104 of the conditional branch instruction from the CPU 100, and receives the direct branch instruction execution signal 102 and the condition establishment signal of the conditional branch instruction. A branch take signal that is a logical sum of two terms of the logical product of 104, the logical product of the indirect branch instruction execution signal 103 and the conditional establishment instruction 104 of the conditional branch instruction, and means that the branch is executed 351 is output.

  The branch destination address update detection circuit 310 receives the indirect branch instruction execution signal 103, the condition establishment signal 104 of the conditional branch instruction, and the interrupt execution signal 105 from the CPU 100, and receives the indirect branch instruction execution signal 103 and the condition establishment signal of the conditional branch instruction. The logical product of 104 and the logical sum of the three terms of the interrupt execution signal 105 are taken, and a branch destination address update signal 311 is output, which means that a branch requiring address output has been executed.

  The branch detection circuit 340 receives the direct branch instruction execution signal 102, the indirect branch instruction execution signal 103, and the interrupt execution signal 105 from the CPU 100, and outputs a logical sum of them as a branch execution signal 341.

  The sequential instruction execution counter (Type 2, 3) 530 inputs the instruction completion signal 101 from the CPU 100 to the count enable, and is synchronously cleared by the branch execution signal 341. The count value of the sequential instruction execution counter (Type 2, 3) 530 is loaded into the sequential instruction execution counter value holding means (Type 2, 3) 540 by the branch execution signal 341, and is prepared for output of trace information.

  The branch destination address holding means 600 receives and holds the branch destination address 110 from the CPU 100 when the branch destination address update signal 311 is asserted.

  The branch flag counter 820 is a counter that receives the branch execution signal 341 to enable counting and is synchronously cleared by the branch destination address update signal 311. The branch flag counter value 821 is supplied to the state machine 220, and its lower 3 bits are the timing at which the branch destination address update signal 311 is asserted or the state machine 220 transitions to the BST_HEAD state although not shown. At the timing, it is loaded into the branch flag counter value holding means 830.

  The branch flag shift register 800 shifts in the branch take signal 351 by using the branch execution signal 341 as a shift enable signal. When the branch destination address update signal 311 is asserted, the branch flag shift register 800 is synchronously cleared, but the previous flag value is loaded into the branch flag holding means 810.

  The MDO [7: 0] output multiplexer (Type 2) 720 includes an output of the header fixed value “0x38” output circuit 430, an output of the header fixed value “0x3a” output circuit 450, and sequential instruction execution counter value holding means ( Type 2, 3) 540 output, a signal obtained by dividing the output of the branch destination address holding means 600 in units of 8 bits, the output of the branch flag counter value holding means 830 and the output of the branch flag holding means 810 are merged to generate 8 bits. The signal is re-aligned as a unit and input as a signal to be selected for 13 groups, and one of the 13 groups is selected by the MDO [7: 0] output selection signal (Type 2) 222, and MDO [7 : 0] Output as an output signal (Type2) 721. The MD0 [7: 0] output signal (Type2) 721 is output as it is to the trace data output terminal (MDO [7: 0]).

  FIG. 3 shows assignment of TCODE which is an ID of a trace message output by the system of FIG. 4 shows a message format of Program Trace and Branch Status Message, FIG. 5 shows a message format of Program Trace and Branch Destination Address Message, and FIG. 6 shows a message format of Program Trace and Branch Exception Message. . The MDO [7: 0] output and the MSEO [1: 0] output are changed in synchronization with the reference clock of the trace output not described here.

  As shown in the trace message / packet control state machine (Type2) state table in FIG. 2, when a direct branch condition is satisfied (the direct branch instruction execution signal 102 and the branch instruction execution condition satisfaction signal 104 are simultaneously "1") When the branch flag count value is full (BFcount == 31), transition from IDLE state → BST_HEAD state → BST_NV state → BST_BRF0 → BST_BRF1 → BST_BRF2 → BST_BRF3 → IDLE state, MDO output selection signal output and MSEO output signal Thus, the sequence output shown in the message format of Program Trace, Branch Status Message in FIG. 4 is obtained.

  When the condition of an indirect branch instruction is satisfied (the indirect branch instruction execution signal 103 and the condition satisfaction signal 104 at the time of branch instruction execution are simultaneously “1”) and the branch flag count value is zero (BFcount == 0), the IDLE state → Transition is made from BDA_HEAD state → IND_UADR0 state → IND_UADR1 state → IND_UADR2 state → IND_UADR3 state → IDLE state, and a trace output as shown in the message format of Program Trace, Branch Destination Address Message in FIG. 5 is obtained.

  When the condition of an indirect branch instruction is satisfied (the indirect branch instruction execution signal 103 and the condition satisfaction signal 104 at the time of branch instruction execution are simultaneously “1”) and the branch flag count value is not zero (BFcount! = 0), Control to output PTBDA message after outputting PTBST message.

  When an interrupt occurs (interrupt execution signal 105 is “1”) and the branch flag count value is zero (BFcount == 0), IDLE state → EXC_HEAD state → EXC_ICNT state → IND_UADR0 state → IND_UADR1 state → IND_UADR2 state → IND_UADR3 state → Transition to IDLE state and trace output as shown in the message format of Program Trace, Exception Message in FIG. 6 is obtained.

  When an interrupt occurs (interrupt execution signal 105 is “1”) and the branch flag count value is not zero (BFcount! = 0), the PTBST message is output first and then the PTEXC message is output. The

  Originally, there is a possibility that the next branch instruction may be executed between each sequence, and it is necessary to be designed to accept them, but this is omitted for the sake of simplicity. . The length of U-ADDR is a protocol that does not need to output the upper bits if the upper address does not change, but this is also controlled by outputting a fixed length of 32 bits for simplicity. Please note the points explained.

  FIG. 19 shows an overall configuration diagram of a development support apparatus using this processor.

The trace information storage device 2 receives the trace status signal 1011 and the trace data signal 1021 from the processor 1, and the trace memory control 1210 controls the trace memory control signal 1211 and the trace memory write data 1212, whereby memory access to the trace memory 1230 is performed. Are stored in the trace memory 1230 as trace information. The host computer 3 outputs a trace memory read request 1301 to the trace information storage device 2, accesses the trace memory via the trace memory control 1210, and acquires the trace memory output 1231. (This is exactly the same as the conventional example.)
Next, how the trace data is acquired from the processor 1 configured as described above and the execution history is restored will be described by taking the program of FIG. 8 as an example. When executed from address 0x50000000 in FIG. 8, the taken / not-taken branch until the occurrence of the indirect branch of (17) is accumulated in the shift register, and “PTBST NV = 4, BR-FLAG = 0b0111” is output, After that, since the indirect branch of (17) was taken, “PTBDA U-ADDR = 0x50000300” is output. Similarly, since the “ret” instruction in (20) is regarded as an indirect branch take, “PTBDA U-ADDR = 0x50000034” is output. The trace information acquired in this way is as shown in FIG.

  Next, a description will be given of the procedure in which the host computer 3 restores the execution history according to the algorithm shown in FIG. 7 when the source program of FIG. 8 and the trace information of FIG. 9 are given.

First, in step 2001, IP is set to address 0x50000000, TP is set to address 0, and ETP is set to address 3. Next, since TP ≠ ETP, 2002 is skipped, and the trace message of TP = 0 is “PTBST BR-FLAG = 0b0111”. Therefore, the process proceeds to step 2100 and step 2101, and the instruction “instruction 1” at IP = 0x50000000 is entered. The instruction “instruction 2” at IP = 0x50000004 is displayed. In step 2102, the instruction “bra loop_A” at IP = 0x50000008 is displayed, and the direct branch destination address 0x50000014 (loop_A) is set to IP. In step 2103, since the branch flag valid flag still remains, the process returns to step 2101 again. This time, the instruction “loop_A: instruction 3” at IP = 0x50000014 is displayed, “instruction 4” at IP = 0x50000018 is displayed. In step 2102, “bne loop_A” at IP = 0x5000001c is displayed, and the branch flag is 1. Therefore, the branch destination address 0x50000014 (loop_A) is set directly in the IP. Similarly, IP = 0x50000014 to IP = 0x5000001c are repeated twice. In “bne loop_A” at the last IP = 0x5000001c, since the corresponding branch flag is “0”, the address 0x50000020 of the next instruction is set to IP, and the number of valid flags is ended in step 2103. Go to and increment TP.
At the next TP = 1, “PTBDA U-ADDR = 0x50000300” is processed, but since this is also TP ≠ ETP, 2002 is skipped, the process proceeds to N in steps 2100 and 2200, and proceeds to Y in step 2300. In step 2301, "instruction 5" with IP = 0x50000020, "instruction 6" with IP = 0x50000024, "instruction 7" with IP = 0x50000028, and "mov Sub_C, a0" with IP = 0x5000002c are sequentially displayed. Subsequently, in step 2302, the indirect branch instruction “call (a0)” of IP = 0x50000030 is displayed, and in step 2303, IP is set to the address 0x50000300 indicated by U-ADDR. In step 2050, TP is incremented to 2.

At the next TP = 2, “PTBDA U-ADDR = 0x5000034” is processed. Since this is also TP ≠ ETP, 2002 is skipped, and the process proceeds to N in steps 2100 and 2200, and proceeds to Y in step 2300. In step 2301, “Sub_C: Command 9” with IP = 0x50000300 and “Command 10” with IP = 0x50000304 are sequentially displayed. Subsequently, in step 2302, an indirect branch instruction “ret” with IP = 0x50000308 is displayed. In step 2303, IP is set to an address 0x50000034 indicated by U-ADDR. In step 2050, TP is incremented to 3.
At the next TP = 3, it is determined in step 2002 that TP == ETP, so the execution history restoration ends. The execution history thus obtained is shown in FIG.

  As shown in this example, in the present invention, the result of the direct branch instruction that conventionally required one packet can be compressed to 1 bit of BR-FLAG of the PTBST message.

  FIG. 11 is a block diagram showing the configuration of the processor in the second embodiment of the present invention.

  When the condition at the time of execution of the direct branch instruction is satisfied, the CPU 100 simultaneously sets the direct branch instruction execution signal 102 and the condition satisfaction signal 104 at the time of execution of the branch instruction to “1”. When the condition at the time of execution of the direct branch instruction is not satisfied, the direct branch instruction execution signal 102 is “1”, and the condition satisfaction signal 104 at the time of execution of the branch instruction is “0”. When the condition at the time of execution of the indirect branch instruction is satisfied, the indirect branch instruction execution signal 103 and the condition satisfaction signal 104 at the time of execution of the branch instruction are simultaneously set to “1”. When the condition at the time of execution of the indirect branch instruction is not established, the indirect branch instruction execution signal 103 is “1”, and the condition establishment signal 104 at the time of execution of the branch instruction is “0”. When an interrupt or exception is accepted, the interrupt execution signal 105 becomes “1”, and the values of the direct branch instruction execution signal 102, the indirect branch instruction execution signal 103, and the condition establishment signal 104 at the time of branch instruction execution may be ignored.

  The trace message / packet control state machine (Type 3) 230 includes a direct branch instruction execution signal 102, an indirect branch instruction execution signal 103, a condition establishment signal 104 when executing a conditional branch instruction, an interrupt execution signal 105, and a branch flag counter 820. Branch flag counter value 821 and branch take counter value 901 from branch take counter 900 are received and sequenced from the input signal and internal state as shown in the trace message / packet control state machine (Type 3) state table of FIG. , MSEO [1: 0] output (Type3) 231 and MDO [7: 0] output selection signal (Type3) 232 are generated. The MSEO [1: 0] output (Type3) 231 is output to the trace state output terminal (MSEO [1: 0]) 1010 as it is.

  The branch take detection circuit 350 receives the direct branch instruction execution signal 102, the indirect branch instruction execution signal 103, and the condition establishment signal 104 of the conditional branch instruction from the CPU 100, and receives the direct branch instruction execution signal 102 and the condition establishment signal of the conditional branch instruction. A branch take signal that is a logical sum of two terms of the logical product of 104, the logical product of the indirect branch instruction execution signal 103 and the conditional establishment instruction 104 of the conditional branch instruction, and means that the branch is executed 351 is output.

  The branch not-taken detection circuit 330 receives the direct branch instruction execution signal 102, the indirect branch instruction execution signal 103, and the condition establishment signal 104 of the conditional branch instruction from the CPU 100 as inputs, and negates the direct branch instruction execution signal 102 and the conditional branch instruction. The logical product of the condition establishment signal 104 of the above, the negation of the indirect branch instruction execution signal 103, and the logical product of the condition establishment signal 104 of the conditional branch instruction, and the logical sum of the two terms. A meaning branch not-taken signal 331 is output.

  The branch destination address update detection circuit 310 receives the indirect branch instruction execution signal 103, the condition establishment signal 104 of the conditional branch instruction, and the interrupt execution signal 105 from the CPU 100, and receives the indirect branch instruction execution signal 103 and the condition establishment signal of the conditional branch instruction. The logical product of 104 and the logical sum of the three terms of the interrupt execution signal 105 are taken, and a branch destination address update signal 311 is output, which means that a branch requiring address output has been executed.

  The branch detection circuit 340 receives the direct branch instruction execution signal 102, the indirect branch instruction execution signal 103, and the interrupt execution signal 105 from the CPU 100, and outputs a logical sum of them as a branch execution signal 341.

  The sequential instruction execution counter (Type 2, 3) 530 inputs the instruction completion signal 101 from the CPU 100 to the count enable, and is synchronously cleared by the branch execution signal 341. The count value of the sequential instruction execution counter (Type 2, 3) 530 is loaded into the sequential instruction execution counter value holding means (Type 2, 3) 540 by the branch execution signal 341, and is prepared for output of trace information.

  The branch destination address holding means 600 receives and holds the branch destination address 110 from the CPU 100 when the branch destination address update signal 311 is asserted.

  The branch flag counter 820 is a counter that receives the branch execution signal 341 to enable counting and is synchronously cleared by the branch destination address update signal 311. The branch flag counter value 821 is supplied to the state machine 230, and the lower 3 bits thereof are the timing at which the branch destination address update signal 311 is asserted or the state machine 230 transitions to the BST_HEAD state although not shown. At the timing, it is loaded into the branch flag counter value holding means 830.

  The branch flag shift register 800 shifts in the branch take signal 351 by using the branch execution signal 341 as a shift enable signal. When the branch destination address update signal 311 is asserted, the branch flag shift register 800 is synchronously cleared, but the previous flag value is loaded into the branch flag holding means 810.

  The branch take counter 900 is a counter that receives the branch take signal 351 as a count enable and is synchronously cleared by the branch not-taken signal 331. The branch take counter value 901 is supplied to the state machine 230, and at the timing when the branch not-taken signal 331 is asserted (this may be added artificially later), the branch take is added. The counter value holding means 910 is loaded.

  The MDO [7: 0] output multiplexer (Type 3) 730 outputs the header fixed value “0x38” output circuit 430, the header fixed value “0x39” output circuit 440, and the header fixed value “0x3a” output. The output of the circuit 450, the output of the sequential instruction execution counter value holding means (Type 2, 3) 540, the signal obtained by dividing the output of the branch destination address holding means 600 into 8-bit units, and the output of the branch flag counter value holding means 830 And the output of the branch flag holding means 810 are merged and rearranged in units of 8 bits and the output of the branch taken counter value holding means 910 are input as 15 groups of selected signals, and MDO [7: 0] One of the 15 groups is selected by the output selection signal (Type 3) 232 and is output as an MDO [7: 0] output signal (Type 3) 731. The MD0 [7: 0] output signal (Type3) 731 is output as it is to the trace data output terminal (MDO [7: 0]).

  FIG. 13 shows assignment of TCODE which is an ID of a trace message output by the system of FIG. 4 shows a message format of Program Trace and Branch Status Message, FIG. 5 shows a message format of Program Trace and Branch Destination Address Message, FIG. 6 shows a message format of Program Trace and Branch Exception Message, and FIG. Shows the message format of Program Trace and Branch Taken Count Message. The MDO [7: 0] output and the MSEO [1: 0] output are changed in synchronization with the reference clock of the trace output not described here.

  As shown in the trace message / packet control state machine (Type 3) state table in FIG. 12, when a direct branch condition is satisfied (the direct branch instruction execution signal 102 and the condition satisfaction signal 104 at the time of branch instruction execution are simultaneously “1”). When the branch flag count value is full (BFcount == 31), transition from IDLE state → BST_HEAD state → BST_NV state → BST_BRF0 → BST_BRF1 → BST_BRF2 → BST_BRF3 → IDLE state, MDO output selection signal output and MSEO output signal Thus, the sequence output shown in the message format of Program Trace, Branch Status Message in FIG. 4 is obtained.

  When the condition of an indirect branch instruction is satisfied (the indirect branch instruction execution signal 103 and the condition satisfaction signal 104 at the time of branch instruction execution are simultaneously “1”) and the branch flag count value is zero (BFcount == 0), the IDLE state → Transition is made from BDA_HEAD state → IND_UADR0 state → IND_UADR1 state → IND_UADR2 state → IND_UADR3 state → IDLE state, and a trace output as shown in the message format of Program Trace, Branch Destination Address Message in FIG. 5 is obtained.

  When the condition of an indirect branch instruction is satisfied (the indirect branch instruction execution signal 103 and the condition satisfaction signal 104 at the time of branch instruction execution are simultaneously “1”) and the branch flag count value is not zero (BFcount! = 0), Control to output PTBDA message after outputting PTBST message.

  When an interrupt occurs (interrupt execution signal 105 is “1”) and the branch flag count value is zero (BFcount == 0), IDLE state → EXC_HEAD state → EXC_ICNT state → IND_UADR0 state → IND_UADR1 state → IND_UADR2 state → IND_UADR3 state → Transition to IDLE state and trace output as shown in the message format of Program Trace, Exception Message in FIG. 6 is obtained.

  When an interrupt occurs (interrupt execution signal 105 is “1”) and the branch flag count value is not zero (BFcount! = 0), the PTBST message is output first and then the PTEXC message is output. The

  Originally, there is a possibility that the next branch instruction may be executed between each sequence, and it is necessary to be designed to accept them, but this is omitted for the sake of simplicity. . The length of U-ADDR is a protocol that does not need to output the upper bits if the upper address does not change, but this is also controlled by outputting a fixed length of 32 bits for simplicity. Please note the points explained.

  FIG. 19 shows an overall configuration diagram of a development support apparatus using this processor.

The trace information storage device 2 receives the trace status signal 1011 and the trace data signal 1021 from the processor 1, and the trace memory control 1210 controls the trace memory control signal 1211 and the trace memory write data 1212, whereby memory access to the trace memory 1230 is performed. Are stored in the trace memory 1230 as trace information. The host computer 3 outputs a trace memory read request 1301 to the trace information storage device 2, accesses the trace memory via the trace memory control 1210, and acquires the trace memory output 1231. (This is exactly the same as the conventional example.)
Next, how the trace data is acquired from the processor 1 configured as described above and the execution history is restored will be described by taking the program of FIG. 16 as an example. When executed from address 0x50000000 in FIG. 16, the branch take / not-taken flag is accumulated in the shift register and the branch take count value is incremented until the conditional branch instruction (69) becomes not-taken. However, since the code efficiency is higher when the branch taken count message is output, “PTBTCBR-TAKEN = 22” is output. After that, since the indirect branch of (78) was taken, “BTBST BR-FLAG = 0b0” including the no-taken flag remaining in the shift register of the branch flag is output, followed by “PTBDA U-ADDR = 0x50000300 "Is output. Similarly, since the “ret” instruction in (77) is regarded as an indirect branch take, “PTBDA U-ADDR = 0x50000034” is output. The trace information acquired in this way is as shown in FIG.

  Next, the procedure in which the host computer 3 restores the execution history according to the algorithm shown in FIG. 15 when the source program of FIG. 16 and the trace information of FIG. 17 are given will be described.

  First, in step 2001, IP is set to address 0x50000000, TP is set to address 0, and ETP is set to address 4. Next, since TP ≠ ETP, 2002 is skipped, and the trace message of TP = 0 is “PTBTC BR-TAKEN = 22”, so the process proceeds to step 2400 and step 2401 and internally converted to the set of branch flags 0b11111111111111111111111 To do. Then, go to Step 2101, display the instruction “Instruction 1” at IP = 0x50000000, display the instruction “Instruction 2” at IP = 0x50000004, display the instruction “bra loop_A” at IP = 0x50000008 in Step 2102, and branch directly. Set the destination address 0x50000014 (loop_A) to IP. In step 2103, since the branch flag valid flag still remains, the process returns to step 2101 again. This time, the instruction “loop_A: instruction 3” at IP = 0x50000014 and “instruction 4” at IP = 0x50000018 are displayed. In step 2102, “bne loop_A” at IP = 0x5000001c is displayed and the branch flag is 1. Therefore, the branch destination address 0x50000014 (loop_A) is set directly in the IP. Similarly, IP = 0x50000014 to IP = 0x5000001c are repeated 20 times. Since the number of valid flags is completed in step 2103, the process proceeds to step 2050 and TP is incremented.

  At the next TP = 1, “PTBST BR-FLAG = 0b0” is processed, but since this is also TP ≠ ETP, 2002 is skipped, proceeding to N in step 2400, proceeding to Y in step 2100, and in step 2101 = 0x50000014 address "loop_A: Instruction 3", IP = 0x500000018 address "Instruction 4" is displayed, IP = 0x5000001c address "bne loop_A" is displayed, but the branch flag is "0" The next instruction address 0x50000020 is set to IP, the process proceeds to step 2050, and TP is incremented.

  At the next TP = 2, “PTBDA U-ADDR = 0x50000300” is processed, but since this is also TP ≠ ETP, 2002 is skipped, proceeding to N in Step 2400, Step 2100, Step 2200, and proceeding to Y in Step 2300 . In step 2301, "instruction 5" with IP = 0x50000020, "instruction 6" with IP = 0x50000024, "instruction 7" with IP = 0x50000028, and "mov Sub_C, a0" with IP = 0x5000002c are sequentially displayed. Subsequently, in step 2302, the indirect branch instruction “call (a0)” of IP = 0x50000030 is displayed, and in step 2303, IP is set to the address 0x50000300 indicated by U-ADDR. In step 2050, TP is incremented to 3.

  At the next TP = 3, “PTBDA U-ADDR = 0x5000034” is processed, but since this is also TP ≠ ETP, 2002 is skipped, proceeding to N in Step 2400, Step 2100, Step 2200, and proceeding to Y in Step 2300 . In step 2301, “Sub_C: Command 9” with IP = 0x50000300 and “Command 10” with IP = 0x50000304 are sequentially displayed. Subsequently, in step 2302, an indirect branch instruction “ret” with IP = 0x50000308 is displayed. In step 2303, IP is set to an address 0x50000034 indicated by U-ADDR. In step 2050, TP is incremented to 4.

  At the next TP = 4, it is determined in step 2002 that TP == ETP, so the execution history restoration ends. The execution history thus obtained is shown in FIG.

  As shown in this example, in the present invention, the result of the direct branch instruction that conventionally required one packet is used when the branch take is continuous and shorter than the PTBST message is output. By controlling to output PTBTC messages, the highest compression efficiency is always achieved in any case.

  The processor and the development support apparatus according to the present invention are useful as means for analyzing and evaluating the operation of the processor from the outside.

The block diagram of the processor by 1st Example of this invention The figure which shows the state table of the trace message / packet control state machine of 1st Example of this invention The figure which shows TCODE definition of the trace message in 1st Example of this invention Diagram showing Message Format of Program Trace, Branch Status Message Figure showing the message format of Program Trace, Branch Destination Address Message Diagram showing the message format of Program Trace and Exception Message The figure which shows the execution log restoration algorithm by 1st Example of this invention Diagram showing source program example and execution order The figure which shows the trace information acquired when the program of FIG. 8 is executed The figure which shows the execution log | history restored | reconstructed from the program of FIG. 8, and the trace information of FIG. The block diagram of the processor by 2nd Example of this invention The figure which shows the state table | surface of the trace message / packet control state machine of 2nd Example of this invention. The figure which shows TCODE definition of the trace message in 2nd Example of this invention Diagram showing Message Format of Program Trace, Branch Taken Count Message The figure which shows the execution log restoration algorithm by 1st Example of this invention Diagram showing source program example and execution order The figure which shows the trace information acquired when the program of FIG. 16 is executed The figure which shows the execution history decompress | restored from the program of FIG. 16, and the trace information of FIG. Configuration diagram of development support equipment Configuration diagram of a conventional processor A diagram showing a state table of a conventional trace message / packet control state machine Figure showing the TCODE definition of a conventional trace message Diagram showing Message Format of Program Trace, Direct Branch Message Diagram showing Message Format of Program Trace, Indirect Branch Message The figure which shows the execution history restoration algorithm in the conventional development support device Diagram showing source program example and execution order The figure which shows the trace information acquired when the program of FIG. 26 is performed The figure which shows the execution history decompress | restored from the program of FIG. 26, and the trace information of FIG.

Explanation of symbols

1 Processor 2 Trace Information Storage Device 3 Host Computer 100 CPU
101 Instruction execution completion signal 102 Direct branch instruction execution signal 103 Indirect branch instruction execution signal 104 Conditional branch instruction condition establishment signal 105 Interrupt execution signal 110 Branch destination address 200 Trace message / packet control state machine (Type 0)
201 MSEO [1: 0] output signal (Type0)
202 MDO [7: 0] output selection signal (Type0)
220 Trace message / packet control state machine (Type2)
221 MSEO [1: 0] output signal (Type2)
222 MDO [7: 0] output selection signal (Type2)
230 Trace message / packet control state machine (Type3)
231 MSEO [1: 0] output signal (Type3)
232 MDO [7: 0] output selection signal (Type3)
310 Branch destination address update detection circuit 311 Branch destination address update signal 320 Branch take + Exception detection circuit 321 Branch take + Exception signal 330 Branch not-taken detection circuit 331 Branch not-taken signal 340 Branch execution detection circuit 341 Branch execution signal 350 Branch take detection Circuit 351 Branch take signal 410 Fixed value “0x03” for header Output circuit 420 Fixed value for header “0x04” Output circuit 430 Fixed value for header “0x38” Output circuit 440 Fixed value for header “0x39” Output circuit 450 Fixed value for header "0x3a" output circuit 460 Fixed value for header "0x3b" output circuit 500 Sequential instruction execution counter (Type0)
510 Sequential instruction execution counter value holding means (Type 0)
530 Sequential instruction execution counter (Type 2, 3)
540 Sequential instruction execution counter (Type 2, 3)
600 Branch destination address holding means 700 MDO [7: 0] output multiplexer (Type 0)
701 MDO [7: 0] output signal (Type0)
720 MDO [7: 0] output multiplexer (Type2)
721 MDO [7: 0] output signal (Type2)
730 MDO [7: 0] output multiplexer (Type3)
731 MDO [7: 0] output signal (Type3)
800 Branch flag shift register 810 Branch flag holding means 820 Branch flag counter 821 Branch flag counter value 830 Branch flag counter value holding means 900 Branch take counter 901 Branch take counter value 910 Branch take counter value holding means 1010 Trace status output terminal (MSEO) [1: 0])
1020 Trace data output terminal (MDO [7: 0])
1011 Trace status signal 1021 Trace data signal 1210 Trace memory control means 1211 Trace memory control signal 1212 Trace memory write data 1230 Trace memory 1231 Trace memory read data 1301 Trace memory read request

Claims (6)

The CPU receives the execution signal of the branch instruction and the condition establishment signal of the conditional branch instruction obtained from the CPU, and the establishment bit when executing the branch instruction when the condition is satisfied, and the unestablishment bit when executing the branch instruction when the condition is not satisfied And a trace control circuit that outputs a branch state message that summarizes all the bits stored in the shift register and information on the number of valid bits. Branch that receives the execution signal of the branch instruction and the condition establishment signal of the conditional branch instruction obtained from the CPU, increments when the branch instruction that satisfies the condition is executed, and clears when the branch instruction that does not satisfy the condition is executed A processor comprising a trace control circuit having a taken counter and outputting a branch take count message including a branch take count value. The CPU receives the execution signal of the branch instruction and the condition establishment signal of the conditional branch instruction obtained from the CPU, and the establishment bit when executing the branch instruction when the condition is satisfied, and the unestablishment bit when executing the branch instruction when the condition is not satisfied Is shifted into the shift register, and a branch state message is generated that summarizes all the bits accumulated in the shift register and the effective bit number information.
It has a branch take counter that is incremented when a branch instruction that satisfies the condition is executed, and that is cleared when a branch instruction that does not satisfy the condition is executed, and generates a branch take count message that includes a branch take count value. When the branch take count message has a shorter code, select to output the branch take count message; otherwise, from the trace control circuit that selects to output the branch status message. A processor characterized by being configured. A trace memory for inputting the branch status message according to claim 1 and storing trace information, and an execution history restoration program for reading the contents of the trace memory and restoring an execution history using a source program executed by the CPU. In the development support apparatus constituted by a computer, the execution history restoration program restored the trace information on the trace memory while corresponding to the instructions of the source program in order, and encountered a branch status message on the trace memory. Sometimes a branch instruction is made to correspond to a branch establishment / non-establishment bit. If it is an establishment bit, the history restoration point is updated at the branch destination of the branch instruction. Development support device characterized by updating points. A trace memory for storing the trace information by inputting the branch take count message according to claim 2, and an execution history restoring program for reading the contents of the trace memory and restoring the execution history using the source program executed by the CPU In the development support apparatus constituted by the computer, the execution history restoration program restores the trace information on the trace memory in order corresponding to the instructions of the source program, and generates a branch take count message on the trace memory. When it encounters, it translates the number of branch taken iterations into a sequence of branch establishment bits, associates the branch instruction with the branch establishment bit, and updates the history restoration point at the branch destination of the branch instruction in the case of the establishment bit. A development support device that is characterized. An execution history which restores an execution history using a branch memory which inputs a branch status message or a branch take count message according to claim 3, stores trace information, reads the contents of the trace memory, and uses a source program executed by the CPU. In the development support apparatus constituted by a computer having a restoration program, the execution history restoration program restores the trace information on the trace memory while sequentially corresponding to the instructions of the source program, and branches on the trace memory. When the status message is encountered, the branch instruction is made to correspond to the branch establishment / non-establishment bit. When the branch take count message on the trace memory is encountered, the branch take repetition number is translated into a branch establishment bit string, and the branch instruction Correspond to the branch establishment bit, and Expediently, branches update the history restore point branch target instruction, if not satisfied bits, development support apparatus and updates the history restore point to the next instruction of the branch instruction.

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