JP2005191901A - Laminated body board with mesh hole ground strip line structure - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a laminated body board with high performance and high reliability for executing efficient degassing having compatibility between a signal transmission line whose needs are high speed processing and a high frequency and a product of the laminated body board requiring a low cost. <P>SOLUTION: Grating hole patterns LAMH 1, LAMH 2 wherein small holes MH of the same shape are arranged in a grating form are respectively formed on upper lower ground conductors CG 1, CG 2 for configuring a strip line, and the small holes MH of the grating hole patterns LAMH 1, LAMH 2 opposed to each other are alternately arranged in a laminated direction so as to reduce the impedance Z<SB>c</SB>of the strip line. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a transmission line of a laminated substrate using a dielectric.

  With the progress of the information society, mobile communication networks such as mobile phones and satellite communications, or fixed communication networks such as the Internet and high-speed data communication have become widespread, and wireless high-frequency circuits or high-speed digital circuits used in these communication devices As a method of realizing light and thin equipment, low cost and high performance of equipment, a multilayer substrate using a dielectric has come to be used frequently. Laminate substrates are roughly classified into organic substrates using resin materials that are electrically insulating materials and inorganic substrates using alumina ceramics. In any substrate, a large amount of expensive metal conductive material such as Cu and Au is formed on the conductor layer that forms a ground conductor or ground conductor having a relatively large surface for transmitting or processing high-frequency signals or high-speed digital signals. One of the requirements for reducing the cost of a product is to reduce the amount used.

  In the case of a ceramic laminate substrate, a green sheet obtained by kneading raw ceramic powder with a solvent and an additive is processed to form a product, so that gas is generated from the substrate in the firing step. On the other hand, in the case of an organic substrate called a build-up substrate, an insulating layer is formed using a thermosetting resin or a photosensitive resin on a core substrate in which resins are stacked in multiple layers, and copper is plated thereon. A conductor layer is formed. Both the thermosetting resin and the photosensitive resin contain solvents, additives, and the like, and gas is generated when the substrate is thermoformed to cure the resin. Thus, in the manufacturing process of baking or thermoforming both substrates, the generated gas is efficiently released to shorten the required time, thereby improving the production efficiency.

An organic solvent generated from a laminate (dielectric / conductor) by forming an opening in a large-area ground conductor or the like and reducing the conductor area as a method for achieving both reduction of the metal conductive material and degassing. Etc. are efficiently discharged. As a method of releasing the generated gas by providing an opening in the ground conductor, a slit-shaped opening is provided in the ground electrode, which is one of the ground conductors, to make the generated gas easy to escape, and the ground electrode is peeled off and Patent Document 1 describes that the peeling of the dielectric layer can be effectively prevented.
Japanese Patent Laid-Open No. 5-291802

  However, providing the ground conductor with an opening such as a slit or a square that extends over the entire size of the substrate causes a problem in the characteristics of the transmission line for transmitting and receiving signals. Specifically, the center conductor is placed via a dielectric layer on the stripline, which is a distributed constant line of a conductor three-layer structure in which a center conductor is inserted between two ground conductors, or on one ground conductor. The line impedance, that is, the characteristic impedance of the microstrip, which is a distributed constant line having a conductor two-layer structure, greatly fluctuates in the vicinity of the opening.

  In particular, as the social needs for improving the performance of LSIs such as MPUs and RAMs used in digital circuits increase, the operating speed [MIPS: Million Instruction Per Second] is required, and the clock frequency is several GHz or higher. There is a need to handle digital signals with these distributed constant lines. On the other hand, in order to cope with the tight use of radio wave usage capacity such as frequency allocation for social needs that require the spread and further increase of communication equipment, the frequency band used for radio wave communication equipment such as mobile communication and wireless data communication Higher frequency is progressing, and the band of the high frequency signal that they handle is expanding from several GHz to several tens of GHz. In order to cope with such high-speed digital signals and higher-frequency radio-related high-frequency signals, the transmission line of the multilayer substrate that handles them has a stable characteristic impedance at high frequencies and a reference value of 50Ω, etc. It is necessary to maintain high accuracy with a wide band.

  The object of the present invention is to provide a high-performance and highly reliable laminate that achieves both the high-speed and high-frequency needs required for a laminate substrate as described above and the degassing method for realizing the cost reduction required for the product. It is to provide a substrate.

Means for Solving the Problems and Effects of the Invention

In order to solve the above problems, a multilayer substrate having a mesh hole ground strip line structure according to the present invention includes a first conductor layer, a first dielectric layer, a second conductor layer, a second dielectric layer, and a third conductor layer. In the laminate substrate laminated in this order,
In the first conductor layer, holes of the same shape penetrating the conductor layer in the thickness direction are arranged in the first direction at the first interval D _P1 , and on the other hand in the second direction orthogonal to the first direction at the second interval D _P2 A first ground conductor having a first grid-shaped hole pattern arranged is formed;
In the second conductor layer, a strip-shaped conductor pattern whose center line is parallel to the first direction of the first lattice-shaped hole pattern is formed as a central conductor,
The third conductor layer is formed with a second ground conductor having a second lattice hole pattern obtained by projecting the lattice hole pattern on the first conductor layer in the stacking direction,
The respective hole positions are determined so that the holes of the first lattice hole pattern on the first conductor layer and the second lattice hole pattern on the third conductor layer do not overlap,
The first ground conductor, the center conductor and the characteristic impedance Z _c of the strip line constituted by the second grounding conductor, the characteristics of the strip line when grid-like hole pattern on the first ground conductor and the second grounding conductor is not arranged When the impedance is Z ₀ , the hole opening diameter D _H and the distance between the first grid hole patterns formed in the first ground conductor and the second ground conductor so that Z _c falls within Z ₀ + 10%. D _P1 and D _P2 are defined.

The multilayer substrate having the mesh hole ground stripline structure according to the present invention is arranged with a distance D _P1 in the first direction and a distance D _P2 in the second direction perpendicular to the first direction on the first ground conductors constituting the strip line. The first lattice-shaped hole pattern thus formed is provided on the second ground conductor with a second lattice-shaped hole pattern having the same hole arrangement as the first lattice-shaped hole pattern. The first grid hole pattern on the first ground conductor and the second grid hole pattern on the second ground conductor are arranged so that the holes do not overlap each other in the hole arrangement. It is configured to be parallel to one direction (see FIG. 1). The characteristic impedance Z _c of this strip line is Z ₀ (typically this value is 50 Ω of the reference value). The interval D _P1 and D _P2 of the lattice-like hole pattern and the hole opening diameter D _H are determined so that Z _c falls within Z ₀ + 10%.

In this way, small holes (openings) are uniformly distributed on the ground conductor surface so that the gas generated from the multilayer substrate can be easily released from the ground conductor surface. This stabilizes the performance of the signal transmission line for high-speed digital signals and high frequency signals by suppressing the characteristic impedance Z _c of the strip line is a signal transmission line within Z ₀ + 10% of the reference characteristic impedance Z _0, it can be improved . Since the grid-like hole pattern uniformly arranged in a grid is arranged on both the first ground conductor and the second ground conductor, the generated gas can be evenly dispersed and released, and the gas can be efficiently extracted. . As a result, it is possible to eliminate peeling, cavities, irregularities, and undulations generated between the conductor layer such as the ground conductor and the center conductor and the dielectric layer, and the residual stress remaining between the conductor layer and the dielectric layer. Since it can be removed, the reliability / quality of the product of the laminated substrate is improved. Regarding the electrical performance of the signal transmission line, if the hole opening diameter D _H is close to the shape of the center conductor of the strip line (especially its width and distance from the ground conductor), the hole is also covered by the entire area. When the ratio of closing is small, the deviation from the reference value Z ₀ : Z _c −Z ₀ can be made small (see FIGS. 5 and 7).

The multilayer substrate having the mesh hole ground strip line structure of the present invention is configured such that the center line of the central conductor is positioned directly above the hole arrangement of the first lattice hole pattern in the stacking direction of the multilayer substrate, The characteristic impedance Z _c can be configured to fall within Z ₀ + 10% of the characteristic impedance Z ₀ . In this way, the overlap of the hole arrangement (BT1, BT2) of the first grid hole pattern of the strip line center conductor and the first ground conductor is symmetric with respect to the center line of the center conductor and the distance between them is even. Is uniformly distributed in the direction of the line length. At this time, the hole arrangement (ST1 and others) of the second grid-like hole pattern of the second ground conductor does not enter below the center conductor and its coupling region. That is, since the center conductor does not overlap the opening of the hole arrangement on the second ground conductor, the influence of the opening is approximately half that of the case where the center conductor overlaps both openings of the first ground conductor and the second ground conductor. (See FIG. 3, details will be described later). Therefore, the balance of the transmission line is improved, and the deviation in which the characteristic impedance Z _c of the signal transmission line increases from the reference characteristic impedance Z _{0 due} to the influence of the opening of the hole is further reduced (see FIG. 3 and Table 1). be able to. Center conductor and the overlap of the hole is biased may for characteristic impedance Z _c of the strip line results in uneven band characteristic of the signal frequencies, may affect the performance of the signal transmission line.

Further, in the multilayer substrate having the mesh hole ground strip line structure of the present invention, the opening ratio of the hole opening diameter D _H to the first interval D _P1 of the first lattice hole pattern is D _H / D _P1 , and the characteristic impedance Z _c May be configured such that the opening ratio D _H / D _P1 of the first grid-like hole pattern formed in the first ground conductor is determined so as to fall within Z ₀ + 10% of the characteristic impedance Z ₀ . In this case, since the opening area ratio of the grid-like hole pattern formed in both the first ground conductor and the second ground conductor is made constant, efficient gas discharge and characteristic impedance proportional to the total opening area are achieved. The performance of Zc can be made compatible. For example, when the aperture ratio D _H / D _P1 ≈0.45, a good characteristic impedance of Zc ≦ Z ₀ + 10% is obtained, and the aperture area ratio = (total hole area / ground conductor area) ≈16% Outgassing can be achieved. In the case of substantially overlapping holes arranged on the central conductor and the first ground conductor also has to is any deviation of the difference between the characteristic impedance Z _c and the reference characteristic impedance Z ₀ of the laminate substrate having a mesh hole ground strip line structure The impedance ΔZ is ΔZ≈E × (D _H / D _P1 ) / {1−F (D _H / D _P1 )} ----- (1) (where E and F are proportional constants) (See (32) and (304)). Therefore, by selecting the aperture ratio (D _H / D _P1 ) within an appropriate range, the deviation impedance ΔZ is reduced, and the characteristic impedance Z _c of the multilayer substrate having the mesh hole ground strip line structure is brought close to the reference characteristic impedance Z ₀ . be able to.

The multilayer substrate having a mesh hole ground strip line structure according to the present invention has a constant opening ratio D _H / D _{P1 of} the first grid-like hole pattern, and a surface in contact with the first dielectric layer of the first ground conductor. In the strip line where the distance between the surface of the second ground conductor and the surface in contact with the second dielectric layer is B, and the center line of the center conductor having the band width w is located at the midpoint of the distance B,
D _P2 −D _H ≧ (w + B) / 2 and S ≦ w + B where S is the side length of an equal-area square opening having the same area as the circular hole area of the hole opening diameter D _H of the first lattice hole pattern It can also be configured to satisfy. In this way, each hole of the hole array overlapping the central conductor on the first ground conductor is positioned directly below the center conductor affects the characteristic impedance Z _c of the laminate substrate having a mesh hole ground strip line structure The whole hole fits within the range equivalently (exactly, an equal area square opening having the same area as the circular hole fits within the range) and the holes of the hole arrangement on the second ground conductor do not overlap this range . In this case, uniquely (FIG sequence conditions, i.e. at intervals D _P1 and the hole opening diameter D _H of the hole array characteristic impedance Z _c of the laminate substrate having a mesh hole ground strip line structure overlapping the center conductor 5 See) Since it is not affected by the adjacent hole arrangement of the first ground conductor and the second ground conductor (see FIG. 3), the influence of the holes on the multilayer substrate having the mesh hole ground stripline structure becomes simple. frequency characteristics of the well without the characteristic impedance Z _c partial change of the position of the transmission line can be flat and stable. The above-mentioned range R _i that affects the characteristic impedance Z _c is given as R _i ≈w + B ----- (2) where B is the distance between the first ground conductor and the second ground conductor. The range is an area (refer to FIG. 3) inside two parallel lines (AB / CD) separated by H = B / 2 from the edge of the central conductor of the band width w.

In the multilayer substrate having a mesh hole ground strip line structure according to the present invention, the thickness of the central conductor is t, the relative dielectric constant of the first dielectric layer and the second dielectric layer is ε _r , and S is S ≧ w. When
Characteristic impedance Z _c : Z _c ≈ Z ₀ + {15K / (ε _r ) ^1/2 } (S _c / l _A ), correction coefficient associated with the shape of the inductance of the center conductor: k ≈ [log _e {S _c / (w + t)}] + 1.193 + 0.2235 (w + t) / S _c , correction coefficient for the aperture ratio D _H / D _P1 : S _c / l _A ≈0.781 (D _H / D _P1 ) / {1−0.781 (D _H / D _P1 )}, correction coefficient associated with the decrease in capacitance per unit length formed by the center conductor and the upper and lower ground conductors by the hole: K≈k−4.43 × 10 ⁻⁵ × Z ₀ ² × ε _r {2w /(B−t)+(1.13π/2)×(t/H) ^1/4 × {1 + 1.13log _e [2.41H / (d _b + (H ² + d _b ² ) ^1/2 )]}} The distance between the center line of the center conductor and the upper and lower ground conductors: H = B / 2, side length of the equal area square opening having the same area as the circular hole with the diameter _DH : S = 0.886D _H , Correction associated with reduction in aperture size due to edge effect capacitance: S _c = S log _e {1+ (2) ^1/2 }, the length of the equivalent square reduced aperture protruding from the center conductor of band width w: 2d _b = (S It is preferable to determine the characteristic impedance Z _c represented by a series of relational expressions composed of _c −w) so that Z _c −Z ₀ is minimized.

With this configuration, the characteristic impedance Z _c is given by Z _c ≈Z ₀ + {15 K / (ε _r ) ^1/2 } (S _c / l _A ) ----- (3), and mesh hole ground By optimizing the shape and configuration (w, t, B, D _H , D _P1 , D _P2 ) of the laminate substrate having the stripline structure, the difference between the characteristic impedance Z _c and the reference characteristic impedance Z ₀ A certain deviation impedance ΔZ can be minimized (see (303) and (304) described later). In the prototype evaluation stage, the deviation impedance ΔZ can be set to ΔZ ≦ 3Ω, and the laminate substrate having the mesh hole ground stripline structure of the present invention is used as a 50Ω transmission line (various distributed constant lines usually used). When connected, it is possible to obtain the best transmission characteristics.

Hereinafter, the best mode of a laminate substrate having a mesh hole ground strip line structure of the present invention will be described with reference to the accompanying drawings. FIG. 1 shows a schematic basic structure of a laminate substrate (hereinafter referred to as “MHGSL”) having a mesh hole ground strip line structure of the present invention. In [1A], MHGSL1 has a first conductor layer CL1 having a first ground conductor GC1 (hereinafter also referred to as a “lower ground conductor”) having a thickness of 14.5 μm, a relative dielectric constant ε _r at a thickness H≈40 μm. A dielectric layer DL1 having a central conductor MC (hereinafter also referred to as “line”) having a thickness of 14.5 μm, a dielectric layer DL2 having a thickness H≈40 μm and a relative permittivity ε _r ; The third conductor layer CL3 having a second ground conductor GC2 (hereinafter also referred to as “upper ground conductor”) having a thickness of 14.5 μm is laminated in the order from the bottom layer to the top layer. The first ground conductor GC1 and the second ground conductor GC2 are respectively formed with a first grid hole pattern LAMH1 and a second grid hole pattern LAMH2 in which holes MH having the same shape are arranged in a grid. The holes in the hole arrangement of the first lattice hole pattern LAMH1 and the hole arrangement of the second lattice hole pattern LAMH2 are arranged so as not to overlap with each other in the direction of the laminated surface.

Details of the first grid-like hole pattern LAMH1 formed on the first ground conductor GC1 of the MHGSL of the present invention are shown in [1B]. The opening diameter (diameter) of the hole MH having a circular opening is _DH , and this MH has a first interval (distance between the centers of adjacent MHs) D _P1 in the first direction parallel to the center conductor MC, and the center conductor. The central conductor MC, which is a strip-like conductor pattern having a width w, is arranged in a grid pattern in the second direction orthogonal to the MC at intervals D _P2 and is located immediately above one hole array in the first direction. Details of the second grid-like hole pattern LAMH2 formed on the second ground conductor GC2 of MHGSL are shown in [1C]. The opening diameter (diameter) of the hole MH having a circular opening is similarly D _H , and this MH is a first interval (distance between the centers of adjacent MHs) D _P1 in the first direction parallel to the central conductor MC, and disposed in a second direction perpendicular to the center conductor MC at intervals D _P2 in a lattice shape, the center conductor MC is strip conductor pattern having a width w is positioned directly above the center of the gap between two holes arranged in the first direction .
As shown in FIG. 2, the actual product form is composed of a composite laminate substrate 10 in which transmission lines / filters using MHGSL shown in FIG. . In this case, the center conductor MC can adopt a meander line structure or the like, and the line length can be set to an optimum value (for example, 1/4 wavelength).

Here, a specific configuration of the composite laminate substrate 10 employing the MHGSL1 of the invention will be described by taking an inorganic substrate using alumina ceramic as a dielectric material as an example. Each dielectric layer DL (DL1, DL2) is formed of a dielectric material having a dielectric constant epsilon _r, alumina ceramics in the dielectric material and the alumina content is 98% or more, mullite ceramics, aluminum nitride ceramics A material having a small dielectric loss in the high frequency region, such as silicon nitride ceramics, silicon carbide ceramics, and glass ceramics, is applied. In this case, the relative dielectric constant ε _r is adjusted to ε _r = 5-20. Each conductor layer CL (CL1, CL2, CL3) has a distributed constant line (strip line, etc.), capacitor electrodes, or a ground plane (ground conductor, etc.) made of a metal conductor. For example, when glass ceramics is used as the material for the ceramic dielectric layer, a material mainly composed of Ag, Au, or Cu can be used.

  Next, the manufacturing method of the composite laminated substrate 10 which employ | adopted MHGSL1 of this invention is demonstrated easily. First, a ceramic green sheet to be the dielectric layer DL is prepared. The ceramic green sheet is made of ceramic ceramic raw material ceramic powder (for example, in the case of glass ceramic powder, mixed powder of borosilicate glass powder and ceramic filler powder such as alumina) with a solvent (such as acetone) and a binder [acrylic. Additives such as plastic resins (for example, polyacrylic acid esters), plasticizers (such as butyl benzyl phthalate), and peptizers [such as fatty acids (such as glycerin trioleate)] are kneaded and mixed by a doctor blade method or the like. It is formed into a sheet shape.

  Then, on this ceramic green sheet, various conductive patterns (such as a grid-like hole pattern LAMH1, LAMH2 or a strip pattern of the central conductor MC) or electrode conductors which are conductor layers CL (including a ground conductor and a central conductor) or electrode conductors are coated with metal powder. Used to form a predetermined shape. This metal powder shape is formed by a known screen printing method using a paste of metal powder mainly composed of Cu or Ag. When the metal powder shape of the conductor layer is formed, another ceramic green sheet is overlaid thereon, and the process of metal powder shape printing / ceramic green sheet lamination is repeated to obtain a green laminate to be the ceramic laminate substrate 10. The green laminate described above is formed by continuously forming a plurality of conductor layer metal powder shapes of individual ceramic laminate substrates 10 (using the MHGSL1 of the present invention) in a predetermined arrangement and arrangement. By using and cutting and separating along the cutting line, separate green laminates to be individually formed into the ceramic laminate 10 are obtained. By firing this, a composite laminate substrate 10 as shown in FIG. 2 is obtained.

When an organic substrate is formed by laminating resin materials by the build-up method, each dielectric layer DL1, DL2 is formed of a resin dielectric sheet, for example, a build-up layer composed of a photosensitive resin. ing. The photosensitive resin composition is composed of epoxy resin (FR4: Fiber Reinforced) or the like, and the relative dielectric constant ε _r is adjusted to ε _r = 2-4. The manufacturing method of the laminated substrate 10 using a resin as a dielectric is as follows. Lattice hole pattern LAMH1, LAMH2, strip pattern, etc. by coating photosensitive resin on the core substrate in which resin is laminated in multiple layers, and exposing and developing a photomask for producing conductor pattern on it with ultraviolet rays A photo via corresponding to the conductor pattern is formed. After the surface of the resin is roughened with a surface treatment agent or the like, electroless copper plating is performed to form a copper thin film on the photo via portion, and further, electrolytic copper plating is performed to form a conductor layer having a predetermined thickness (several tens of um) as described above. It is formed according to the pattern. Dielectric layers (equivalent to dielectric layers DL1 and DL2) and conductor layers (equivalent to CL1, CL2, and CL3) are alternately laminated by repeating the process of electrolytic copper plating from this photosensitive resin coating, and a multilayer substrate A resin sheet in which 10 are continuously arranged in a planar shape is produced. By separating and separating this resin sheet along a cutting line using a cutter, a separate resin sheet that is to become the organic laminate substrate 10 is obtained. Finally, this separated resin sheet is heat-treated to cure the resin layer, the resin layer is cured, and the composite laminate substrate 10 is obtained.

  As described above, when the ceramic laminate substrate is manufactured, a green sheet obtained by kneading the raw ceramic powder with a solvent, an additive, and the like is processed to form a product, and thus gas is generated from the substrate in the firing step. Also, in the manufacture of organic substrates called build-up substrates, a conductor layer is formed by forming an insulating layer on a core substrate in which resins are stacked in multiple layers using a thermosetting resin or a photosensitive resin, and copper plating on the insulating layer. Form. Both the thermosetting resin and the photosensitive resin contain a solvent, an additive, and the like, and gas is generated when the resin is cured by heat-treating the substrate. In this way, the gas generated in the manufacturing process of the substrate firing or heat treatment is efficiently released by distributing the mesh-shaped small holes MH in each conductor layer sandwiching the dielectric layer, and the ceramic firing process or Reducing the time required for the resin heat treatment process leads to an improvement in production efficiency.

Since the above-mentioned lattice-shaped hole patterns LAMH1 and LAMH2 in which small holes MH are uniformly arranged in a lattice shape are arranged on the first ground conductor and the second ground conductor, respectively, the effect of evenly distributing and releasing the generated gas And the gas generated in the laminate substrate 10 can be released. As a result, it is possible to eliminate peeling, cavities, irregularities, undulations, etc. that may occur between the conductor layer such as the ground conductor and the center conductor and the dielectric layer, and remain between the conductor layer and the dielectric layer. Since the residual stress can be removed, the reliability / quality of the laminated substrate product can be further improved. How to arrange the holes MH in the respective lattice-like hole patterns LAMH1 and LAMH2 formed on the first ground conductor GC1 and the second ground conductor GC2 (hole opening diameter D _H , first interval D _P1 , second interval D _(P2 and upper / lower hole position) With this condition setting, the characteristic impedance Z _c (line impedance) of the multilayer substrate MHGLS1 having the mesh hole ground stripline structure is not provided on the first ground conductor GC1 and the second ground conductor GC2 with the lattice hole patterns LAMH1 and LAMH2. In other words, how close it is to the characteristic impedance Z ₀ (hereinafter, this impedance is referred to as “reference impedance”) of the strip line having a solid ground is the central subject of the present invention. Therefore, the relationship between the deviations ΔZ, ΔZ = Z _c −Z ₀ ----- (20) of the characteristic impedance Z _c with respect to the reference impedance Z ₀ and the optimal arrangement of the holes MH in the lattice-shaped hole patterns LAMH1, LAMH2 will be sequentially described. To do.

Results of main points of the high-frequency line analysis of the characteristic impedance Z _c of the laminate substrate MHGLS1 with mesh hole ground stripline structure revealed in the design and development process of the evaluation in the invention are as follows. In this case, the description of the normally known circuit analysis / line analysis process is omitted. First, the characteristics of the line model of the multilayer substrate MHGLS1 having a mesh hole ground stripline structure to be analyzed will be described with reference to FIG. The following relationship exists between the hall MH arranged under the central conductor MC of the line and the line structure. When the distance between the first ground conductor GC1 and the second ground conductor GC2 shown in FIG. 5 is B, and B = 2H ---- (21), the line width w (band-like pattern) The center of the central conductor MC is located.

The total capacitance C _t per unit length in the line length direction formed by the center conductor MC, the first ground conductor GC1, and the second ground conductor GC2 is approximately two parallel lines AB at a distance H from both ends of the center conductor (line) MC. It was found that this occurs due to the coupling of the center conductor MC, the first ground conductor GC1, and the second ground conductor GC2 in the coupling region sandwiched between the CDs. Two holes MH1, MH2 line direction adjacent on the first grounding conductor GC1, i.e. the first interval of the first direction D _P1, the hole opening diameter of the holes MH1, MH2 and D _H. If the reduced correction equivalent square openings SQ _c for the holes MH1 and MH2 defined in FIG. 4 are SQ _c 1: BT1, SQ _c 2: BT2 and the side length is S _c , the reduced correction equivalent square from the end of the line MC. The distances to the opening ends APE _R and APE _L of the opening SQ _c are d _b respectively. Further, the end-to-end distance l _A between the adjacent reduced correction equivalent square openings SQc1 and SQc2 is given by l _A = D _P1 −S _c ----- (22). When the reduced correction equivalent square opening SQ _c on the second ground conductor GC2 is ST1, the gap d _a between the boundary line CD of the coupling region and the reduction correction equivalent square opening ST1 is d _a = {Dp− (B + w + Sc)} / 2 ----- Since (23), the aperture ratio D _H / D _P = 0.45, S _c ≈0.781D _H , B = 80.5um, w = 31um, D _H = 75 to 250um d _a ≈0 μm to 120 μm, and it can be seen that the reduced correction equivalent square opening SQ _c on the second ground conductor GC2 does not substantially fall within this coupling region. In other words, it has been found that the reduced correction equivalent square opening SQ _c on the second ground conductor GC2 hardly affects the characteristic impedance Z _c of the multilayer substrate MHGSL1 having the mesh hole ground stripline structure.

Next, the relationship among the hole MH, the equal area square opening SQi, and the reduced correction equivalent square opening SQc will be described with reference to FIG. And equal area square opening SQi having the same area as the opening area of the hole MH opening diameter D _H, is the side length and S. The end effect capacitance C _Sf for the equal area square opening SQi, the side length of the corrected reduced opening of equal area squares opening SQi reduction correction equivalent square opening SQc and S _c. At this time, S = {(π) ^1/2 /2}≒0.886D _H ----- (24), S _c = S log _e {1+ (2) ^1/2 } ≒ 0.881S ----- Therefore, S _c ≈0.781D _H ----- (26) is obtained.

Next, the cross-sectional configuration of the MHGSL1 in the line length direction and the capacitance generated by the coupling between the lower ground conductor GC1, the upper ground conductor GC2 and the center conductor (line) MC will be described with reference to FIG. As described above, the reduced correction equivalent square opening SQ _c on the second ground conductor (upper ground conductor) GC2 does not affect the characteristic impedance Z _c of the multilayer substrate having the mesh hole ground strip line structure. The reduced correction equivalent square opening SQcb by the first grid hole pattern formed in the first ground conductor (lower ground conductor) CG1 is located immediately below the line width w. When the dielectric constant of vacuum is ε ₀ and the relative dielectric constant of the dielectric is ε _r , the interelectrode capacitance C _p1 formed between the center conductor MC and the upper ground conductor GC2 is given by (101) since the lower ground conductors GC1 directly under the central conductor MC is an opening S _c, S _c ≧ w, if it has a relationship of _{S c ≦ w + B ----- (} 27), this Itakyoku The inter-capacitance C _p1 is C _p1 = 0 −−−−− (102).

End effect capacitance C _f formed between the center conductor MC having a thickness t and the lower ground conductor GC1 or the upper ground conductor GC2 (the bottom where the electric lines of force extending radially from the side surface of the center conductor MC are below or above it. Capacitance generated by the coupling between both of the grounding conductor GC1 and the upper grounding conductor GC2 is approximated by (103) as a result of various electromagnetic analysis and computer analysis (one of the major features of the present invention) I understood that I can do it. Reduction correction equivalent distance d _b at the end of the opening end and the center conductor MC square opening SQcb is given by _{d b = (S c -w)} / 2 ----- (28), reduced end by the opening SQcb The effect capacities C _f1 and C _f2 can be expressed by (104). From the above, assuming that the total capacity per unit length (um) in the line length direction is C _t , g (B, t, w) ≡C _t / (ε ₀ ε _r ) = 2w / (Bt) + ( 1.13π / 2) (t / H) ^1/4 {1 + 1.13log _e [H {1+ (2) ^1/2 } / {d _b + (d _b ² + H ² ) ^1/2 }]} --- -(106).

Then, when the line shown in FIG. 3 described above are continued, derives the reflection coefficient gamma _T to the characteristic impedance Z _c of the line it is MHGSL1 forms. FIG. 6 shows an equivalent circuit of the MGHSL1 line of the present invention. Series inductance L _s and a ground capacitance C _s block surrounded by a broken line is composed of a circuit ECS1, --- ECSN Member is corresponding to the side length S _c of the equivalent circuit (square openings reduction correction equivalent square opening SQc portion of FIG. 3 The grounding capacitance C _s is related to the total capacitance C _t per unit length in FIG. The combined impedance of the block circuits ECs1 and --Ecsn is defined as Z _s and the reflection coefficient is defined as Γ _s . In FIG. 3, the region of the line length l _A having no opening is connected before and after each of the block circuits ECs1, --- Ecsn, and is a unit split line having a reference impedance Z ₀ , an electrical length θ _A , and a line length l _A It corresponds to. When n holes MH (reduction-corrected equivalent square aperture SQc) are formed in the hole array located immediately below the central conductor MC in MHGSL1, the equivalent circuit of the line of MHGSL1 is the block circuit ECs1, --ECsn N unit divided lines (Z ₀ , θ _A , l _A ) sandwiched between them are connected in series. Here, the impedance of each part of the equivalent circuit and the reflection coefficient thereof are obtained as follows. The combined impedance Z _s of the block circuits ECs1 and --Ecsn is Ls, which is the inductance that causes the reduced correction equivalent square aperture SQc, and the ground capacitance C _s associated with the total capacitance C _t per unit length in FIG. 5 is C _s = S _c C _t ----- is approximated by (29) to the _{Z s ≒ Z 0 + jω (} L s -C s Z 0 2) / 2 ----- (201). The reflection coefficient gamma _s for the synthetic impedance Z _s is given by (202), total reflection coefficient gamma _T of the equivalent circuit of the gamma _s << 1 ----- (30) is a so MHGSL1 line finally ( 205).

Since this (205) includes a phase rotation part associated with the line length 2 (n + 1) θ _A , the reflection coefficient Γ _t corresponding to the characteristic impedance Z _c of the MHGSL1 line excluding this is (206) (202) and various relational expressions (208) are finally applied to Γ _t ≒ 7.5K / {(ε _r ) ^1/2 Z ₀ } (S _c / l _A ) ----- (209) is obtained. At this time, since the reflection coefficient Γ _{t with} respect to the characteristic impedance Z _c is Γ _t << 1 ----- (31), Z _c = Z ₀ (1 + Γ _t ) / (1−Γ _t ) ≈Z ₀ It can be approximated as (1 + 2Γ _t ) ----- (301). By applying (209) to this (301), the characteristic impedance Z _c is finally Z _c ≈Z ₀ + {15K / (ε _r ) ^1/2 } (S _c / l _A ) ---- -Led (302). However, the coefficient K is K≈ [log _e {S _c /(w+t)}+1.193+0.2235(w+t)/S _c ] −4.43 × 10 ⁻⁵ × Z ₀ ² × ε _r g (B, t, w) ----- given by (303), representing the total capacity C _t for reduction correction equivalent square opening SQc described above (106) is applied. Therefore, the deviation ΔZ of the characteristic impedance Z _c with respect to the reference impedance Z ₀ is (302) and (20), and ΔZ≈ {15K / (ε _r ) ^1/2 } (S _c / l _A ) ----- ( 304). When the action of (304), which is the greatest feature of the present invention, is roughly analyzed, first, S _c / l _A ≈0.781D _H / (D _P1 −0.781D _H ) = 0.781 (D _H / D _P1 ) /{1-0.781(D _H / D _P1 )} ----- (32)
If the value is made smaller (that is, the aperture ratio: (D _H / D _P1 ) is made smaller), the deviation ΔZ proportional to it will naturally become smaller. If, S _c / l _A constant [i.e., opening _{ratio: (D H / D P1)} = constant] and when is, S _c ≒ 0.781D _H ----- given by (25) S _c Is reduced (ie, the opening diameter D _H of the hole MH is reduced), d _b = (S _c −w) / 2 −−−−−−, d _b given by (28) also becomes smaller, and g given by (106) Since (B, t, w) becomes large, it can be seen that the coefficient K finally given by (303) becomes small and the deviation ΔZ can be made small.

FIG. 7 shows the result of calculation processing of the above series of relational expressions (302), (303), (106) using the spreadsheet software Excel of Microsoft Corporation in the United States. In this numerical analysis, the relative permittivity of the dielectric of the multilayer substrate 10 is ε _r = 2.9, the stripline shape is such that the distance between the upper and lower ground conductors GC1 and GC2 is B = 80.5 μm, and the width of the center conductor MC. And thickness are set as w = 31um and t = 14.5um respectively, and the characteristic impedance (reference line impedance) of the strip line (solid ground) without the grid-like hole pattern LAMH in the upper and lower ground conductors GC1 and GC2 is Z ₀ = 50Ω. At this time, the combination of the hole interval D _P (= 550, 220, 165, 110 um) hole opening diameter D _H (= 250, 100, 75, 50 um) with respect to the lattice-shaped hole pattern LAMH is changed, and the mesh hole of the present invention is changed. It was determined characteristic impedance (line total impedance) Z _c of the laminate substrate MHGSL1 with ground strip line structure. In any of the analysis 1, 2, 3, 4 in FIG. 7, the opening ratio is constant at D _H / D _P ≈0.45, but when the hole opening diameter D _H is the second smallest D _H = 75 μm, deviation [Delta] Z of the reference impedance Z ₀ = characteristic impedance Z _c of the laminate substrate MHGSL1 with mesh hole ground strip line structure for 50Ω is as small as 6% of ΔZ ≒ 3.00Ω and Z _0. Finally, the results of electromagnetic analysis simulation for MHGSL1 of the present invention are shown in Table 1, and the effects of the present invention will be briefly described. This simulation was performed by applying FDTD (Finite Different Time Domain) electromagnetic analysis simulation using Applied Simulation Technology's ApsimFDTD.

The difference of the characteristic impedance of Table 1 from FDTD simulation results Z _c and the high-frequency line analysis result characteristic impedance Z _c is a 1/10 (Omega) below about 4Ω, D _H = 75um in D _H = 250 um, the present invention of MHGSL1 is enough opening diameter D _H of the hole MH is small, it can be seen that can be designed with high accuracy. The minimum value of the deviation [Delta] Z of MHGSL1 characteristic impedance Z _c of the present invention with respect to the reference impedance Z ₀ can be seen to fall within approximately Z ₀ + 10% of [Delta] Z ≒ 3 [Omega] and the reference impedance. Also, according to FIG. 7, Z _c ≈51Ω is obtained in the best combination of D _P = 110 (um) and D _H = 50 (um) under the constant condition of aperture ratio D _H / D _P ≈0.45. Yes. This indicates that the electrical performance of the multilayer substrate MHGSL1 having the mesh hole ground strip line structure of the present invention is excellent. From the above results, it has been found that the MHGSL1 of the present invention has a great effect in terms of both the productivity of efficiently releasing generated gas in the manufacturing process and the electrical performance of optimizing the line impedance.

The schematic structure figure which shows the basic composition of the laminated body board | substrate which has the mesh hole ground strip line structure of this invention. The schematic structure figure of the composite laminated substrate which employ | adopted the laminated substrate which has a mesh hole ground strip line structure of this invention. The figure explaining the positional relationship of the hole of the grid | lattice-like hole pattern in the laminated substrate which has the mesh hole ground stripline structure of this invention, and the center conductor of a track | line. The figure which shows the relationship between the circular hole opening of the grid | lattice-like hole pattern formed in the up-and-down ground conductor, the equal area square opening, and the reduction correction equivalent square opening. The figure explaining the capacity | capacitance which arises by the coupling | bonding of the center conductor of a laminated body board | substrate which has a mesh hole ground stripline structure of this invention, and a vertical ground conductor. The equivalent circuit diagram showing the periodic structure which consists of the equivalent circuit of the hole opening part in the laminated body board | substrate which has the mesh hole ground stripline structure of this invention, and the line | wire of a hole space | interval part. The figure which shows the calculation result of calculation software Excel which applied the relational expression which derives | leads-out the characteristic impedance of the laminated body board | substrate which has the mesh hole ground stripline structure of this invention.

Explanation of symbols

1 Laminated substrate with mesh hole ground stripline structure (MHGSL, signal transmission line, line, stripline)
10 Composite laminate substrate
CL1, CL2, CL3 Conductor layer
DL1, DL2 dielectric layer
LAMH1, LAMH2 Lattice hole pattern
MH1, MH2 hall
CG1 First ground conductor (lower ground conductor)
CG2 Second ground conductor (upper ground conductor)
MC center conductor (strip conductor pattern, track)
SQi equal area square aperture
SQc Reduction correction equivalent square aperture
C _p plate electrode capacitance
C _f edge effect capacity
Z _c characteristic impedance
Z ₀ standard characteristic impedance (reference impedance)
ΔZ Deviation impedance (deviation between characteristic impedance Z _c and reference impedance Z ₀ )
D _P1 1st hole interval
D _P2 2nd hole interval
D _H hole opening diameter
D _H / D _P opening ratio
S Side length of equal area square opening
Side length of S _c reduction correction equivalent square opening
B Distance between upper and lower ground conductors (distance between conductors)
w Band width (width) of center conductor
t Center conductor thickness
C _t Total capacity per unit length
Ec _s block circuit Γ _T , Γ _t , Γ _s reflection coefficient
BT1, BT2 Reduction correction equivalent square opening of the first ground conductor
ST1 Reduction correction equivalent square opening of the second ground conductor

Claims (1)

In the laminated substrate in which the first conductor layer, the first dielectric layer, the second conductor layer, the second dielectric layer, and the third conductor layer are laminated in this order,
In the first conductor layer, holes having the same shape penetrating the conductor layer in the thickness direction are arranged in the first direction at the first interval D _P1 , and the second interval D _P2 in the second direction orthogonal to the first direction is arranged. A first ground conductor having a first lattice-shaped hole pattern arranged in a
A strip-shaped conductor pattern whose center line is parallel to the first direction of the first lattice-shaped hole pattern is formed as a central conductor on the second conductor layer,
A second ground conductor having a second grid hole pattern formed by projecting the grid hole pattern on the first conductor layer in the stacking direction is formed on the third conductor layer,
The respective hole positions are determined so that the holes of the first lattice hole pattern on the first conductor layer and the second lattice hole pattern on the third conductor layer do not overlap,
Said first ground conductor, the center conductor and the characteristic impedance Z _c of the formed strip line by said second ground conductor, said grid-like hole pattern on the first ground conductor and said second ground conductor is not arranged the characteristic impedance of the strip line in the case when a Z _0, Z _c is to fit Z ₀ + 10% within the first grounding conductor and the second formed in said grounding conductor first grid-like hole pattern A laminated substrate having a mesh hole ground strip line structure, characterized in that the hole opening diameter D _H and the distances D _P1 and D _P2 are defined.

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