JP2005184440A - Stream packet transmitter, stream packet transmission control method, program and recording medium - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that it is difficult to secure transmission quality as stream information becomes like bursts when packetized by a conventional method. <P>SOLUTION: A stream packet transmitter includes a timer means 107 for generating an event signal every predetermined period and descriptor processing means 104 and 106 for processing a second descriptor describing packet information carrying successively generated stream information according to timing at which the event signal is generated, and processing a first descriptor describing packet information carrying information other than the stream information as needed. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a stream packet transmission apparatus and a stream packet transmission control method on the transmission side of an apparatus that transmits information having temporal continuity such as audio and moving image, generally called stream information, over a network.

  In a network transmission / reception apparatus, generally, DMA (direct data transfer) is used for data transfer between a CPU (central processing unit) that handles information to be transmitted / received in the apparatus and a controller that transmits / receives a packet to / from a data link constituting the network. Memory access) is used.

  In order to improve the efficiency of data transfer, instead of performing DMA for each piece of data, for example, every packet, a descriptor describing information necessary for performing DMA is prepared, and the descriptors are further chained. Thus, a series of data can be continuously performed without CPU intervention (see, for example, Patent Document 1).

  FIG. 3 is a block diagram showing a configuration of a conventional packet transmission apparatus. First, the CPU 301 writes data to be transmitted to the main memory 303 through the bus 302. FIG. 3 shows four pieces of data.

  Next, the CPU 301 writes a descriptor including information on the start address of the data on the main memory 303 and its length into the main memory 303. The same four descriptors as data are written in the main memory 303.

  In this state, the CPU 301 gives an operation instruction to the descriptor processor 304. More specifically, a write address of the first descriptor on the main memory 303 is given and an instruction to read the descriptor information is given.

  The descriptor processor 304 reads the data write address and length information from the read descriptor information, and provides the data to the DMA controller 305. The DMA controller 305 reads data from the main memory 303 through the bus 302 and transfers it to the transmission queue 306.

  The data link controller 307 checks the state of the network, reads data from the transmission queue 306 when transmission to the network becomes possible, and transmits data to the network.

  When one descriptor process is completed, the interrupt generator 308 generates an interrupt signal to the CPU 301.

  The descriptor processor 304 repeats the above operation until all the descriptors written on the main memory 303 are processed. As a result, all the data that the CPU 301 initially writes to the main memory 303 is transmitted from the network.

As described above, the CPU 301 can transmit data by preparing data to be transmitted and a corresponding descriptor once and starting the operation of the descriptor processor 304.
JP-A-6-244902

  However, when transmitting information that is continuous in time, such as audio and video, generally called stream information, using the transmission device as shown in FIG. 3, packets to be transmitted are continuous. A phenomenon occurs in which a descriptor is processed in bursts.

  In other words, since descriptors and data prepared at a time are continuously processed, the transmission interval of those packets is short, and transmission is not performed until the next time descriptors and data are prepared. The interval becomes longer.

  FIG. 4 is a time chart showing a transmission packet and an interrupt signal by the transmission apparatus shown in FIG. Packets sent out due to the above phenomenon are in a burst form as shown in FIG. If the packet is biased to such a part of the time axis, the network load increases instantaneously, and interference with a packet flowing through another network is likely to occur. As a result, when packet transmission time varies or interference is severe, the packet is discarded.

  The stream information has a fixed amount of information per time expressed by a bit rate or the like. Therefore, the packet interval expands and contracts according to the original bit rate of the stream information, and the mutual packet interval widens, so that the packets are dispersed as much as possible on the time axis in order to ensure transmission quality in the network. desirable.

  Also in the conventional transmission apparatus shown in FIG. 3, when the processing speed of the data link controller 307 is limited and approaches the bit rate of the stream information, the interval of packets sent to the network increases, as shown in FIG. Become.

  However, in order to function as a network transmission device, packets other than stream information must also be transmitted. For example, it is necessary to exchange network address information and respond to inquiries from various other devices on the network. In addition, there are cases where it is necessary to send control information, management information, and the like of stream information even with the exchange of stream information.

  When packets other than stream information are transmitted in this way, if the packet interval is widened by limiting the processing speed of the data link controller 307 as described above, other than stream information as shown in FIG. The packet 401 is interrupted in the middle, and the packet carrying the stream information deviates from the original transmission timing.

  That is, the completion time of transmission of the stream information changes depending on the number of packets other than the stream information generated while the transmission of the stream information is continued. There is a possibility of interruption.

  Limiting the processing speed of the data link controller 307 also limits the response speed to inquiries from devices on other networks.

  As described above, in the conventional packet transmission apparatus, it is difficult to achieve both the distribution of packets carrying stream information and the high-speed processing of packets other than the stream information.

  The present invention solves the above-described problems in the prior art, and provides a stream packet transmission device, a stream packet transmission control method, and the like that achieve both the dispersion of packets of stream information and the speed of processing of packets other than stream information. The purpose is to provide.

In order to solve the above-described problem, the first aspect of the present invention provides:
Timer means for generating an event signal at predetermined intervals;
A first descriptor describing information of a packet carrying information other than stream information by processing a second descriptor describing information of a packet carrying continuously generated stream information according to the timing at which the event signal is generated. Is a stream packet transmitting device comprising descriptor processing means for processing the data as needed.

The second aspect of the present invention
When the descriptor processing means is processing the first descriptor when starting the processing of the second descriptor in accordance with the timing at which the event signal is generated, the descriptor processing means The stream packet transmitting apparatus according to the first aspect of the present invention, which processes the second descriptor continuously after the processing is completed, regardless of the timing at which the event signal is generated.

The third aspect of the present invention provides
Further, a timer that calculates a packet transmission interval based on a data amount per unit time of the stream information and a data amount included in one packet, and sets the packet transmission interval as the predetermined period in the timer means It is the stream packet transmitter of the 1st or 2nd this invention provided with the setting means.

The fourth invention relates to
Furthermore, the stream packet transmitting apparatus according to any one of the first to third aspects of the present invention, further comprising interrupt generation means for generating an interrupt signal upon completion of processing of a predetermined number of second descriptors set in advance. .

The fifth aspect of the present invention relates to
When the descriptor processing means transmits a plurality of the stream information having the same data amount per unit time in the same time zone, the descriptor processing means takes the same time zone for each event signal from the timer means. The stream packet transmitting apparatus according to any one of the first to fourth aspects of the present invention, which processes the second descriptors corresponding to the number of the plurality of pieces of stream information to be transmitted.

The sixth invention relates to
Generating an event signal at predetermined intervals;
Processing a second descriptor describing information of a packet carrying stream information according to a timing at which the event signal is generated;
A stream packet transmission control method comprising: a step of processing a first descriptor describing information of a packet carrying information other than stream information as needed.

The seventh invention relates to
A program for causing a computer to function as the descriptor processing means for processing the first descriptor and the second descriptor in any of the first to fifth stream packet transmitting apparatuses of the present invention.

The eighth invention relates to
A recording medium carrying the program of the seventh aspect of the present invention, which can be used by a computer.

  According to the present invention, it is possible to provide a stream packet transmission apparatus, a stream packet transmission control method, and the like that can achieve both the distribution of packets of stream information and the high-speed processing of packets other than stream information.

  Hereinafter, a stream packet transmitting apparatus according to an embodiment of the present invention will be described with reference to the drawings.

(Embodiment 1)
FIG. 1 is a block diagram of a stream packet transmitting apparatus according to the first embodiment of the present invention. The configuration of the stream packet transmitting apparatus according to the first embodiment will be described together with the operation thereof using FIG.

  The CPU 101 writes data to be transmitted and a descriptor for the data in the main memory 103 through the bus 102.

  However, the data other than the stream information and the data of the stream information are separated, and as shown in FIG. 1, the data 1 consisting only of the data other than the stream information and the descriptor 1 including the start address and length information of the data 1 , And the descriptor 2 including the data 2 including only the stream information and the start address and length information of the data 2 are written in the main memory 103.

  In FIG. 1, both data 1 and data 2 are composed of four data, but each of these data has a size that can be transmitted in one packet transmitted to the network. That is, one data corresponds to one transmission packet. Further, the data 1 and the data 2 are composed of four data, and are examples, and any of the data 1 and the data 2 may be composed of one or more pieces of data.

  The first descriptor processor 104 performs descriptor processing on data other than stream information. That is, when the first descriptor processor 104 receives an operation start instruction from the CPU 101, it immediately reads the descriptor 1 on the main memory 103, and sends the data 1 start address and data 1 length information to the DMA controller 105. give.

  The second descriptor processor 106 processes the descriptor for the stream information data. The second descriptor processor 106 reads the descriptor 2 on the main memory 103 and gives the DMA controller 105 information on the start address of the data 2 and the length of the data 2.

  However, the second descriptor processor 106 does not immediately start the processing of the descriptor 2 even if an instruction to start the operation is received from the CPU 101, and waits for the arrival of an event signal from the timer 107 that occurs every predetermined period. Then, the processing of descriptor 2 is started. Further, when the operation of the second descriptor processor 106 is started, the processing status of the DMA controller 105 is inquired. When the DMA controller 105 is processing the information given from the first descriptor processor 104, the processing ends. Wait for.

  Then, after the processing of the DMA controller 105 with respect to the information given from the first descriptor processor 104 is finished, the second descriptor processing that has been kept waiting is independent of the timing of the event signal from the timer 107. The processing of the device 106 is started.

  A configuration in which the first descriptor processor 104 and the second descriptor processor 106 are combined is an example of the descriptor processor of the present invention. Descriptor 1 and descriptor 2 are examples of the first descriptor and the second descriptor of the present invention, respectively. The timer 107 is an example of timer means of the present invention.

  The DMA controller 105 reads data 1 or data 2 from the main memory 103 via the bus 102 based on the information of the descriptor 1 or 2 given from the first descriptor processor 104 and the second descriptor processor 106, Transfer to the transmission queue 108.

  The data link controller 109 checks the state of the network, and when transmission to the network becomes possible, reads the data from the transmission queue 108 and transmits the data to the network.

  The stream number register 110 holds the number of descriptors to be processed by the second descriptor processor 106 for each event signal generated by the timer 107. When receiving the event signal, the second descriptor processor 106 refers to the stream number register 110 and determines the number of descriptors to be processed at one time. The setting of the stream number register 110 is performed by the CPU 101.

  The period register 111 holds information on the generation period of the event signal generated by the timer 107. The timer 107 reads the value of the period register 111 at the start of operation, and generates an event signal after a time corresponding to the value. At the same time, the value of the period register 111 is read again. Thereby, the period of the event signal generated by the timer 107 corresponds to the set value of the period register 111. The setting of the period register 111 is performed by the CPU 101. The period register 111 is an example of the timer setting unit of the present invention.

  The interrupt unit register 112 holds information on how many interrupt signals are generated by the number of descriptors processed by the second descriptor processor 106. When the second descriptor processor 106 finishes processing one descriptor, the processing number counter 113 counts it. Here, the information about how many interrupt signals are generated and held in the interrupt unit register 112 is an example of a predetermined number set in advance of the present invention.

  The interrupt generator 114 compares the value held in the interrupt unit register 112 with the count value of the processing number counter 113, and generates an interrupt signal to the CPU 101 if they match. The interrupt generator 114 is an example of the interrupt generation means of the present invention.

  At the same time as generating an interrupt signal, the count value of the processing number counter 113 is set to zero. As a result, the interrupt signal generated by the interrupt generator 114 is generated each time the number of descriptors processed by the second descriptor processor 106 reaches the value set in the interrupt unit register 112. The interrupt unit register 112 is set by the CPU 101.

  FIG. 2 is a time chart showing the state of a transmission packet and an interrupt signal obtained by the stream packet transmission device according to the first embodiment.

  First, FIG. 2A shows the state of a packet when stream information is transmitted by the first descriptor processor 104 as in the conventional example shown in FIG. There are timings when the packets exist in a biased manner and timings when the packets do not exist, and the packet is likely to interfere with other packets.

  FIG. 2 (b) shows the state of a packet when the second descriptor processor 106 is used and 1 is set in the stream number register and the period T is set in the period register. Packet intervals are widened and packet positions are distributed. The period T set in the period register is T = L / B, where B is the amount of data per unit time of stream information, that is, B is the amount of data of stream information carried by one packet. Can be calculated. This calculation can be performed by the CPU 101. The period T is an example of the packet transmission interval according to the present invention.

  FIG. 2C shows an interrupt signal when 3 is set as a value in the interrupt unit register 112. When transmitting the stream information to the network, an interrupt signal is continuously generated each time the second descriptor processor 106 finishes processing the three descriptors.

  In the conventional example, an interrupt signal is generated for each descriptor processing, that is, for each packet transmission. FIG. 4D shows the generation timing of the interrupt signal in the conventional example, and comparing this with FIG. 2C, it can be seen that the generation frequency of the interrupt signal is relaxed to 1/3.

  FIG. 2D shows a state of a transmission packet when a packet other than the stream information is transmitted in a state where each register is set as described above and the stream information is transmitted at intervals.

  As described above, the packets other than the stream are written on the main memory 103 as the data 1, and the descriptor is the descriptor 1 independent of the descriptor 2 for the data 2 which is the data of the stream information.

  Further, the descriptor 1 is processed by the first descriptor processor 104 having a higher priority than the second descriptor processor 106 that processes the descriptor 2. For this reason, the packet 202 carrying stream information that should be processed at the timing of t1 is delayed, and the packet 201 carrying data other than the stream information is transmitted first.

  Thus, packets carrying data other than stream information are preferentially transmitted regardless of the presence or absence of packets carrying stream information. For example, in response to an inquiry from another device, the response speed is not reduced. Absent.

  Further, it can be seen that the packet 203 following the packet 202 whose transmission has been delayed is transmitted at the original timing as compared with FIG. 4C of the conventional example. This is because the transmission timing is determined by the event signal generated by the timer 107, unlike the conventional example in which the packet transmission timing is determined by a relative time difference from the packet transmitted immediately before.

  FIG. 2E shows the state of a packet when a plurality of pieces of stream information are transmitted. In this example, two pieces of stream information are transmitted. If the bit rates of the individual streams are the same, the value set in the period register 111 may be a value calculated by the above-described calculation formula, T = L / B, and need not be changed. Instead, if the number of streams is 2, 2 is set as the value in the stream number register. Here, a time zone in which two stream information packets are transmitted at the same timing is an example of the same time zone of the present invention.

  For data 2 and descriptor 2, it is necessary to prepare for the stream. However, when the same data is sent to different destinations, the data 2 can be shared.

  With the above setting, the second descriptor processor 106 processes two descriptors every time an event signal arrives from the timer 107, so that a stream packet is transmitted at a transmission interval as shown in FIG. become.

  In the first embodiment, by setting 3 in the interrupt unit register 112, an interrupt signal is generated for each transmission process of three packets. However, the interrupt signal is not limited to being generated periodically. Instead, the interrupt signal may be generated only once after transmission of all data packets is completed. By setting the number of descriptors 2 written in the main memory 103, that is, the number of data 2 to the value set in the interrupt unit register 112, an interrupt signal can be generated only once at the end of the packet of all data.

  However, when the transmission time of continuous stream information is long, it is preferable to periodically generate an interrupt signal in order to periodically check the transmission state during packet transmission. The value set in the interrupt unit register 112 may be adjusted according to the stream information to be transmitted.

  Further, the number of descriptors processed by the second descriptor processor 106 is added to the processing counter 113, and the interrupt generator 114 compares the value with the value held in the interrupt unit register 112. The interrupt signal is generated in this way, but first, the value held in the interrupt unit register 112 is set in the processing number counter 113, and the processing number is processed each time the second descriptor processor 106 processes the descriptor. The value of the counter 113 may be subtracted and an interrupt signal may be generated when the value of the processing number counter 113 becomes zero. In this case, each time the processing number counter 113 is counted, it is not necessary to compare with the value held in the interrupt unit register 112.

  In the first embodiment, the descriptor processing means includes a first descriptor processor 104 that processes descriptor 1 of information other than stream information, and a second descriptor processor 106 that processes descriptor 2 of stream information. Although it is configured with two descriptor processors, it may be configured with one descriptor processor that handles both descriptors of stream information and information other than stream information.

  As described above, in the stream packet transmitting apparatus of the present invention, the stream information descriptor 2 is processed according to the event signal generated by the timer 107. It becomes possible to adjust to a desired interval.

  Even in a state where the packet interval of the stream information is widened, the descriptor 1 is preferentially handled for packets other than the stream information, so that a response process to an inquiry can be performed without reducing the processing speed.

  Even when handling multiple streams, if the bit rate of a single stream is the same, the period of the event signal to be generated by the timer 107 is the same, and the setting contents are changed each time the number of streams increases or decreases. The procedure to do can be omitted.

  Also, compared to a conventional packet transmission device, the frequency of generation of interrupt signals can be reduced, and the processing load on the CPU 101 that receives and processes interrupt signals can be reduced.

  The program of the present invention is a program for causing a computer to execute the functions of the timer means, descriptor processing means, timer setting means, and interrupt generating means of the above-described stream packet transmitting apparatus of the present invention, and cooperates with the computer. It is a program that operates as

  The recording medium of the present invention carries a program for causing a computer to execute all or some of the functions of the timer means, descriptor processing means, timer setting means, and interrupt generating means of the above-described stream packet transmitting apparatus of the present invention. The recording medium can be read by a computer and the read program is used in cooperation with the computer.

  Further, one usage form of the program of the present invention may be an aspect in which the program is recorded on a computer-readable recording medium and operates in cooperation with the computer.

  The recording medium includes a ROM and the like, and the transmission medium includes a transmission medium such as the Internet, light, radio waves, sound waves, and the like.

  The computer of the present invention described above is not limited to pure hardware such as a CPU, and may include firmware, an OS, and peripheral devices.

  As described above, the configuration of the present invention may be realized by software or hardware.

  The stream packet transmission device and the stream packet transmission control method according to the present invention have the effect of achieving both the dispersion of packets of stream information and the speeding up of the processing of packets other than the stream information, and the time for audio and video images. In particular, the present invention is useful as a stream packet transmission apparatus, a stream packet transmission control method, and the like on the transmission side of an apparatus that transmits stream information having continuity through a network.

1 is a block diagram of a stream packet transmitting apparatus according to a first embodiment of the present invention. In the stream packet transmitting apparatus according to the first embodiment of the present invention, (a) a diagram showing a state of a packet when transmitted by the first descriptor processor, (b) when transmitted by the second descriptor processor The figure which shows the mode of a packet, (c) The figure which shows the generation timing of an interrupt signal, (d) The figure which shows the mode of a packet when packets other than stream information are transmitted during stream information transmission, (e) Multiple The figure which shows the mode of the packet when stream information is transmitted Block diagram of packet transmission apparatus in conventional example In the conventional packet transmission apparatus, (a) a diagram showing the state of the transmission packet, (b) a diagram showing the state of the transmission packet when the processing speed of the data link controller is limited, and (c) during stream information transmission The figure which shows the mode of a packet when packets other than stream information are transmitted, (d) The figure which shows the generation timing of an interrupt signal

Explanation of symbols

101 CPU
102 Bus 103 Main Memory 104 First Descriptor Processor 105 DMA Controller 106 Second Descriptor Processor 107 Timer 108 Transmission Queue 109 Data Link Controller 110 Stream Number Register 111 Period Register 112 Interrupt Unit Register 113 Processing Number Counter 114 Interrupt Generator

Claims (8)

Timer means for generating an event signal at predetermined intervals;
A first descriptor describing information of a packet carrying information other than stream information by processing a second descriptor describing information of a packet carrying continuously generated stream information according to the timing at which the event signal is generated. A stream packet transmitting device comprising descriptor processing means for processing the data as needed.   When the descriptor processing means is processing the first descriptor when starting the processing of the second descriptor in accordance with the timing at which the event signal is generated, the descriptor processing means The stream packet transmitting device according to claim 1, wherein the second descriptor is processed after the processing is completed, regardless of a timing at which the event signal is generated.   Further, a timer that calculates a packet transmission interval based on a data amount per unit time of the stream information and a data amount included in one packet, and sets the packet transmission interval as the predetermined period in the timer means The stream packet transmitter according to claim 1, further comprising a setting unit.   4. The stream packet transmission device according to claim 1, further comprising interrupt generation means for generating an interrupt signal upon completion of processing of a predetermined number of second descriptors set in advance.   When the descriptor processing means transmits a plurality of the stream information having the same data amount per unit time in the same time zone, the descriptor processing means takes the same time zone for each event signal from the timer means. 5. The stream packet transmission device according to claim 1, wherein the second descriptor is processed in the number of the plurality of pieces of stream information to be transmitted. Generating an event signal at predetermined intervals;
Processing a second descriptor describing information of a packet carrying stream information according to a timing at which the event signal is generated;
A stream packet transmission control method comprising: a step of processing a first descriptor describing information of a packet carrying information other than stream information as needed.   6. A program for causing a computer to function as the descriptor processing means for processing the first descriptor and the second descriptor of the stream packet transmitting device according to claim 1. A recording medium carrying the program according to claim 7 and usable by a computer.

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