JP2005174154A - Method, device and program for designing circuit having electric wiring and optical connection - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a design method and device capable of performing design of a further optimum photoelectric integrated circuit in a relatively short time by using the performance of hardware. <P>SOLUTION: The method for designing a circuit having electric wiring and an optical connection comprises a first step for generating a circuit connection list (net list); a second step 12 for generating a connection list (electric net) 13 shouldered by an electronic circuit and a connection list (optical net) 14 shouldered by an optical connection; a third step 18 for performing arrangement of parts and further a wiring design based on the electric net 13; and a fourth step 17 for performing a design of optical connection based on the optical net 14. A fifth step 16 for performing arrangement of an optical port that is a part having photoelectric converting function may be executed after the second step 12 and before the third step 18 and the fourth step 17. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

The present invention relates to a design method, a design apparatus, a design program, and the like for a circuit (also referred to as a photoelectric fusion circuit) in which an electronic circuit connected by electrical wiring and an optical circuit by optical connection are mixed.

Recently, information processing devices such as personal computers, mobile phones, and personal information terminals (PDAs) have been demanded to be faster in processing in addition to being smaller and lighter, but as processing speed increases, Problems such as wiring delay and EMI (electromagnetic radiation interference noise) occur in the circuits used there. As a technique for avoiding these wiring delays and EMI, there is a method using an optical circuit using optical connection (see Patent Document 1).

On the other hand, in the control devices such as the information processing device and the robot described above, it is desired to control by switching a plurality of control algorithms in real time. From such a viewpoint, a circuit that can be reconfigured, particularly a circuit that can be reconfigured at high speed in real time is desired. Examples of reconfigurable circuits include Field Programmable Gate Array (FPGA) and Complex Programmable Logic (CPLD)
device) and the like (see Patent Document 2), further improvement is desired in terms of high speed and circuit scale.

An example of a design flow generally used for designing these information processing devices (semiconductor systems) is shown in FIG. As shown here, in general, after designing a system based on required specifications, through logic design, circuit connection list (net list) generation, layout design (place and route: place and place:
& route), verify. For example, there is a design method using this technique for a system having two chips (Patent Document 3). In such a design method, when a failure occurs in verification, redesign is performed retroactively to placement and routing and further to system design.
JP-A-6-308519 JP 2000-311156 JP 2001-298086

Therefore, in order to realize advanced information processing equipment and control equipment, it is necessary for the circuit to have a large scale, high speed, flexibility (reconfigurable), and such requirements. In order to satisfy the above, it is conceivable to use a circuit in which an optical circuit and an electronic circuit by optical connection are mixed, that is, a photoelectric fusion circuit.

Conventionally, in the design of a system in which an optical circuit using an optical fiber, an optical waveguide or the like is mounted together with an electronic circuit, the optical circuit and the electronic circuit are clearly shown in FIG. 16 at the initial stage of the system design shown in FIG. Separate and independent design was done. However, in such a design method, since the optical circuit and the electronic circuit are designed independently, it is difficult to perform a design that fully utilizes the performance of both circuits (hardware). Furthermore, although it was possible to optimally design each of the optical circuit and the electronic circuit, the performance of the total optimization as the photoelectric fusion circuit was insufficient. In addition, the total design as a photoelectric fusion circuit requires advanced knowledge of both circuits, and a great deal of time and cost.

In view of the above problems, the method for designing a circuit (photoelectric fusion circuit) having an electrical wiring and an optical connection according to the present invention is characterized by having at least the following steps for optimization of the design.
A first step of generating a circuit connection list (net list);
A second step of generating, from the circuit connection list, a connection list (electric net) carried by the electronic circuit and a connection list (optical net) carried by the optical connection;
A third step of designing parts placement and wiring based on the electrical net;
A fourth step of designing an optical connection based on the optical net.

Preferably, after the second step, before the third step and the fourth step, a fifth step of arranging an optical port which is a component having a photoelectric conversion function may be executed. In this way, by optimizing the layout design especially for the optical port that is the interface between the optical circuit and the electronic circuit, in addition to the optimal design of the optical circuit and the electronic circuit, the optoelectronic integrated circuit as a whole is optimized. Is further planned.

You can also do the following:
In the second step, the generation of the electric net and the optical net is made so that the number of electric nets is reduced, or in the fifth step, the arrangement of the optical ports is made so that the total electric wiring length is shortened. Can be done. Further, the placement and routing design in the third step and the optical connection design in the fourth step are verified, and it is determined whether to return to any one of the second to fifth steps or to finish the design. It is also possible to have a sixth step.

The photoelectric fusion circuit has a package structure having a plurality of semiconductor chips, an electric wiring layer, and an optical connection layer, and at least a part of the connection between the semiconductor chips is optically connected through the optical connection layer. In this case, the optical connection layer has a two-dimensional optical waveguide and an optical port for inputting / outputting an optical signal between the two-dimensional optical waveguide, and mutual optical connection is performed across any combination of optical ports. Can be as possible. Furthermore, the semiconductor chip has a reconfigurable circuit, the internal configuration of the semiconductor chip can be changed, and further, the optical connection between the semiconductor chips is changed via the optical connection layer. Can also be possible.

In view of the above problems, the optoelectronic circuit designing device of the present invention has at least the following means.
A first means for generating an electronic circuit connection list and an optical connection list from the circuit connection list;
A second means for storing a circuit connection list, an electronic circuit connection list and an optical connection list;
A third means for designing the layout of the electronic circuit based on the electronic circuit connection list;
Fourth means for designing an optical connection based on the optical connection list.
The fifth means for arranging the optical port, which is a component having a photoelectric conversion function, or the placement and wiring design of the third means and the verification of the optical connection design of the fourth means, A sixth means for determining whether or not to end the design and a control means for controlling the execution order of the first to sixth means may be provided. With such a design apparatus, the above design method is reliably and suitably implemented.

In view of the above-described problems, the optoelectronic circuit design program according to the present invention causes a computer to execute at least the following steps.
A first step of generating an electronic circuit connection list and an optical connection list from the circuit connection list;
A second step of designing the layout of the electronic circuit based on the electronic circuit connection list;
A third step of designing an optical connection based on the optical connection list.
After the first step, before the second step and the third step, there may be a fourth step for causing the computer to execute the arrangement of the optical port, which is a component having a photoelectric conversion function. It is also possible to have a branching step that causes the computer to execute the selection of the next step based on the result of the verification. By mounting such a design program on a computer together with data such as a netlist and an evaluation guideline, the above design method is reliably and suitably implemented.

Further, in view of the above problems, the photoelectric fusion circuit of the present invention has a plurality of electronic circuits, an electrical wiring portion, and an optical connection portion, and is configured to be designed using the above design method, or It is characterized by being designed using the above design method. Such a photoelectric fusion circuit enables the design method of the present invention to be executed.

Further, in view of the above problems, a photoelectric fusion circuit reconfiguration device according to the present invention includes the above-described photoelectric fusion circuit design device and input / output means. In the design device based on information from the input / output means, It is characterized in that the design is made and the result of the design can be mounted on a reconfigurable optoelectronic circuit. Here, the processing data input from the input / output means is processed by a reconfigurable optoelectronic circuit mounted with the design result, and the processing data is output from the input / output means. Can be done. Such a reconstruction device is an application example of the design device of the present invention, and realizes a photoelectric fusion reconstruction system such as a photoelectric fusion system that can be reconfigured in real time.

Further, in view of the above problems, the photoelectric fusion circuit reconfiguration method of the present invention uses a reconfigurable photoelectric fusion circuit and the above-described photoelectric fusion circuit design apparatus, and designs in the design apparatus based on input information. The result of the design is mounted on the reconfigurable optoelectronic circuit. This reconfiguration method is a usage example of the design apparatus and photoelectric fusion circuit of the present invention, and is a reconfiguration method corresponding to the photoelectric fusion reconstruction system.

Further, in view of the above problems, the photoelectric evaluation circuit design evaluation apparatus of the present invention is implemented by mounting the above-described photoelectric fusion circuit design apparatus and the design result of the design apparatus on a reconfigurable photoelectric fusion circuit. And an evaluation means for evaluating the result of the design. Such a design evaluation apparatus is also an application example of the above-described design apparatus of the present invention, and designs a photoelectric fusion circuit using a reconfigurable photoelectric fusion circuit as an emulator.

In view of the above problems, the photoelectric evaluation circuit design evaluation method of the present invention uses a reconfigurable photoelectric fusion circuit and the above-described photoelectric fusion circuit design apparatus, and redesigns the design apparatus. It is mounted on a configurable optoelectronic circuit, operated, and the result of the design is evaluated. This design evaluation method is also a usage example of the design apparatus and the photoelectric fusion circuit of the present invention, and is a design evaluation method corresponding to the design evaluation apparatus.

In this way, by using the design method and design apparatus of the present invention, it is possible to design a more optimal optoelectronic circuit with high reliability in a relatively short time by utilizing the performance of hardware. Here, since a design method in which electronic circuit design and optical circuit design are integrated is used, the electronic circuit and the optical circuit are designed in a coordinated manner, and a highly optimized optoelectronic circuit design as a whole can be realized. Thereby, the cost performance of the final photoelectric fusion circuit can be made excellent. Further, the design method of the present invention can be applied to automatic design of a reconfigurable photoelectric fusion circuit.

In particular, in the second step, the generation of the electric net and the optical net is performed so that the number of electric nets is minimized, or in the third step, the total length of the electric wiring is shortened so that the total electric wiring length is shortened. By performing the arrangement, it is possible to realize a photoelectric fusion circuit in which an optical circuit and an electronic circuit are designed in a highly cooperative manner.

FIG. 1 shows an outline of the design flow of the photoelectric fusion circuit of the present invention. After a schematic system design 21 based on the required specification 20, a circuit connection list (net list) 10 is generated through a logic design 22 and a circuit design, and based on this, a photoelectric fusion characteristic of the present invention is created. Perform design 11.

Hereinafter, each process will be described.
First, in the system design 21, a schematic system configuration is determined in view of the required specification 20. The required specification 20 includes functions to be realized, that is, functional specifications and design constraints. The functional specification is a function to be satisfied by the circuit, and is set variously depending on the application, such as an arbitrary control algorithm, image processing, and audio processing. On the other hand, design constraints include performance, power consumption, cost, design period, and the like. Based on these considerations, the system design 21 determines the division of hardware and software and the outline of the hardware configuration. Examples of the hardware configuration include, for example, the number and type of semiconductor chips, the number of layers of the electrical wiring substrate, the area, the quantity, and the configuration of the optical connection module described later. However, some of these hardware configurations may be restricted as design constraints.

As described above, in the past, the optical circuit and the electronic circuit were separated at the system design stage, and the independent design was performed thereafter, but in the system design 21 of the present invention, the electronic circuit and Does not split the optical connection.

Next, the logic design 22 is performed to obtain the netlist 10. The netlist is data describing circuit connection information. In the present invention, the means for obtaining the netlist 10 is not particularly limited, and any logic synthesis tool or other means can be used. For example, a hardware description language (hardware
It is described in RTL (register transfer level) using description language), and logic synthesis is performed using a logic synthesis tool to obtain a gate level netlist. At this stage, logic verification simulation can be performed to increase the reliability of the design.

Alternatively, a netlist may be created by performing behavioral synthesis from a description in C language. In addition, any IP (intellectual) such as processor, memory, interface, data compression, image processing, etc.
property) macros can also be used for logical design. As the netlist, any connection information such as a transistor level, a gate level, a cell level, a functional block (cell set) level, an IP macro level, or the like can be applied. Furthermore, in the case of a design having an analog circuit, the circuit design of the analog part is finished at this stage and used as a macro, so that the net list creation process can be advanced.

  Subsequently, photoelectric fusion design 11 is performed based on the netlist 10, and a design result (output information) 24 is obtained. Based on the design result 24, mask design is performed, and an optical module including a semiconductor chip, a printed board, an optical transmission medium, an optical port, and the like is manufactured. When a reconfigurable device such as an FPGA is used for the semiconductor chip, the internal configuration of the chip is changed, that is, reconfigured (configured) based on the output information. Furthermore, when the optical connection between chips can be reconfigured, the connection between chips can be reconfigured based on this output.

  Compared to the conventional design method, that is, the method of FIG. 16 in which the electronic circuit and the optical circuit are separated in the initial system design, in the design method and the design apparatus of the present invention, after the netlist is generated (that is, after the logic design), The optoelectronic circuit is designed (the second to fifth steps described above). In particular, the optical connection and electrical wiring assignment performed in the second step are performed after the step of generating the circuit connection list (net list), thereby providing the following effects.

First, when a failure is found in the design result in the verification process 19, it is necessary to make a design change retroactively to the most upstream system design in the conventional method (even if it is not actually necessary, retroactively go back to the system design) Need to consider the possibility of redesign of On the other hand, in the method of the present invention, it is only necessary to perform redesign only in the steps after the netlist generation. This reduces the redesign load and leads to shortened development time.

Further, since the generation of the netlist 10 does not depend on the design constraints related to the optical circuit using the optical connection, it is easy to reuse the netlist that is an intellectual asset. In other words, a net list created in order to realize a system with only electronic circuits can be used as it is. Furthermore, it is not necessary to make major changes to the logical design when changing the hardware specifications including the optical module. For example, when the specifications of an optical module are improved, optimization and performance improvement as a photoelectric fusion circuit can be achieved without greatly changing the logic design.

Next, the method of the photoelectric fusion design 11 of the present invention will be described with reference to FIG. In the optoelectronic design 11, first, from the netlist 10, a connection list (electrical net 13) for an electronic circuit and a connection list (optical net 14) for an optical connection are generated. In step 12 of generating the electric net and the optical net, the electric net 13 and the optical net 14 are generated from the net list based on the hardware specifications (constraints) of the optical module. For example, when the number of optical ports that can be mounted in the optical module is determined in advance, the number of nets that can be handled by the optical net is thereby limited. Based on this, one to be assigned to the optical net 14 is selected from the net list 10. At this time, it is preferable to apply a design that maximizes the performance of the optical module.

Further, in this step 12, a plurality of net lists can be assigned to one optical connection (optical net). For example, a plurality of parallel connections can be assigned to a one-to-one serial optical connection. At this time, since the optical connection is capable of high-speed signal transmission, information corresponding to a plurality of wirings can be transmitted in a time division manner. In addition, when an optical free circuit using a planar or two-dimensional (2D) optical waveguide, which will be described later, is applied to the optical module, it is considered that multiple fan-out signals are assigned to the broadcast optical connection. It is done. Functionally, an optical free circuit is a circuit that can be optically connected to each other across any combination of optical ports.

In this way, since a plurality of net lists can be assigned to a smaller number of optical nets, the number of nets that can be handled by the optical net is not uniquely determined. In other words, the number of electrical nets can vary depending on the configuration of the optical module and the way of allocation to the optical net. In particular, in a system to which an optical free circuit is applied, the diversity of optical connections is high, and allocation to various optical networks can be considered. For example, considering the case where the number of optical ports is determined in advance, the number of nets that can be handled by only 1: 1 optical connection is limited to half the number of ports. The net can be treated as an optical net.

  When the optical free circuit is applied, it is preferable that this step 12 is performed so that the number of the electric nets 13 is as small as possible in order to make use of the characteristics of the optical free circuit. As an actual design example, a plurality of pairs of optical nets and electrical nets are generated, the number of electrical nets is calculated for each, and the one that minimizes this is selected.

More specifically, a high Fan-out, high Fan-in part and a parallel connection part in the net list are preferentially assigned to the optical network 14 as an example. FIG. 3 is a diagram showing that the number of electric nets is reduced by performing broadcast optical connection to the Fan-out portion.
(a) illustrates the connection in the net list, and (b) illustrates the connection in the optical net. In the net list, it can be seen that four nets (four nets in the electric net) can be realized by one optical net. By actively assigning such parts to the optical net 14, the number of electrical nets 13 can be reduced.

High fan-out electrical connections increase the driver's load and disrupt the electrical signal waveform. Making such a connection as an optical connection is a preferable choice from the viewpoint of EMI of electric wiring, in addition to reducing the number of electric nets.

In addition, in order to take advantage of the characteristics of the optical connection capable of high-speed data transmission, it is also a preferable example that the parallel wiring is positively assigned to the optical net and handled as a serial optical connection. Furthermore, when a net for transmitting a high-speed signal is known in advance, it can be assigned to an optical net. In particular, since high-speed parallel electrical wiring is likely to cause crosstalk, it can be said that realizing this by optical connection is a preferable choice from the viewpoint of EMI. Based on these considerations, the example of assigning the fan-out part of the parallel connection as shown in Fig. 4 (a) to the optical net with the optical port 102 as shown in (b) is an example that makes the most of the characteristics of the optical free circuit. One.

Generating the electric net 13 and the optical net 14 so that the number of the electric nets 13 is reduced as much as possible by the above-described method leads to the following effects.

First, wiring (net) that tends to be a bottleneck in an electronic circuit and wiring that greatly restricts other electrical wiring can be preferentially assigned to an optical net. As a result, the load on the subsequent electronic circuit layout design 18 can be reduced. Furthermore, it is possible to output a design result 24 that fully utilizes the hardware configuration of the optical module, particularly the optical free circuit. By these, the design of the final optoelectronic circuit and the final form of the hardware can be improved.

Here, as a preferred example, the method of generating the electric net and the optical net so as to reduce the number of electric nets as much as possible has been described in detail. However, Step 12 may be performed based on any other guideline. For example, to reduce the number of optical ports 102, to reduce the total electrical wiring length, to reduce power consumption, to reduce circuit area, etc. Is mentioned. It can be arbitrarily selected based on the functional specifications that are ultimately aimed at.

Further, after the generation of the electric net 13 and the optical net 14, if necessary, a new electronic circuit (electric net) such as a register, flip-flop, serializer, or deserializer may be added around the optical circuit. At this time, these additional contents are added to the electric net. For example, when the parallel electrical wiring portion is assigned to the optical connection, a serializer may be added to the transmission-side optical port 102 and a deserializer may be added to the reception-side optical port 102. The addition of the electric net is in a direction contrary to the guideline that the number of electric nets is increased and the design is preferably performed so that the number of electric nets is reduced. However, the number of nets increasing here is locally generated around the optical port, and is unlikely to be a large design bottleneck. Therefore, the increment here is not necessarily included in the determination of the number of electric nets.

Thereafter, verification of the generation of the electric net and the optical net may be performed. For example, it is possible to verify whether the contents of the net list before the division and the combination of the electric net and the optical net logically match. Furthermore, logic verification may be performed again on the optical network and the added electronic circuit portion.

Next, a photoelectric fusion layout design 15 is performed based on the electric net 13 and the optical net 14. In this process, the arrangement of various parts, connection of electrical wiring, optical connection, and the like are designed. Here, the component refers to a cell in a standard cell LSI, a functional block having one function in a set of cells, a block corresponding to an IP macro, and the like. In a system to which an FPGA is applied, a logic cell, a configurable block (a collection of logic cells), a block corresponding to an IP macro, and the like correspond to this. Furthermore, in the case of a system in which a plurality of chips are mounted, one chip or device is also included in the component. This includes an optical port described later (a port that performs at least one of light output and input).

That is, in the photoelectric fusion circuit mounting a plurality of chips, in this step, the chip arrangement, the optical port arrangement described later, the wiring between the chips, the optical connection between the optical ports, the cell arrangement in the chip, the chip internal Design of electrical wiring and so on.

In the photoelectric fusion layout design 15 of the present invention, it is preferable to design so that the total electrical wiring length is shortened. The short total electrical wiring length indicates that the optical module, particularly the optical free circuit, functions effectively. Various methods are conceivable as a method for shortening the total electrical wiring length, but it is preferable to preferentially design the arrangement with respect to the optical port which is an interface between the optical circuit and the electronic circuit. From this point of view, the optical port arrangement 16 is first performed as shown in FIG. Here, the optical port arrangement 16 is designed in consideration of both an optical circuit and an electronic circuit as described below. By arranging both in consideration, it is possible to obtain a totally optimized design as a photoelectric fusion circuit.

First, the positions of the optical ports are preferably arranged as dispersed as possible. This is because there is a high possibility that the electrical wiring is congested in the vicinity of the optical port capable of advanced connection. Such a distributed arrangement enables many electrical nets to be effectively connected to the optical port, so that various designs of electronic circuits are possible (various designs are possible and the design range is expanded). . Furthermore, the optical module contributes to efficient use of the optical transmission medium and reduction of crosstalk. That is, such an arrangement of the optical port that is an interface between the optical circuit and the electronic circuit works effectively for both the electronic circuit and the optical circuit, and improves the performance of the final photoelectric fusion circuit.

In addition, it is preferable to arrange the optical port so that a difficult connection form having a heavy load on the electric wiring can be realized by optical connection. Such an arrangement of the optical ports enables a total optimum design as a photoelectric fusion circuit. For example, in general, it is common to use only the x and y directions as electrical wiring. In such a case, the optical ports are intentionally arranged so that optical connection close to an oblique direction is made. It is preferable.

In terms of the distance between the optical port for transmission and the optical port for reception, from the viewpoint of only the optical module, it is preferable that the distance between the transmission and reception ports is closer because more light can be received. However, from the viewpoint of a connection form that is difficult for the electric wiring, it is preferable to arrange the optical ports at a distance as far as possible in view of the fact that it is difficult for the electric wiring to transmit a high-speed signal over a long distance. Because of such conflicting demands, it is preferable to arrange optical ports for transmission and reception as far as possible within a range that satisfies the transmission of the optical connection. For example, the maximum port-to-port distance is simply estimated from the required data transmission rate and data error rate, and the ports are arranged at far positions within the distance range (a pair of far ports is selected).

Further, when performing broadcast optical connection in an optical free circuit, considering only as an optical module, it is preferable to arrange an optical port so that the light emission angle becomes small from the viewpoint of effective use of light. On the other hand, from the viewpoint of a connection form that is difficult for electric wiring, it is preferable to arrange the optical ports so as to broadcast as wide as possible. This is because the distribution of the broadcast wiring at a wide angle by electricity imposes great restrictions on other wiring layouts. Based on such conflicting requirements, in the present embodiment, it is preferable to arrange the optical ports so that the wide-angle broadcast is performed as long as the transmission of the optical connection is satisfied. In addition, when emphasizing circuit area and performance, optical ports should be arranged using wide-angle broadcast as a priority guideline and narrow-angle broadcast as a priority guideline when power consumption is important. Can be considered.

In this way, by arranging the optical ports so as to realize optical connections that are difficult to connect with electrical wiring, the optimal design of the entire optoelectronic circuit is realized, not the optimal design of the optical module alone. . Further, when using hardware in which the position of the optical port is determined in advance, the optical port arrangement 16 is a process of assigning which optical port to each optical net. Allocation can be performed in the same way as described above.

Here, as an example of a preferable photoelectric fusion layout, the method of preferentially arranging the optical ports so that the total electrical wiring length is shortened has been described in detail, but even if this step 15 is performed based on other arbitrary guidelines. Good. For example, the power consumption can be reduced or the circuit area can be reduced. It can be arbitrarily selected based on the functional specifications that are ultimately aimed at.

Next, an electronic circuit layout design 18 based on the electric net 13 and an optical connection design 17 based on the optical net 14 are performed. If the arrangement 16 of the optical ports is completed, the order of the electronic circuit layout design 18 and the optical connection design 17 does not matter. They may be performed in order (whichever is first) or may be performed in parallel at the same time. However, both are performed independently.

As the electronic circuit layout design 18, layout of parts other than the optical port, electrical wiring, and electronic circuit analysis are performed. However, since the arrangement of the optical ports has already been determined in the previous process, this is a placement and routing as a constraint. A general technique can be applied as the placement and wiring of the electronic circuit. For example, the min-cut method (min-cut method)
placement) or the like. Wiring includes line search router, maze-running router, channel wiring method (channel
router) or the like. The wiring can be divided into a schematic wiring for assigning each net to a channel set in the wiring area and a detailed wiring for determining a wiring route in each channel. As an electronic circuit analysis, a delay value of a signal in each net is calculated from the wiring resistance and wiring capacitance of the wiring itself, and timing analysis is performed based on the delay value. In addition, EMI analysis such as crosstalk and waveform distortion may be performed.

Further, the total electrical wiring length is calculated from the result of the electronic circuit layout design. It is possible to design and calculate various optical port arrangements and select an optical port arrangement with a short total electrical wiring length.

In the optical connection design 17, an optical transmission medium design, an optical port design, an optical connection analysis, and the like are performed. As the design of the optical transmission medium, the configuration (shape, thickness, etc.) of the 2D optical waveguide is designed. Further, when the optical transmission medium 101 having a configuration in which the line waveguide 108 is embedded in the 2D optical waveguide as shown in FIG. 13 is used, the arrangement and configuration of the line waveguide are designed. As the design of the optical port, the configuration of the transmission optical port and the reception optical port is determined and the type is selected for each port. Further, in the optical port, the light transmission method, the light emission angle, the light transmission direction, the transmission speed, and the like are set. As the analysis of the optical connection, an analysis of the light amount used for the optical connection, a transmission rate analysis based on the light amount analysis, a delay analysis, and the like are performed.

Next, as verification 19, it is verified whether the design result satisfies the required specifications (function, circuit speed, circuit area, power consumption, etc.). Verification can be performed by performing various simulations. In particular, in the circuit timing verification, it is preferable to perform analysis in consideration of both the delay analysis of the electric net and the delay analysis of the optical net.

If a defect is found in this verification process, it is possible to return to the previous process and redesign as appropriate. However, it is not necessary to return to the process before the netlist 10. The design result after this verification process becomes the final design result 24.

The design method of the photoelectric fusion circuit of the present embodiment described above has the following merits.
In addition to the optimum design of each of the optical circuit and the electronic circuit, a design in which the device arrangement, the electrical wiring, and the optical connection configuration are optimized as a whole of the photoelectric fusion circuit can be provided in a relatively short time. In particular, when the electrical net 13 and the optical net 14 are generated so that the number of electrical nets is reduced, the load of the electronic circuit layout design 18 is reduced, and the total design of the photoelectric fusion circuit is good. Can be obtained. Further, since the optical port which is an interface between the optical circuit and the electronic circuit is preferentially arranged, a good result can be obtained as a total design of the photoelectric fusion circuit. That is, not only the optimization of the electronic circuit and the optical circuit but also the optimization as a photoelectric fusion circuit can be achieved.

In addition, since the electrical net 13 and the optical net 14 are generated from the netlist 10 based on an appropriate guideline and then the optoelectronic layout design 15 is performed, the design reliability is high and the design reproducibility is high. And easy to reuse design assets. Furthermore, the final design result 24 can be obtained without repeating the number of times of returning to the previous process through the verification process.

Hereinafter, the present invention will be described with reference to specific examples. However, the present invention is not limited to the embodiments shown below, and can be changed in configuration, manufacturing method, sequence, addition of steps, omission, etc., as long as they are included in the above concept.

"Example 1"
In this embodiment, a reconfigurable photoelectric fusion circuit is used as hardware, and the above-described photoelectric fusion layout technique is applied to the automatic design of this circuit. As shown in FIG. 5, a reconfigurable photoelectric fusion circuit includes a reconfigurable electronic circuit (FPGA) 107 and a planar or two-dimensional (2D) optical waveguide (sheet-shaped optical transmission medium) 101 described later. A circuit in which an optical free circuit using the above is mixed is used.

In reconfigurable electronic circuits such as FPGAs, with the increase in scale and high integration, in particular, the influence of electrical wiring delay increases, and the time and cost required for design optimization tend to increase. On the other hand, in a system that requires real-time reconfiguration, circuit design in a shorter time is desired. In addition, there is a method to electrically connect multiple FPGAs to increase the scale, but the electrical wiring between chips is fixed and lacks flexibility, so a reconfigurable circuit spans multiple chips. As a result, the limit was large.

The reconfigurable optoelectronic circuit used in this embodiment solves this problem by interconnecting FPGAs with an optical free circuit. The optical free circuit is essentially capable of complete coupling (coupling characteristics that allow free optical connection between optical ports), and has a very high degree of freedom in connection, such as multicast transmission. Thereby, the FPGAs can be connected by an optical free circuit, and reconfiguration across a plurality of chips can be performed with a high degree of freedom. With such a configuration of the photoelectric fusion circuit, it is a reconfigurable circuit having high speed and flexibility in addition to a large scale. Furthermore, such an optoelectronic circuit can alleviate the RC signal delay and EMI problems of the in-chip wiring by using optical connection, so that a large-scale and high-speed reconfigurable circuit can be realized.

On the other hand, an optoelectronic circuit having an optical free circuit has an advantage that the degree of freedom of optical connection is remarkably high. On the other hand, since the degree of freedom is high, there are many options and it is difficult to perform optimal design. From such a viewpoint, an advanced design technique is desired particularly in a photoelectric fusion circuit to which an optical free circuit is applied. From this point of view, a particularly preferable example is configured by applying the design method of the present invention that can provide a method for realizing an optimal design with high reliability to a reconfigurable optoelectronic circuit described in detail below. .

<Hardware>
First, hardware used in this embodiment, that is, a reconfigurable optoelectronic circuit will be described in detail with reference to FIGS. 5 and 6 are schematic views for explaining the circuit board of this embodiment. FIG. 5 corresponds to a planar layout of the circuit, and FIG. 6 is a sectional view thereof. 5 and 6, reference numeral 100 denotes a substrate, 101 denotes a two-dimensional (2D) optical transmission medium (2D waveguide), 102 denotes an optical port that performs at least one of output and input of light, and 103 propagates through the optical transmission medium 101. Propagating light, 105 is an electrical wiring layer, 106 is an electrical wiring, 107 is a reconfigurable electronic device (logic block), 201 is a logical element, 206 is an intersection, 207 is a connection, 208 is an electrical connection network Matrix wiring. As shown in FIG. 5, a plurality (nine) of 400,000-gate FPGAs are mounted as reconfigurable electronic circuits 107, and they are interconnected by an optical transmission medium 101 forming an optical free circuit and an electrical wiring 106. .

Further, as shown in FIG. 6, an electronic module having an FPGA and an electric wiring layer 105 and an optical module having a 2D waveguide 101 and an optical port 102 are laminated and bonded to form a layer structure. In addition, an electrical wiring layer 105 having electrical wirings 106 for connecting the chips 107 is laminated and mounted in a compact manner. The number of layers of the optical transmission medium 101 can be any number, but in this embodiment, the number of layers is one. Further, the adjacent FPGAs are connected by 32 electrical wirings by the electrical wiring layer 105.

Further, as shown in FIG. 6, the optical transmission medium 101 is sandwiched between the electric wiring layers 105, and an optical port 102 is provided in the vicinity of the interface between the electric wiring layer 105a and the optical transmission medium 101. The size of the substrate 100 is 3 cm □. Further, as shown in FIG. 5, nine FPGAs 107 ([1, 1] to [3, 3]) are arranged, and one optical port 102 is arranged corresponding to each FPGA 107. ing. Thus, the FPGA 107 is connected to the optical port 102 having a function of transmitting or receiving an optical signal to the optical transmission medium 101 (the optical port is not shown in FIG. 5).

As described above, the optical transmission medium 101 has a configuration of a 2D optical waveguide. Here, a 100 μm thick polycarbonate (refractive index: 1.59) coated with fluorinated polyimide (refractive index of about 1.52) as a clad is used. In the optical connection established in this way, an electrical signal output from one FPGA 107 is converted into an optical signal in the optical port 102, and the optical signal propagates through the 2D optical waveguide, which is the optical transmission medium 101, and then another optical signal. It is converted into an electrical signal at the port 102 and input to another FPGA 107.

In this way, the FPGAs are connected by both electrical wiring and an optical free circuit. Which is used for signal transmission can be selected by switching the connection terminal inside the FPGA.

As described above, in addition to changing the internal configuration of the electronic circuit (FPGA) 107, the photoelectric fusion circuit of this embodiment changes the configuration of the entire circuit by freely changing the optical connection between the FPGAs. It is possible. That is, the connection between the FPGAs via the optical free circuit can be reconfigured.

The configuration of the optical free circuit will be further described.
An optical free circuit is a circuit that transmits information using light as a carrier, and is a circuit that can freely change the transmission form of information between optical ports 102 via an optical transmission medium 101. In this embodiment, the optical free circuit includes a two-dimensional waveguide (planar optical waveguide) 101 and an optical port 102.

In an optical free circuit, an optical port can be arranged at an arbitrary position of a two-dimensional waveguide if it is desired to transmit it, and optical data is transmitted two-dimensionally from an optical port arranged at an arbitrary point to an arbitrary optical port. can do. For example, the light 103 can be propagated at an arbitrary radiation angle 104 over the plane of the optical transmission medium 101 as shown in FIG. Each optical port can broadcast an optical signal to all other optical ports. As mentioned earlier, at the optical port 102, the FPGA
The signal from 107 is converted into an optical signal. The optical signal propagates through the optical transmission medium 101, is converted into an electrical signal in another optical port 102, and is input to another FPGA 107.

The optical port 102 has a function of transmitting or receiving an optical signal. That is, it has an optical output unit that converts an electrical signal into an optical signal, an optical input unit that converts an optical signal into an electrical signal, or both. The light emitted from the light emitting element that is the light output unit of the optical port responsible for transmission propagates through the optical transmission medium 101 and is input to the light receiving element that is the light input part of the optical port responsible for reception. By converting the signal into an electrical signal at the optical port responsible for reception, signal transmission from the optical port 102 to the optical port 102 is performed, and an optical circuit is configured.

For the light output unit, for example, a surface emitting laser can be used. Specifically, an electrical signal is converted into an optical signal by applying a logic signal (for example, 3.3 V) of the FPGA 107 input to the optical port 102 to the light emitting element so as to be forward biased. Here, a 0.85 μm band emitting laser (VCSEL) is used as the light emitting element. Standard VCSEL characteristics are 3mW optical output at a drive current of 3.0mA.

Furthermore, as shown in FIG. 11, the optical port 102 is configured to be able to propagate at various in-plane radiation angles and radiation directions. In order to realize this, a quadrangular pyramid-shaped mirror as shown in FIG. 12A can be used as the optical coupler 301 for optically coupling the optical port 102 and the optical transmission medium 101. Here, the light 303 from the light emitting element 306 of the light output unit 305 is irradiated from above the pyramid mirror 301, reflected in the lateral direction, and coupled to the optical transmission medium 101. As shown in FIG. 12 (b), when the light from the light emitting element 306 is irradiated to the light irradiation position 302 on one slope of the pyramid 301, the propagation of the light 304 is realized with an in-plane radiation angle of approximately 90 °. When the four inclined surfaces are irradiated as shown in FIG. 12 (c), the light 304 is propagated at an in-plane radiation angle of 360 °. For 2 and 3 slopes, they are 180 ° and 270 °, respectively. Since the pyramid slope is a diffusing surface, uniform light is propagated over a range of radiation angles.

In the example of FIG. 12, five light emitting elements 306a, 306b, 306c, 306d, and 306x are arranged above the pyramid mirror 301, for example, one for each inclined surface and one for the center. It is arranged to irradiate each slope. With such a configuration, the emission angle can be set by selecting a light emitting element. For example, if the center light emitting element 306x is used, if one of 306a to d is selected in all directions of 360 °, the direction of 90 ° is determined if two are selected, and the direction of 180 ° is selected if two are selected. If you select three, you can propagate in the direction of 270 °, and if you select four, you can propagate in the direction of 360 °. In this manner, by arranging a plurality of light emitting elements in the optical port 102 and selecting the light emitting element to be driven, the radiation angle and the radiation direction can be switched. The light emitting element can be selected in the FPGA 107.

Here, an example of an optical port in which a pyramid mirror is used and a radiation angle and a radiation direction can be selected in units of 90 degrees is shown, but the present invention is not limited to this. Even if an optical port that can broadcast in almost all 360 ° directions, can realize beam-like propagation with a radiation angle as small as possible corresponding to the radiation angle of the light emitting element, and can also propagate in various directions, etc. Good.

The optical signal propagating through the optical transmission medium 101 is taken into the light receiving element of the optical port 102 and converted into an electronic signal. As the light receiving element, a Si-PIN photodiode can be used, which is connected to the electronic circuit 107. The converted electric signal is captured and processed as an input electric signal in an electronic circuit 107 such as an LSI close to the electric signal. At this time, if a preamplifier that amplifies an electric signal is integrated with the light receiving element, it can be restored to a CMOS compatible voltage. Further, by using a conical optical coupling section (see the optical coupler 301 in FIG. 12) as the light receiving section, it is possible to receive light from all 360 ° directions of the 2D optical waveguide 101. Thus, by applying an optical port and a 2D optical waveguide and allowing light to freely propagate in the waveguide, the function of the optical free circuit, that is, an arbitrary optical connection between the optical ports becomes possible.

Here, an example of an optical port that can receive light from all directions of 360 ° of a 2D optical waveguide has been shown. However, a plurality of parts that receive light from a limited direction are provided, and it is the same as the previous outgoing optical port. A signal to be received may be selected by selecting a light receiving unit using a technique.

In the present embodiment, as described above, the transmission angle is selected by changing the radiation angle and propagation direction of the optical signal from the transmission optical port, or the reception direction of the optical signal is changed at the reception optical port. Then, the circuit connection is changed (reconfigured). In addition, the circuit can be reconfigured by selecting data at the reception optical port. For example, the transmission optical port can transmit information to a desired reception optical port by giving information as a packet signal and broadcast-transmitting the information, and selecting the address by the reception optical port.

In this way, the optical free circuit is essentially a circuit that can realize full bidirectional coupling at the optical port. Further, 1: N multicast communication, N: M communication, and the like can be realized. Furthermore, these connections can be freely changed (reconfigured), and one-to-one, 1: N or N: M transmission can be freely switched (reconfigured). In the optical free circuit of this embodiment, the data transfer rate between the optical ports is 1 Gbps at maximum, typically 500 Mbps.

Here, the reason why the 2D waveguide is preferable as the optical waveguide used in the optical free circuit, not the line waveguide or the free space connection will be described. First, an optical circuit using an optical fiber or a line waveguide may be used. However, since the line wiring is fixed, the degree of freedom of wiring is inferior. Realizing reconfiguration of an optical circuit with this configuration involves difficulties such as the need for many optical switches. Furthermore, the linear optical waveguide needs to be aligned with the optical axis in a size of several microns to several tens of microns, which is difficult. In addition, the optical waveguide needs to be finely processed and is difficult to manufacture.

On the other hand, by applying the 2D waveguide, an optical device (light emitting element or light receiving element) can be mounted at a desired arbitrary position, and information can be transmitted between arbitrary positions. Furthermore, optical alignment is facilitated in optical coupling between the optical device and the waveguide layer. Because of such a simple configuration, a circuit board can be easily formed, and the cost can be reduced. Furthermore, as will be described later, in an optical free circuit to which a 2D optical waveguide is applied, an optical circuit can be reconfigured basically only by controlling an optical port that is an optical input / output unit.

On the other hand, since the line waveguide is capable of high-speed signal transmission, it may be embedded in a 2D optical waveguide to carry out a predetermined fixed connection. For example, as shown in FIG. 13, a line waveguide 108 may be prepared for connection between distant chips 107. As an optical transmission medium, a method of propagating light in free space has been proposed. However, this method has a problem that the wiring size is high but the size becomes large. A configuration using an optical free circuit using a 2D optical waveguide can realize a thin and high-density circuit board.

The above-described reconfigurable optoelectronic circuit can reconfigure the optical connection in the optical free circuit in addition to the circuit configuration inside the FPGA. However, the configuration data that is the information responsible for these reconfigurations is described above. This information is output by designing the photoelectric fusion circuit.

The reconfigurable optoelectronic circuit of this embodiment can read configuration data from the outside and reconfigure the entire circuit. By rewriting the configuration data, the design of the circuit inside the FPGA is changed and the electronic circuit (inside the FPGA and the electrical connection between the FPGAs) is reconfigured. In addition, the FPGA via the optical free circuit such as optical port selection The connection is changed (reconfigured). More specifically, the optical circuit is reconfigured by changing the radiation angle and the radiation direction at each optical port based on the configuration information. In the case of using hardware capable of setting an optical connection mode by controlling a movable part such as a mirror in an optical port, the optical connection mode can be changed (that is, reconfigured) by controlling such a movable part.

In the reconfiguration, the entire circuit may be reconfigured or may be partially reconfigured. If similar functions can be satisfied, partial reconfiguration is more preferable because high-speed reconfiguration can be realized.

<Design method>
Next, a method for designing the above-described reconfigurable optoelectronic circuit applied in this embodiment will be described. In this design method, as shown in FIG. 1, a system design 21 and a logic design 22 are performed based on a required specification 20, and a net list 10 at a gate level is output. The application includes contents obtained by adding an image processing function to a video signal decoder. In the logic design 22, as described above, it is described in RTL using a hardware description language, and logic synthesis is performed using a logic synthesis tool to obtain a gate level netlist 10.

Next, based on the netlist 10, a photoelectric fusion design 11 characteristic of the present invention is performed. Here, the design is performed using the optoelectronic circuit design apparatus shown in FIG. This optoelectronic circuit design device has input / output means, storage means 81, design means 82, and control means 83.

The storage means 81 is a part for storing a net list, an electric net, an optical net, various design parameters, design results, intermediate design results, design time, functional specifications as required specifications, design constraints, and the like. The input / output means is a means for allowing the above-described data to be input from the outside and outputting design results, evaluation results, and the like to the outside. The design means 82 includes means for generating an electric net and an optical net from the net list, optical port placement means, electronic circuit layout design means (including placement means and wiring means), optical connection design means, and verification means. The control means 83 controls the entire design means 82. In this embodiment, the design means 82 and the control means 83 are implemented as programs (software) in a general computing device.

FIG. 2 is a diagram showing a flow of optoelectronic design used in this example. First, the electric net 13 and the optical net 14 are generated from the netlist 10 based on the specifications (constraints) of the reconfigurable optoelectronic circuit described above. As described above, as described above, the number of optical ports in the optical module is nine. The position of the optical port is fixed.

In the present embodiment, a part corresponding to fan-out is extracted from the net list, and this is preferentially assigned to the optical net, thereby generating an optical net and an electric net. The fan-out is connected by a broadcast optical connection in an optical free circuit. For example, three netlists
node 1 =>
node 2
node 1 =>
node 3
node 1 =>
node 4
In the optical network as one 1: 3 connection
port1 =>
port2, port3, port4
And assign.

In this way, three electric nets can be reduced by using four optical ports. Since the optical module of the present embodiment has nine ports, another net can be assigned to the optical net.

Next, photoelectric fusion layout design 15 is performed based on the electric net and the optical net. As shown in FIG. 2, first, after the optical port arrangement 16 is performed, the electronic circuit layout design (arrangement wiring) 18 and the optical connection design 17 are performed.

Here, the optical port arrangement 16 is designed in consideration of both the optical circuit and the electronic circuit. Here, the optical ports to be used are dispersed as much as possible, and are arranged so that the total optical connection distance, that is, the distance between the transmission optical port and the reception optical port is as long as possible. For example, the aforementioned optical net (port1
=> port2, port3, port4), for example, as a port corresponding to [1,1] as an optical port for transmission and as an optical port for reception
Ports corresponding to [1,3], [3,1], [3,3] are selected (see FIG. 5).

Following the arrangement 16 of the optical port, an electronic circuit layout design 18 based on the electric net and an optical connection design 17 based on the optical net are performed. In the electronic circuit layout design, a min cut method is used as a method for arrangement, and a channel wiring method is used for wiring. As an electrical analysis, a delay value of a signal in each net is calculated from the wiring resistance and wiring capacitance of the wiring itself, and timing analysis is performed based on the delay value. In addition, power consumption is estimated. Further, the total electrical wiring length is calculated from the result of the electronic circuit layout design.

In the design of the optical connection, it is further determined how the light is transmitted in the optical port for transmission and in what light emission angle the light is transmitted. Here, it is selected so as to be most effective in consideration of the light emission direction, the emission angle, and the position of the optical port for reception at the port [1,1]. That is,
In order to emit light in the lower right direction in FIG. 5 so that signals can be sent to the ports corresponding to [1,3], [3,1], [3,3], the two light emitting units in FIG. Selected and driven. As the analysis of the optical connection, an analysis of the light amount used for the optical connection, a transmission rate analysis based on the light amount analysis, and a delay analysis are performed.

Subsequently, it is verified whether the design result satisfies the required specifications (circuit speed, circuit area, power consumption, etc.). In timing verification, analysis is performed in consideration of both the delay result of the electric net and the optical net. If a defect is found in the verification process, it can be redesigned, but this embodiment is not particularly necessary.

Based on the above-described design result (output information) 24, that is, configuration data, the connection between the FPGA and the FPGA is changed. That is, reconfiguration is performed.

(Reference design 1)
As reference design 1, different methods were used in the steps of generating an electric net and an optical net. Here, as in this embodiment, the same four ports are used, but the optical net uses a 1: 1 connection, and the design is attempted for a case where the number of electric nets is reduced by two. That is, as a netlist
node 11 =>
node 12
node 13 =>
node 14
As it is with a light net
port
11 => port12
port
13 => port14
This is the case when assigned to. In the reference design 1, the other steps used the same method as in this example.

(Reference design 2)
The optical port arrangement method used in the above-described embodiment is not necessarily a preferable arrangement because of the long transmission distance when only the optical module is considered. Here, as reference design 2, an arrangement that emphasizes optimization as a single optical module was performed. In this case, for a similar optical network, the transmission / reception port distance is shortened, the transmission optical port is a port corresponding to [2,2], and the reception optical port is [1,2], [ Ports corresponding to [1,3] and [2,3] are selected. Also in the reference design 2, the other steps used the same method as in this example.

The table below shows the characteristics of the reconfigured circuit based on each design.
Operating speed Power consumption This example 120MHz 0.7W
Reference design 1 30MHz 0.75W
Reference design 2 75M 0.65W
It can be seen that the performance (operation speed) of the circuit designed by the design method of this embodiment is high. Further, the circuit scale (number of gates used in the FPGA) of the circuit designed in this example was the smallest.

In particular, in this embodiment, it can be seen that the circuit performance is improved by designing so that the number of electrical nets is reduced when generating an optical net, as compared to the reference design 1. Further, the time required for the electronic circuit layout design was shorter than that of the reference design 1. That is, in the design of this example, the electric net and the optical net were generated so that the number of electric nets was reduced, and therefore, good results could be obtained as a total design of the photoelectric fusion circuit.

Further, in the present embodiment, it can be seen that the circuit performance is improved by distributing the optical ports in the arrangement of the optical ports as compared with the reference design 2. Furthermore, it can be seen that the optimum design of the entire optoelectronic circuit can be performed even at the expense of the design of the optical module alone. Also, compared with the reference design 2, the time required for the electronic circuit layout design was shorter.

That is, in the design of the present embodiment, since the optical port that is an interface between the optical circuit and the electronic circuit is preferentially arranged, a satisfactory result was obtained as a total design of the photoelectric fusion circuit. In addition, the total electrical wiring length of this example was about 30% shorter than the total electrical wiring length of Reference Design 2. That is, it can be seen that it is effective to arrange the optical ports so as to shorten the total electrical wiring length.

With the design method of this embodiment, not only the optimization of the electronic circuit and the optical circuit, but also the optimization as a photoelectric fusion circuit was achieved. The optoelectronic circuit of this embodiment designed in this way is designed to make the best use of the performance of the hardware and has high cost performance. In addition, the design of this embodiment has features such as high reliability, high reproducibility, and easy reuse of design assets. Furthermore, the photoelectric fusion circuit having the optical free circuit has an advantage that the degree of freedom of optical connection is remarkably high. On the other hand, since the degree of freedom is high, there are many options and the optimum design becomes difficult. By using this, a sufficiently good design could be achieved.

In this embodiment, the number of optical ports is as small as nine, and the optical connection mode and the arrangement of the optical ports are described as simple enough that it is not necessary to perform automatic design or the like for easy understanding. However, when the number of optical ports increases, diversity increases and it becomes difficult to optimally design. Even in such a case, the design method of the present embodiment can provide a highly reliable design in a short time. In particular, it is more preferable to perform automatic design.

In the present embodiment, an FPGA is used as a reconfigurable electronic circuit. However, the present invention is not particularly limited to this. As shown in FIG. 5, the reconfigurable electronic circuit may be a circuit including a logic element 201 whose logic function can be changed and an electric connection network whose interconnection can be changed. An example of the logical element 201 is an LUT (Look Up Table) that has an input / output truth table relating to a logical function to be realized in a RAM format and outputs an output signal for an input combination. Further, AND, NAND, OR, NOR, XOR, flip-flops, latches, registers, inverters, multipliers, and the like, or a circuit combining any of these may be included. Furthermore, a memory may be included. In addition, an arithmetic unit (processor) such as integer arithmetic, floating point arithmetic, and function arithmetic may be included.

The electrical connection network can set the connection between the logic elements. For example, the electrical connection network may be composed of electrical wiring and switches arranged in a matrix that connects the logic elements arranged in an array (see FIG. 5). The switch is arranged at a connection portion between the logic element and the electric wiring, an intersection portion of the matrix wiring, or the like. In this embodiment, the reconfiguration system uses only the FPGA, but may have other chips such as ASIC, CPU, DSP, and memory. In this case, an optical port can be prepared for a chip such as an ASIC.

"Example 2"
This embodiment is an example of designing a circuit having an ASIC (custom chip) as hardware, and also having an FPGA, a memory, and the like. The basic structure of the photoelectric fusion circuit is assumed to be the configuration shown in FIG. The main restriction is the use of custom chips. In addition, as hardware limitations, the maximum number of FPGA chips is 4, the maximum number of electrical wiring layers is 10, the number of optical connection layers is 1, and the maximum number of optical ports is 16.

A difference in design range from the first embodiment will be described.
In the first embodiment, the details of the inside of the FPGA and the optical module are variable, but the arrangement of the chip and the optical port is fixed. In other words, an optimal design was performed for a preset reconfiguration system called a photoelectric fusion circuit having 9 FPGAs and 9 optical ports. In addition, the configuration of the electronic circuit layer including the position of the FPGA and the electrical wiring between the FPGAs, and the configuration of the optical connection layer such as the number and position of the optical ports have been set in advance.

In this embodiment, the layout of ASIC and FPGA is also a design element. In addition, in the present embodiment, the configuration of the optical connection layer such as the position and type of the optical port and the optical transmission medium is also designed within the range of restrictions. The optical connection layer is based on an optical free circuit using a 2D optical waveguide as an optical transmission medium. Further, in the optical connection layer of Example 1, the optical connection mode can be changed (reconfigurable), but in this example, the final optical connection mode is fixed. Further, it is also within the scope of restriction to embed and form the line waveguide 108 in a part of the 2D optical waveguide 101 as shown in FIG. Also, it is within the scope of restriction to connect a plurality of optical ports to one chip. On the other hand, in this embodiment, the internal circuit of the ASIC is fixed.

Also in the present embodiment, the outline of the design flow is in accordance with the first embodiment. Hereinafter, the differences will be mainly described. Also in this embodiment, as shown in FIG. 2, system design 21 and logic design 22 are performed based on the required specification 20. Until the gate level netlist 10 is output, the same technique as in the first embodiment is used. However, since the interior of the ASIC has already been designed, it is treated as a fixed block, and its internal circuit is fixed.

Next, photoelectric fusion design 11 is performed. In this embodiment, the design in each ASIC chip has been completed, so the chip layout, electrical connection between chips, FPGA internal configuration, optical connection layer configuration, optical connection between chips, etc. You will be designing.

First, in step 12 of generating electric nets and optical nets, each net is generated so as to reduce the number of electric nets. Here, first, the number of electrical nets is reduced by preferentially allocating parallel connection parts and secondly, fan-out parts to optical nets. When the parallel electrical wiring portion is assigned to the optical connection, a serializer is added to the transmission side optical port, and a deserializer is added to the reception side optical port. Thereafter, it is verified whether the contents of the net list 10 before the division and the combination of the electric net 13 and the optical net 14 are logically coincident.

Next, optical port arrangement 16 is performed. In the first embodiment, the position of the optical port is fixed in advance, but in this embodiment, the optical port can be designed at an arbitrary position. In this embodiment, in view of the size (3 × 4 cm) of the optical transmission medium, the optical ports are distributed and arranged so that the total optical connection distance is increased. Therefore, in particular, the optical ports are arranged based on the following guidelines. First, for an optical network in which a Fan-out signal is assigned to a broadcast optical connection, an optical port is arranged so that the signal is broadcast as wide as possible.

In addition, for an optical network that performs optical transmission with serial connection as a serial connection, an optical port is used so that transmission is performed in a diagonal direction with respect to the xy electrical wiring so as to be as long as possible. Place. Further, the restriction that the optical port cannot be arranged in the range of the width of 5 mm around the periphery of the optical transmission medium was used. Due to this restriction, the optical port is arranged at the lower part of the chip, and the electrical wiring connecting the chip and the optical port can be shortened.

Subsequently, an electronic circuit layout design 18 and an optical connection design 17 are performed. The electronic circuit layout design and the optical connection design are the same as in the first embodiment. However, with regard to the configuration of the optical port, a library with variations in the configuration shown in FIG. 12, the number of light emitting elements, the structure of the scatterers, etc., is prepared and selected from these. Here, variations of scatterers include cones and hemispherical scatterers that can scatter in the same direction, pyramid and prismatic scatterers that can scatter in a limited direction, and scattering of mirrors and prism structures. There is a body. For example, a hemispherical scatterer can be used at a port that broadcasts in all directions, and a scatterer with a 45-degree mirror configuration can be used to transmit light preferentially in a certain direction.

Next, based on the result of the electronic circuit layout design 18, the optical port arrangement is finely corrected. In this fine correction, the position correction is allowed only within a radius of 5 mm from the previous arrangement position. By this fine modification, the wiring distance between the chip and the optical port can be shortened and the reliability between the optical connections can be increased. In particular, the latter can reduce crosstalk and secure a transmission band.

In this example, in the verification 19, the transmission speed was insufficient in a part of the optical connection. Therefore, the optical connection was redesigned. Specifically, the line waveguide 108 is applied to the net portion. As a result, sufficient optical connections were made and the specifications were satisfied.

In this embodiment, the mask is raised based on the design result 24 obtained by the above design, and the optical connection layer and the electrical wiring layer are created. These are bonded together and a chip is mounted to obtain a configuration similar to FIG. Furthermore, the designed photoelectric fusion circuit is realized by constructing a circuit inside the FPGA using the design result 24.

FIG. 8 is a diagram showing an example of the design result of the present embodiment. A to E are semiconductor chips. In this embodiment, A and D are custom chips, B and C are FPGAs, and E is a memory. (a) is a view from above, and shows the arrangement of the chip 107 together with the main electric wiring 106 of the uppermost layer. FIG. 6B is a diagram in which the optical port 102 and the chip 107 are arranged on the optical connection layer 101 in an overlapping manner. A line waveguide 108 is applied to the connection between A and D, and a broadcast optical connection using a 2D optical waveguide is used to connect E to another chip. In the transmission / reception port connected to the line waveguide 108, a type of optical port having an optical coupler (mirror) having a triangular prism structure is used.

On the other hand, as a transmission port for broadcasting, an optical port having a hemispherical optical coupler is used. The electrical wiring and optical connection described here are only a part of them in order to explain typical connection examples. For example, an optical connection with a limited emission angle 104 as shown in FIG. 11 may be provided.

Also in this embodiment, by designing with priority on the position of the optical port, it is possible to optimize not only the optimum design of the optical circuit and the electronic circuit but also the entire optoelectronic circuit. That is, it is possible to design a photoelectric fusion circuit having good performance as a total photoelectric fusion circuit with high reliability. In particular, by generating the electrical net and the optical net so that the number of electrical nets is reduced, good results can be obtained as a total design of the photoelectric fusion circuit. In addition, in the arrangement of the optical ports, the optimum design of the entire optoelectronic circuit can be performed by arranging the optical ports so that the optical connection is difficult to connect with the electric wiring. The optoelectronic circuit of this embodiment designed in this way is designed to take full advantage of hardware constraints and has high cost performance.

"Example 3"
In Example 3, the type of hardware shown in FIG. 9 was used. In FIG. 9, 100 is a substrate, 101 is an optical transmission medium, 102 is an optical port, 103 is propagating light, 105 is an electric wiring layer, and 107 is a semiconductor chip (the electric wiring layer 105 has electric wiring, Is shown). 107a, 107b, and 107c are FPGAs, and 107d is a custom chip. FIG. 9 (a) is a plan view corresponding to the layout. Figure 9 (b)
FIG. 10 is a sectional view of FIG. 9 (a).

That is, in this embodiment, the optical module having the optical transmission medium 101 and the optical port 102 is arranged in a part of the substrate, and the semiconductor chip 107 is arranged in the other area. Moreover, as a restriction, the optical module is handled as a component, and a semiconductor chip cannot be placed at that position. Since the electric wiring layer is separately provided, it is possible to arrange the electric wiring at an in-plane position of the optical module. Other major hardware restrictions are: 3 FPGA chips, 1 custom chip, 4 electrical wiring layers, 1 cm square optical transmission medium, and optical connection layers Is one layer and the maximum number of optical ports is 10 (see FIG. 9 for arrangement). The optical port 102 is disposed at the end of the optical transmission medium 101.

In the optoelectronic circuit design of this embodiment, the internal configuration of the FPGA, the arrangement of the semiconductor chip and the optical module, the electrical wiring between the semiconductor chips, the optical connection between the semiconductor chips, the configuration of the optical module, and the like are designed.

Hereinafter, the design method of this embodiment will be described with reference to FIG. The processes up to the formation of the netlist 10 are the same as those in the first embodiment. In step 12 of generating the electric net 13 and the optical net 14, each net is generated so as to reduce the number of electric nets. Here, the Fan-out part is assigned as the first priority, and the parallel connection part is preferentially assigned to the optical network as the second priority.

The present embodiment is different from the second embodiment in that the step of optoelectronic layout design 15 has the position of the optical transmission medium as a design item. The optical port arrangement 16 is performed so that the total distance of the optical connection is maximized. Thereby, the positions of the optical ports are distributed and arranged at the end of the optical transmission medium. In the electronic circuit layout design 18, the optical transmission medium is handled as a component having an electrical input terminal to the optical port, and is arranged and wired together with other chips. The optical connection design 17 was in accordance with Example 2.

In the design result output of this embodiment, an optical transmission medium 101 is arranged near the center of the substrate 100 as shown in FIG. Further, the arrangement of the optical port 102 and the optical connection are also shown in FIG.

Also in this embodiment, by designing with priority on the position of the optical port, it was possible to optimize not only the optimum design of the optical circuit and the electronic circuit but also the entire photoelectric fusion circuit. That is, it was possible to design a photoelectric fusion circuit having a good performance in the total photoelectric fusion circuit with high reliability. As described above, the photoelectric fusion circuit of this embodiment is also designed to make the best use of the hardware performance, and has high cost performance.

"Example 4"
Example 4 is an example of a photoelectric fusion system (photoelectric fusion reconstruction system) that can be reconfigured in real time. An example of a reconfigurable photoelectric fusion system of this embodiment is shown in FIG. As shown in FIG. 10 (a), it has a circuit (device) 92 for designing an optoelectronic circuit, a reconfigurable optoelectronic circuit 91, a configuration memory 93, and an I / O (input / output means) 94.

The circuit 92 for designing the optoelectronic circuit has the means shown in FIG. 7 and is as described above. In this embodiment, these means are integrated into one chip and mounted as hardware.

In the reconfigurable optoelectronic system of the present embodiment, the circuit 92 for designing the optoelectronic circuit based on the input data from the I / O 94 forms (or changes) the design data and stores it in the configuration memory 93. Save design data. The reconfigurable optoelectronic circuit 91 sequentially reads design data from the configuration memory 93 and performs reconfiguration (change of internal configuration). The output from the reconfigurable optoelectronic circuit 91 is output to the I / O 94. In this way, the internal configuration of the optoelectronic circuit 91 can be optimized at any time based on the input data from the I / O 94.

In this embodiment, the optical circuit and the electric circuit are fused, and the design and further reconfiguration can be performed in real time by making the best use of the resources of the photoelectric fusion circuit 91 having a high degree of wiring freedom. That is, it can function as a dynamic reconfigurable system in which the internal configuration of the photoelectric fusion circuit 91 can be freely changed in real time.

In addition, the reconfiguration system of the present embodiment is a system that requires sequential hardware reconfiguration in response to continuous changes in the operating environment, and the reconfigurable optoelectronic circuit 91 is optimally designed and reconfigured in a short time. Since it can be configured, it can be suitably applied to a control system such as a robot.

In the present embodiment described above, description has been given along FIG. 10A in which the respective parts are interconnected. However, a configuration in which the respective parts are connected by the bus 95 as shown in FIG. 10B is also possible. is there. Further, the function of the memory 93 may be performed in the reconfigurable photoelectric fusion circuit 91 or the circuit 92 that designs the photoelectric fusion circuit.

"Example 5"
The fifth embodiment is an example in which a reconfigurable photoelectric fusion circuit is used for designing a photoelectric fusion circuit having a fixed circuit. That is, circuit verification and evaluation are performed using the reconfigurable photoelectric fusion circuit used in the first embodiment, and a custom photoelectric fusion circuit is created based on the output result.

The configuration of the design evaluation device used in this example is shown in FIG. A photoelectric fusion circuit design means 82 and a design evaluation means 87 for mounting the design result of the design means 82 on a reconfigurable photoelectric fusion circuit 91 and operating it to evaluate the design result are provided. That is, the design evaluation apparatus of the present embodiment includes design evaluation means 87 in addition to the optoelectronic circuit design apparatus (FIG. 7) used in the first embodiment. Here, as the reconfigurable photoelectric fusion circuit 91, the same hardware as that used in the first embodiment is used.

By using this design evaluation apparatus, a plurality of design results output from the design means 82 are mounted on the reconfigurable optoelectronic circuit 91 and operated to perform performance comparison and function verification. In view of the required specifications, a design result with the most favorable performance is selected. This is called the first design result. Here, the largest result of (operating frequency) / (power consumption) is adopted.

The photoelectric fusion layout design is performed again based on another custom specification using the electronic net and the optical net derived from the first design result. The main restriction is that the electronic net is realized with an electrical wiring layer and an ASIC or cell-based custom IC. The physical specification of the electrical wiring layer is the same as that of the reconfigurable photoelectric fusion circuit 91. The optical connection layer has the same configuration as that of the reconfigurable photoelectric fusion circuit 91, but the position of the optical port is arbitrary.

This method of optoelectronic layout design again conforms to the method used in the second embodiment. However, in this embodiment, the internal design of the ASIC is made in the electronic circuit layout design. In addition, a circuit realized over a plurality of FPGAs can be mounted on one ASIC. The substrate is square, but size is a design item. The substrate size is set to be as small as possible based on the electronic circuit layout design. Based on this, the position of the optical port is reduced while maintaining the positional relationship. The result obtained here will be referred to as a second design result.

Based on the obtained second design result, a new mask is created for the ASIC, the electrical wiring layer, and the optical connection layer to create a custom optoelectronic circuit. Although the reconfigurable photoelectric fusion circuit 91 can change the circuit configuration, the custom photoelectric fusion circuit is a circuit whose configuration is fixed. On the other hand, the custom optoelectronic circuit of this embodiment is not used in comparison with the case where it is realized by the reconfigurable optoelectronic circuit 91 using the first design result. Therefore, the circuit area can be greatly reduced. In addition, the internal configuration of the optical port, for example, the configuration of the optical coupling unit, the arrangement and number of the light emitting units, and the like are optimum configurations for each optical port, so that high performance and miniaturization can be achieved. This can also lead to an improvement in performance such as an increase in operating frequency and lower power consumption.

As described above, in this embodiment, a custom photoelectric fusion circuit is designed by using the reconfigurable photoelectric fusion circuit 91 as an emulator, thereby realizing a high-performance and highly reliable photoelectric fusion circuit. In addition, the design method of the optoelectronic circuit of this embodiment is more reliable than the design method using only simulation for verification. In particular, when the circuit scale is large, the design time can be shortened and the design cost can be reduced.

The figure which shows the design flow of the photoelectric fusion circuit of this invention. The figure which shows the detail of the design flow of the photoelectric fusion circuit of this invention. The figure which shows the net list | wrist of a fan-out connection, and the broadcast optical connection corresponding to it. The figure which shows the example of Fan-out of parallel wiring. FIG. 3 is a diagram schematically illustrating a configuration of a reconfigurable photoelectric fusion circuit used in the first embodiment. 1 is a diagram (sectional view) illustrating a configuration of a reconfigurable photoelectric fusion circuit used in Example 1. FIG. The figure which shows the structure of the design apparatus of the photoelectric fusion circuit of this invention. FIG. 10 schematically shows an example of a design result in the second embodiment. FIG. 10 is a diagram illustrating an example of a design result (layout) in the third embodiment. The figure which shows the structure of the photoelectric fusion system (photoelectric fusion reconstruction system) of the Example 4 which can be reconfigured. The figure which shows an optical free circuit. The figure which shows the example of the optical coupling part of an optical port. The figure which shows the optical free circuit which has a line waveguide. FIG. 10 is a diagram showing a configuration of a photoelectric evaluation circuit design evaluation apparatus used in Example 5. The figure which shows the design flow in the conventional integrated circuit. The figure which shows the design flow in the system which has the conventional optical connection and the electronic circuit.

Explanation of symbols

10 Netlist creation process (netlist)
11 Photoelectric fusion design process (photoelectric fusion design)
12 Electric net and optical net generation process (electric net and optical net generation)
13 Electric net generation process (electric net)
14 Optical network generation process (optical network)
15 Photoelectric fusion layout design process (photoelectric fusion layout design)
16 Optical port placement process (Optical port placement)
17 Optical connection design process (optical connection design)
18 Electronic circuit layout design process (electronic circuit layout design)
19 Verification process (Verification)
20 Required specifications
21 System design process (system design)
22 Logic design process (logic design)
24 Design result output process (design result)
81 Memory means
82 Design methods
83 Control means
87 Design evaluation means
91 Reconfigurable optoelectronic circuit
92 Circuit for optoelectronic circuit design
93 memory
94 Input / output means (I / O)
95 Bus
100 substrates
101 Optical transmission medium (2D waveguide)
102 optical port
103, 304 Propagating light
104 Radiation angle
105 Electrical wiring layer
106 Electrical wiring
107 chip (reconfigurable electronic circuit)
108 line waveguide
201 logical elements
205 logical blocks
206 Intersection
207 connection
208 Matrix wiring
301 Optical coupling
302 Light irradiation position
303 Light from light emitter
305 Light output section
306 Light emitter

Claims (12)

A method for designing a circuit having electrical wiring and optical connection, comprising at least the following steps.
A first step of generating a circuit connection list (net list);
A second step of generating, from the circuit connection list, a connection list (electric net) carried by the electronic circuit and a connection list (optical net) carried by the optical connection;
A third step of designing parts placement and wiring based on the electrical net;
A fourth step of designing an optical connection based on the optical net. 2. The fifth step according to claim 1, wherein after the second step, before the third step and the fourth step, a fifth step of arranging an optical port which is a component having a photoelectric conversion function is executed. A method for designing a circuit having electrical wiring and optical connection. 3. The design method for a circuit having electrical wiring and optical connection according to claim 1, wherein the electrical net and the optical net are generated so that the number of electrical nets is reduced in the second step. 3. The method for designing a circuit having electrical wiring and optical connection according to claim 2, wherein the optical ports are arranged so that the total electrical wiring length is shortened in the fifth step. The placement and routing design in the third step and the optical connection design in the fourth step are verified, and it is determined whether to return to any one of the second to fifth steps or finish the design. The method for designing a circuit having an electrical wiring and an optical connection according to claim 1, comprising the steps of: The circuit having the electrical wiring and the optical connection has a package structure having a plurality of semiconductor chips, an electrical wiring layer, and an optical connection layer, and at least a part of the connection between the semiconductor chips is optically connected through the optical connection layer. A method for designing a circuit having an electrical connection and an optical connection according to any one of claims 1 to 5. The optical connection layer has a two-dimensional optical waveguide and an optical port for inputting / outputting an optical signal between the two-dimensional optical waveguide, and mutual optical connection is possible across any combination of optical ports. A method for designing a circuit having an electrical connection and an optical connection according to claim 6. The semiconductor chip has a reconfigurable circuit, and in addition to being able to change the internal configuration of the semiconductor chip, it is also possible to change the optical connection between the semiconductor chips via the optical connection layer. A method for designing a circuit having an electrical wiring and an optical connection according to claim 7. An apparatus for designing a circuit having electrical wiring and optical connection, comprising at least the following means.
A first means for generating an electronic circuit connection list and an optical connection list from the circuit connection list;
A second means for storing a circuit connection list, an electronic circuit connection list and an optical connection list;
A third means for designing the layout of the electronic circuit based on the electronic circuit connection list;
Fourth means for designing an optical connection based on the optical connection list. A program for designing a circuit having electrical wiring and optical connection, wherein the computer executes at least the following steps.
A first step of generating an electronic circuit connection list and an optical connection list from the circuit connection list;
A second step of designing the layout of the electronic circuit based on the electronic circuit connection list;
A third step of designing an optical connection based on the optical connection list. Using the circuit having reconfigurable electrical wiring and optical connection and the circuit design apparatus having electrical wiring and optical connection according to claim 9, designing in the design apparatus based on input information, the result of the design Is mounted on a circuit having reconfigurable electrical wiring and optical connection. A method for reconfiguring a circuit having electrical wiring and optical connection. A circuit having a reconfigurable electrical wiring and an optical connection, and the design device for a circuit having an electrical wiring and an optical connection according to claim 9, wherein the design result of the design apparatus is reconfigurable. A design evaluation method for a circuit having electrical wiring and optical connection, wherein the design result is evaluated by mounting the circuit on a circuit having connection and operating the circuit.