JP2005174153A - Method, device and program for designing circuit having electric wiring and optical connection - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a design method and device capable of performing design of a further optimum photoelectric integrated circuit in a relatively short time by using the performance of hardware. <P>SOLUTION: The method for designing a circuit having electric wiring and an optical connection comprises a first step 10 for generating a circuit connection list; a second step 11 for performing a layout design of electronic circuit based on the circuit connection list; a third step 13 for generating an optical connection list composed of a part of the circuit connection list and an electronic circuit connection list composed of the other part thereof; a fourth step 14 for performing a design of optical connection based on an optical connection list; a fifth step 11 for performing a layout design of electronic circuit based on the electronic circuit connection list; and a sixth step 12 for evaluating the layout design of electronic circuit of the second step, or the designs of the fourth step and the fifth step to determine whether the process is taken to the third step, or the designing is ended. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

The present invention relates to a design method, a design apparatus, a design program, and the like for a circuit (also referred to as a photoelectric fusion circuit) in which an electronic circuit connected by electrical wiring and an optical circuit by optical connection are mixed.

Recently, information processing devices such as personal computers, mobile phones, and personal information terminals (PDAs) have been demanded to be faster in processing in addition to being smaller and lighter, but as processing speed increases, Problems such as wiring delay and EMI (electromagnetic radiation interference noise) occur in the circuits used there. As a technique for avoiding these wiring delays and EMI, there is a method using an optical circuit using optical connection (see Patent Document 1).

On the other hand, in the control devices such as the information processing device and the robot described above, it is desired to control by switching a plurality of control algorithms in real time. From such a viewpoint, a circuit that can be reconfigured, particularly a circuit that can be reconfigured at high speed in real time is desired. Examples of reconfigurable circuits include Field Programmable Gate Array (FPGA) and Complex Programmable Logic (CPLD)
device) and the like (see Patent Document 2), further improvement is desired in terms of high speed and circuit scale.

An example of a design flow generally used for designing these information processing devices (semiconductor systems) is shown in FIG. As shown here, in general, after designing a system based on required specifications, through logic design, circuit connection list (net list) generation, layout design (place and route: place and place:
& route), verify. For example, there is a design method using this technique for a system having two chips (Patent Document 3). In such a design method, when a failure occurs in verification, redesign is performed retroactively to placement and routing and further to system design.
JP-A-6-308519 JP 2000-311156 JP 2001-298086

Therefore, in order to realize advanced information processing equipment and control equipment, it is necessary for the circuit to have a large scale, high speed, flexibility (reconfigurable), and such requirements. In order to satisfy the above, it is conceivable to use a circuit in which an optical circuit and an electronic circuit are mixed, that is, a photoelectric fusion circuit.

Conventionally, in the design of a system in which an optical circuit using an optical fiber, an optical waveguide or the like is mounted together with an electronic circuit, the optical circuit and the electronic circuit are clearly shown in FIG. 16 at the initial stage of the system design shown in FIG. Separate and independent design was done. However, in such a design method, since the optical circuit and the electronic circuit are designed independently, it is difficult to perform a design that fully utilizes the performance of both circuits (hardware). Furthermore, optimal design was possible for each of the optical circuit and the electronic circuit, but the performance of the total optimization as the photoelectric fusion circuit was insufficient. In addition, the total design as a photoelectric fusion circuit requires advanced knowledge of both circuits, and a great deal of time and cost.

In view of the above problems, the method for designing a circuit (photoelectric fusion circuit) having an electrical wiring and an optical connection according to the present invention is characterized by having at least the following steps for optimization of the design.
A first step of generating a circuit connection list (net list);
A second step of designing the layout of the electronic circuit based on the circuit connection list;
An optical connection list consisting of a part of a circuit connection list (a connection list carried by an optical connection (optical net)) and an electronic circuit connection list comprising another part (a connection list carried by an electronic circuit (electric net)) 3 steps,
A fourth step of designing an optical connection based on the optical connection list;
A fifth step of designing the layout of the electronic circuit based on the electronic circuit connection list;
The second step of designing the electronic circuit layout, or the design evaluation of the fourth and fifth steps, is performed to determine whether to proceed to the third step or to finish the design. 6 steps.

The third, fourth, fifth and sixth steps are usually repeated one or more times. By repeating the steps in this manner, in addition to the optimum design of the optical circuit and the electronic circuit, the device arrangement, electrical wiring, and optical connection configuration can be optimized as a whole of the photoelectric fusion circuit. In this design method, electronic circuit design and optical circuit design are fused, and a coordinated design is performed, so that a total design of a highly optimized optoelectronic circuit can be realized.

You can also do the following:
In the fourth step, a new electronic circuit is added to the connection portion between the optical connection and the electronic circuit, and a connection list corresponding to the new electronic circuit is added to the electronic circuit connection list.
The photoelectric fusion circuit has a package structure having a plurality of semiconductor chips, an electric wiring layer, and an optical connection layer, and at least a part of the connection between the semiconductor chips is optically connected through the optical connection layer. In this case, the optical connection layer has a two-dimensional optical waveguide and an optical port for inputting / outputting an optical signal between the two-dimensional optical waveguide, and mutual optical connection is performed across any combination of optical ports. Can be as possible. Furthermore, the semiconductor chip has a reconfigurable circuit, the internal configuration of the semiconductor chip can be changed, and further, the optical connection between the semiconductor chips is changed via the optical connection layer. Can also be possible.

In view of the above problems, the optoelectronic circuit designing device of the present invention has at least the following means.
A first means for storing a circuit connection list;
A second means for designing an electronic circuit layout based on the circuit connection list;
A third means for generating an optical connection list comprising a part of the circuit connection list and an electronic circuit connection list comprising another part;
A fourth means for designing an optical connection based on the optical connection list;
Fifth means for performing design evaluation of the electronic circuit layout design of the second means and the design of the fourth means;
Control means for controlling the execution order of the first to fifth means.
With this design apparatus, the above design method is reliably and suitably implemented.

In view of the above-described problems, the optoelectronic circuit design program according to the present invention causes a computer to execute at least the following steps.
A step of designing a layout of an electronic circuit based on a circuit connection list;
A branch step in which design evaluation is performed, and a next step is selected based on the result of the design evaluation;
Generating an optical connection list comprising a part of the circuit connection list and an electronic circuit connection list comprising the other part;
Designing an optical connection based on the optical connection list;
By implementing this design program on a computer together with data such as a net list and an evaluation guideline, the above design method is reliably and suitably implemented.

Further, in view of the above problems, the photoelectric fusion circuit of the present invention has a plurality of electronic circuits, an electrical wiring portion, and an optical connection portion, and is configured to be designed using the above design method, or It is characterized by being designed using the above design method.

Further, in view of the above problems, a photoelectric fusion circuit reconfiguration device according to the present invention includes the above-described photoelectric fusion circuit design device and input / output means. In the design device based on information from the input / output means, It is characterized in that the design is made and the result of the design can be mounted on a reconfigurable optoelectronic circuit. Here, the processing data input from the input / output means is processed by a reconfigurable optoelectronic circuit mounted with the design result, and the processing data is output from the input / output means. Can be done. Such a reconstruction device is an application example of the design device of the present invention, and realizes a photoelectric fusion reconstruction system such as a photoelectric fusion system that can be reconfigured in real time.

Further, in view of the above problems, the photoelectric fusion circuit reconfiguration method of the present invention uses a reconfigurable photoelectric fusion circuit and the above-described photoelectric fusion circuit design apparatus, and designs in the design apparatus based on input information. The result of the design is mounted on the reconfigurable optoelectronic circuit. This reconfiguration method is a usage example of the design apparatus and photoelectric fusion circuit of the present invention, and is a reconfiguration method corresponding to the photoelectric fusion reconstruction system.

Further, in view of the above problems, the photoelectric evaluation circuit design evaluation apparatus of the present invention is implemented by mounting the above-described photoelectric fusion circuit design apparatus and the design result of the design apparatus on a reconfigurable photoelectric fusion circuit. And an evaluation means for evaluating the result of the design. Such a design evaluation apparatus is also an application example of the above-described design apparatus of the present invention, and designs a photoelectric fusion circuit using a reconfigurable photoelectric fusion circuit as an emulator.

In view of the above problems, the photoelectric evaluation circuit design evaluation method of the present invention uses a reconfigurable photoelectric fusion circuit and the above-described photoelectric fusion circuit design apparatus, and redesigns the design apparatus. It is mounted on a configurable optoelectronic circuit, operated, and the result of the design is evaluated. This design evaluation method is also a usage example of the design apparatus and the photoelectric fusion circuit of the present invention, and is a design evaluation method corresponding to the design evaluation apparatus.

In this way, by using the design method and design apparatus of the present invention, it is possible to design a more optimal optoelectronic circuit in a relatively short time using the performance of hardware. Thereby, the cost performance of the final photoelectric fusion circuit can be made excellent. Further, the design method of the present invention can be applied to automatic design of a reconfigurable photoelectric fusion circuit.

Compared to the conventional design method, that is, the method of FIG. 16 in which the electronic circuit and the optical circuit are separated in the system design, the design method and the design apparatus of the present invention have a netlist generated (that is, after logic design). Electronic circuit design, optical connection selection, and optical connection design are usually repeated. Thereby, the design change or specification change of the optical circuit does not greatly change the logic design. For example, when the specifications of an optical circuit are improved, optimization and performance improvement as a photoelectric fusion circuit can be achieved without greatly changing the logic design.

FIG. 2 shows an outline of the design flow of the photoelectric fusion circuit of the present invention. After a schematic system design 21 based on the required specification 20, a circuit connection list (net list) 10 is generated through a logic design 22 and a circuit design, and based on this, a photoelectric fusion characteristic of the present invention is created. Perform layout design 23.

Hereinafter, each process will be described.
First, in the system design 21, a schematic system configuration is determined in view of the required specification 20. The required specification 20 includes functions to be realized, that is, functional specifications and design constraints. The functional specification is a function to be satisfied by the circuit, and is set variously depending on the application, such as an arbitrary control algorithm, image processing, and audio processing. On the other hand, design constraints include performance, power consumption, cost, design period, and the like. Based on these considerations, the system design 21 determines the division of hardware and software and the outline of the hardware configuration. Examples of the hardware configuration include, for example, the number and type of semiconductor chips, the number of layers of the electrical wiring substrate, the area, the quantity, and the configuration of the optical connection module described later. However, some of these hardware configurations may be restricted as design constraints.

In the system design 21 of the present invention, it is not always necessary to assign an optical connection to an electronic circuit. Of course, such allocation may be performed as a provisional initial design, but it is assumed that the photoelectric fusion layout design 23 will be changed later.

Next, the logic design 22 is performed to obtain the netlist 10. The netlist is data describing circuit connection information. In the present invention, the means for obtaining the netlist 10 is not particularly limited, and any logic synthesis tool or other means can be used. For example, a hardware description language (hardware
It is described in RTL (register transfer level) using description language), and logic synthesis is performed using a logic synthesis tool to obtain a gate level netlist. At this stage, logic verification simulation can be performed to increase the reliability of the design.

Alternatively, a netlist may be created by performing behavioral synthesis from a description in C language. In addition, any IP (intellectual) such as processor, memory, interface, data compression, image processing, etc.
property) macros can also be used for logical design. As the netlist, any connection information such as a transistor level, a gate level, a cell level, a functional block (cell set) level, an IP macro level, or the like can be applied. Furthermore, in the case of a design having an analog circuit, the circuit design of the analog part is finished at this stage and used as a macro, so that the net list creation process can be advanced.

Next, based on the netlist 10, a photoelectric fusion layout design 23 is performed.
In this process, the arrangement of various parts, connection of electrical wiring, optical connection, and the like are designed. Here, the component refers to a cell in a standard cell LSI, a functional block having one function in a set of cells, a block corresponding to an IP macro, and the like. In a system to which an FPGA is applied, a logic cell, a configurable block (a collection of logic cells), a block corresponding to an IP macro, and the like correspond to this. Furthermore, in the case of a system in which a plurality of chips are mounted, a single chip or device is also included in the component. This also includes an optical port described later (a port for performing at least one of light output and input).

That is, in the photoelectric fusion circuit mounting a plurality of chips, in this step, the chip arrangement, the optical port arrangement described later, the wiring between the chips, the optical connection between the optical ports, the cell arrangement in the chip, the chip internal This is a step of designing the electrical wiring and the like. Further, this step may include a circuit analysis step in addition to the above-described layout and wiring and optical connection design.

Based on the design result (output layout information) 24 obtained by the optoelectronic layout design 23, mask design is performed, and an optical module including a semiconductor chip, a printed circuit board, an optical port, an optical waveguide, etc. is manufactured. . When a reconfigurable device such as an FPGA is used as the semiconductor chip, the internal configuration of the chip is changed, that is, reconfigured (configured) based on the output information. Furthermore, when the optical module has a variable portion (for example, the position and arrangement of the mirror, the lens, the light emitting element driving means, etc.), the variable portion is changed based on the output information, and the light in the optical module is changed. The connection mode may be changed (reconfigured).

<Photoelectric fusion layout process>
The above-described photoelectric fusion layout process will be further described with reference to the flowchart of FIG.
In this process, step 11 for designing the layout (placement and routing) of the electronic circuit based on the netlist 10
・ Step 12 of design evaluation with branches,
Step 13, assigning part of the net to the optical connection
・ Step 14 of designing optical connections
Have

Hereinafter, the contents of each step will be described along the flow.
First, component layout, electrical wiring, and electronic circuit analysis are performed as the first electronic circuit layout design 11. A general method can be applied as the placement and routing of the electronic circuit. For example, the min-cut method (min-cut method)
placement) or the like. Wiring includes line search router, maze-running router, channel wiring method (channel
router) or the like. In addition, the wiring can be divided into a schematic wiring for assigning each net to a channel set in the wiring area and a detailed wiring for determining a wiring path in each channel. As the electronic circuit analysis, a delay value of a signal in each net is calculated from the wiring resistance and wiring capacitance of the wiring itself, and timing analysis is performed based on the delay value. In addition, EMI analysis such as crosstalk and waveform distortion may be performed.

The first design here preferably satisfies the required specifications (circuit speed, circuit area, power consumption, etc.), but it does not necessarily have to be satisfied. This is because improvement can be expected in the following flow. In that sense, it is sufficient to design with a lighter load than the conventional layout design. In particular, setting the design time of the electronic circuit layout in advance is effective for shortening the design time. In this case, the optimum solution among the solutions obtained in the design time is used as a result, and the process proceeds to the next step.

Next, the first design evaluation 12 is performed. In the design evaluation, evaluation is made such as how much the result of the first electronic circuit layout design meets the required specifications (circuit speed, circuit area, power consumption, etc.) and where there is a problem. Make a decision based on this,
Judgment A: Proceed to the flow of optical connection, aiming to improve the design,
Judgment B: Output layout information and finish the design (proceed to the next step),
Proceed to either. Judgment criteria can be arbitrarily set by the designer. For example, circuit speed, power consumption, number of gates, circuit area, total wiring length of electronic circuit, and the like can be cited as examples. It may be possible to determine whether the evaluation is good or bad by setting these with priorities, or by setting a target function by weighting them and calculating them.

For example, in the simplest case, there is an example in which determination A is made when the specification is not satisfied (no), and determination B is made when the specification is satisfied (yes). In the case of determination A, the process proceeds to step 13 of optical connection assignment. Save analysis results such as layout results and delay calculations before migration.

In step 13 of optical connection assignment, a part of the netlist is assigned to the optical connection. As a result, an optical connection net is generated (updated if an optical connection net already exists). In addition, an electronic net is generated by removing the part assigned to the optical connection net from the net list. In this assignment, a plurality of electrical wirings can be assigned to the optical connection. For example, it is conceivable that a plurality of parallel wires are assigned to a one-to-one serial optical connection, and a plurality of fan-out signals are assigned to a broadcast optical connection.

At this time, which net is assigned to the optical connection can be randomly assigned or assigned based on an assignment guideline. The former can be assigned at high speed, and the latter can be assigned with high accuracy for performance improvement. When performing allocation based on the guideline, the selection is made based on the layout results, circuit analysis results (such as electrical wiring delay results), optical module constraints, and the like.

As a guideline for assignment, assign a net that transmits high-speed signals, assign a net that requires long-distance connection, assign a net that goes through many vias, assign a net that has a large wiring path compared to a straight line distance, Examples include Fan-out nets, high Fan-in nets, and parallel wiring.

Next, the optical connection design 14 and analysis are performed on the optical network that is the connection list that the optical connection is responsible for. In designing an optical connection, an optical transmission medium and an optical port are designed.

Subsequently, the second electronic circuit layout design 11 is performed based on the electronic network. The design method can be performed by the same method as the first time. However, in this case, since a part of the net is assigned to the optical connection as compared with the previous time, the part of the electronic net is reduced as compared with the previous electronic net (initial net list). On the other hand, the number of parts called optical ports has been increased, and wiring and electronic circuits to the optical ports have been added. Since the contents of the electronic net have changed in this way, the optimum solutions for the first and second electronic circuit layout designs are different.

The second design may be newly designed separately from the first design, or may be improved based on the first design result. As for the latter, for example, it is conceivable to preferentially replace the arrangement of components connected to the optical port. Further, in the timing analysis, it is preferable to perform analysis in consideration of both the delay result of the electrical net that is a connection list carried by the electronic circuit and the delay result of the optical net (including the added portion).

Subsequently, the second electronic circuit layout design 11 is completed, and the second design evaluation 12 is performed. This step can be performed in the same manner as the first design evaluation described above. That is, judgment A or judgment B is selected based on the design evaluation criteria. As the determination criteria, as in the first time, circuit speed, power consumption, number of gates, circuit area, total wiring length of electronic circuit, and the like can be cited as examples. In addition, regarding the optical connection, the effective utilization of the optical port may be used as a reference.

Further, in the second and subsequent evaluations 12, it is possible to make a judgment based on whether the result is improved or worsened compared to the previous and past results. The number of times this design evaluation step is performed may be one of the criteria for determination.

In the second and subsequent optical net assignments, in addition to the existing optical net, a part of another electronic net can be added to the optical net. In addition, the existing optical net can be deleted, and another electronic net can be newly transferred to the optical net. However, the initial netlist always exists on either the electronic or optical net.

By repeating such a flow, the design can be gradually improved to a good quality. That is, after allocating a part of the net to the optical connection, the electronic circuit is laid out and evaluated many times, and a more optimal design can be realized.

The method described above has the following merits.
In the conventional electricity-only design, the layout and wiring are redesigned many times until the specification is satisfied, and thus the layout and wiring often requires a lot of time. In addition, there was little redundancy and flexibility for changing specifications. However, in the present invention using the above-described method as a typical example, it is possible to increase design efficiency by having a flow option to a new optical connection, and to provide redundancy for specification changes and the like. Remarkably improved.

In addition, in the design method of the present invention using the above method as a typical example, in addition to the optimum design of the optical circuit and the electronic circuit, the arrangement of the devices, the electrical wiring, and the optical connection configuration as the whole of the photoelectric fusion circuit are optimum. A simplified design can be provided in a relatively short time. In addition, since the design of the electronic circuit and the design of the optical connection are alternately and time-sequentially performed, the process is linearly performed and the stability of the design flow is excellent. Furthermore, a general electronic circuit design tool can be used for the design portion of the electronic circuit layout, and thus the design method of the present invention is excellent in compatibility with a general electronic circuit design tool.

Hereinafter, the present invention will be described with reference to specific examples. However, the present invention is not limited to the embodiments described below, and can be changed in configuration, manufacturing method, sequence, addition of steps, omission, etc., as long as they are included in the above concept.

"Example 1"
In this embodiment, a reconfigurable photoelectric fusion circuit is used as hardware, and the above-described photoelectric fusion layout technique is applied to the automatic design of this circuit. As shown in Fig. 5, a reconfigurable optoelectronic circuit is a mixture of a reconfigurable electronic circuit (FPGA) and an optical free circuit using a planar or two-dimensional (2D) optical waveguide described later. A circuit was used.

In reconfigurable electronic circuits such as FPGAs, with the increase in scale and high integration, in particular, the influence of electrical wiring delay increases, and the time and cost required for design optimization tend to increase. On the other hand, in a system that requires real-time reconfiguration, circuit design in a shorter time is desired. In addition, there is a method to electrically connect multiple FPGAs to increase the scale, but the electrical wiring between chips is fixed and lacks flexibility, so a reconfigurable circuit spans multiple chips. As a result, the limit was large.

The reconfigurable optoelectronic circuit used in this embodiment solves this problem by interconnecting FPGAs with an optical free circuit. The optical free circuit is essentially capable of complete coupling (coupling characteristics that allow free optical connection between optical ports), and has a very high degree of freedom in connection, such as multicast transmission. Thereby, the FPGAs can be connected by an optical free circuit, and reconfiguration across a plurality of chips can be performed with a high degree of freedom. With such a configuration of the photoelectric fusion circuit, it is a reconfigurable circuit having high speed and flexibility in addition to a large scale. Furthermore, such an optoelectronic circuit can alleviate the RC signal delay and EMI problems of the in-chip wiring by using optical connection, so that a large-scale and high-speed reconfigurable circuit can be realized.

On the other hand, an optoelectronic circuit having an optical free circuit has an advantage that the degree of freedom of optical connection is remarkably high. On the other hand, since the degree of freedom is high, there are many options and it is difficult to perform optimal design. From such a viewpoint, an advanced design technique is desired particularly in a photoelectric fusion circuit to which an optical free circuit is applied. From this point of view, a particularly preferable example is configured by applying the design method of the present invention that can provide a method for realizing an optimum design in a short time to a reconfigurable optoelectronic circuit described in detail below. .

<Hardware>
First, hardware used in this embodiment, that is, a reconfigurable optoelectronic circuit will be described in detail with reference to FIGS. 5 and 6 are schematic views for explaining the circuit board of this embodiment. FIG. 5 corresponds to a planar layout of the circuit, and FIG. 6 is a sectional view thereof. 5 and 6, reference numeral 100 denotes a substrate, 101 denotes a two-dimensional (2D) optical transmission medium (2D waveguide), 102 denotes an optical port that performs at least one of light output and input, and 103 propagates through the optical transmission medium 101. Propagating light, 105 is an electrical wiring layer, 106 is an electrical wiring, 107 is a reconfigurable electronic device, 201 is a logical element, 205 is a logical block (corresponding to the electronic device 107 whose configuration in FIG. 6 can be changed), 206 is a crossing portion, 207 is a connection portion, and 208 is a matrix wiring which is an electrical connection network. As shown in FIG. 5, a plurality (nine) of 400,000-gate FPGAs are mounted as reconfigurable electronic circuits 205, and they are interconnected by an optical transmission medium 101 that forms an optical free circuit and electrical wiring 106. .

Further, as shown in FIG. 6, an electronic module having an FPGA and an electric wiring layer 105 and an optical module having a 2D waveguide 101 and an optical port 102 are laminated and bonded to form a layer structure. In addition, an electrical wiring layer 105 having electrical wirings 106 for connecting the chips 107 is laminated and mounted in a compact manner. The number of layers of the optical transmission medium 101 can be any number, but in this embodiment, the number of layers is one. Further, the adjacent FPGAs are connected by 32 electrical wirings by the electrical wiring layer 105.

Further, as shown in FIG. 6, the optical transmission medium 101 is sandwiched between the electric wiring layers 105, and an optical port 102 is provided in the vicinity of the interface between the electric wiring layer 105a and the optical transmission medium 101. The size of the substrate 100 is 3 cm □. Further, as shown in FIG. 5, nine FPGA 205 ([1, 1] to [3, 3]) are arranged, and one optical port 102 is arranged corresponding to each FPGA 205. ing. Thus, the FPGA 205 is connected to the optical port 102 having a function of transmitting or receiving an optical signal to the optical transmission medium 101 (the optical port is not shown in FIG. 5).

As described above, the optical transmission medium 101 has a configuration of a 2D optical waveguide. Here, a 100 μm thick polycarbonate (refractive index: 1.59) coated with fluorinated polyimide (refractive index of about 1.52) as a clad is used. In the optical connection thus established, an electrical signal output from one FPGA 205 is converted into an optical signal at the optical port 102, and the optical signal propagates through the 2D optical waveguide, which is the optical transmission medium 101, and then another optical signal. It is converted into an electrical signal at the port 102 and input to another FPGA 205.

In this way, the FPGAs are connected by both electrical wiring and an optical free circuit. Which is used for signal transmission can be selected by switching the connection terminal inside the FPGA.

As described above, in addition to changing the internal configuration of the electronic circuit (FPGA) 107 or 205, the photoelectric fusion circuit of this embodiment can be configured to freely change the optical connection between the FPGAs. It is possible to change. That is, the connection between the FPGAs via the optical free circuit can be reconfigured.

The configuration of the optical free circuit will be further described.
An optical free circuit is a circuit that transmits information using light as a carrier, and is a circuit that can freely change the transmission form of information between optical ports 102 via an optical transmission medium 101. In this embodiment, the optical free circuit includes a two-dimensional waveguide (planar optical waveguide) 101 and an optical port 102.

In an optical free circuit, an optical port can be arranged at an arbitrary position of a two-dimensional waveguide if it is desired to transmit it, and optical data is transmitted two-dimensionally from an optical port arranged at an arbitrary point to an arbitrary optical port. can do. For example, the light 103 can be propagated at an arbitrary radiation angle 104 over the plane of the optical transmission medium 101 as shown in FIG. However, in the present embodiment, nine optical ports 102 in which positions are fixed in advance are used. Each optical port can broadcast an optical signal to all other optical ports. As mentioned earlier, at the optical port 102, the FPGA
A signal from 107 or 205 is converted into an optical signal. The optical signal propagates through the optical transmission medium 101, is converted into an electrical signal in another optical port 102, and is input to another FPGA 107 or 205.

The optical port 102 has a function of transmitting or receiving an optical signal. That is, it has an optical output unit that converts an electrical signal into an optical signal, an optical input unit that converts an optical signal into an electrical signal, or both. The light emitted from the light emitting element that is the light output unit of the optical port responsible for transmission propagates through the optical transmission medium 101 and is input to the light receiving element that is the light input part of the optical port responsible for reception. By converting the signal into an electrical signal at the optical port responsible for reception, signal transmission from the optical port 102 to the optical port 102 is performed, and an optical circuit is configured.

For the light output unit, for example, a surface emitting laser can be used. Specifically, an electrical signal is converted into an optical signal by applying a logic signal (for example, 3.3 V) of the FPGA 107 or 205 input to the optical port 102 to the light emitting element so as to be forward biased. Here, a 0.85 μm band emitting laser (VCSEL) is used as the light emitting element. Standard VCSEL characteristics are 3mW optical output at a drive current of 3.0mA.

Furthermore, as shown in FIG. 11, the optical port 102 is configured to be able to propagate at various in-plane radiation angles and radiation directions. In order to realize this, a quadrangular pyramid-shaped mirror as shown in FIG. 12A can be used as the optical coupler 301 for optically coupling the optical port 102 and the optical transmission medium 101. Here, the light 303 from the light emitting element 306 of the light output unit 305 is irradiated from above the pyramid mirror 301, reflected in the lateral direction, and coupled to the optical transmission medium 101. As shown in FIG. 12 (b), when the light from the light emitting element 306 is irradiated to the light irradiation position 302 on one slope of the pyramid 301, the propagation of the light 304 is realized with an in-plane radiation angle of approximately 90 °. When the four inclined surfaces are irradiated as shown in FIG. 12 (c), the light 304 is propagated at an in-plane radiation angle of 360 °. For 2 and 3 slopes, they are 180 ° and 270 °, respectively. Since the pyramid slope is a diffusing surface, uniform light is propagated over a range of radiation angles.

In the example of FIG. 12, five light emitting elements 306a, 306b, 306c, 306d, and 306x are arranged above the pyramid mirror 301, for example, one for each inclined surface and one for the center. It is arranged to irradiate each slope. With such a configuration, the emission angle can be set by selecting a light emitting element. For example, if the center light emitting element 306x is used, if one of 306a to d is selected in all directions of 360 °, the direction of 90 ° is determined if two are selected, and the direction of 180 ° is selected if two are selected. If you select three, you can propagate in the direction of 270 °, and if you select four, you can propagate in the direction of 360 °. In this manner, by arranging a plurality of light emitting elements in the optical port 102 and selecting the light emitting element to be driven, the radiation angle and the radiation direction can be switched. The light emitting element can be selected in the FPGA 107 or 205.

Here, an example of an optical port in which a pyramid mirror is used and a radiation angle and a radiation direction can be selected in units of 90 degrees is shown, but the present invention is not limited to this. Even if an optical port that can broadcast in almost all 360 ° directions, can realize beam-like propagation with a radiation angle as small as possible corresponding to the radiation angle of the light emitting element, and can also propagate in various directions, etc. Good.

The optical signal propagating through the optical transmission medium 101 is taken into the light receiving element of the optical port 102 and converted into an electronic signal. As the light receiving element, a Si-PIN photodiode can be used, which is connected to the electronic circuit 107 or 205. The converted electric signal is taken into an electronic circuit 107 or 205 such as an LSI nearby as an input electric signal and processed. At this time, if a preamplifier for amplifying an electric signal is integrated with the light receiving element, the voltage can be restored to a CMOS compatible voltage. Further, by using a conical optical coupling section (see the optical coupler 301 in FIG. 12) as the light receiving section, it is possible to receive light from all 360 ° directions of the 2D optical waveguide 101. Thus, by applying an optical port and a 2D optical waveguide and allowing light to freely propagate in the waveguide, the function of the optical free circuit, that is, an arbitrary optical connection between the optical ports becomes possible.

Here, an example of an optical port that can receive light from all directions of 360 ° of a 2D optical waveguide has been shown. However, a plurality of parts that receive light from a limited direction are provided, and it is the same as the previous outgoing optical port. A signal to be received may be selected by selecting a light receiving unit using a technique.

In the present embodiment, as described above, the transmission angle is selected by changing the radiation angle and propagation direction of the optical signal from the transmission optical port, or the reception direction of the optical signal is changed at the reception optical port. Then, the circuit connection is changed (reconfigured). In addition, it is possible to reconfigure the circuit by selecting data at the reception optical port. For example, the transmission optical port can transmit information to a desired reception optical port by giving information as a packet signal and broadcast-transmitting the information, and selecting the address by the reception optical port.

In this way, the optical free circuit is essentially a circuit capable of realizing full bidirectional coupling at the optical port. Further, 1: N multicast communication, N: M communication, and the like can be realized. Furthermore, these connections can be freely changed (reconfigured), and one-to-one, 1: N or N: M transmission can be freely switched (reconfigured). In the optical free circuit of this embodiment, the data transfer rate between the optical ports is 1 Gbps at maximum, typically 500 Mbps.

Here, the reason why the 2D waveguide is preferable as the optical waveguide used in the optical free circuit, not the line waveguide or the free space connection will be described. First, an optical circuit using an optical fiber or a line waveguide may be used. However, since the line wiring is fixed, the degree of freedom of wiring is inferior. Realizing reconfiguration of an optical circuit with this configuration involves difficulties such as the need for many optical switches. Furthermore, the linear optical waveguide needs to be aligned with the optical axis in a size of several microns to several tens of microns, which is difficult. In addition, the optical waveguide needs to be finely processed and is difficult to manufacture.

On the other hand, by applying the 2D waveguide, an optical device (light emitting element or light receiving element) can be mounted at a desired arbitrary position, and information can be transmitted between arbitrary positions. Furthermore, optical alignment is facilitated in optical coupling between the optical device and the waveguide layer. Because of such a simple configuration, a circuit board can be easily formed, and the cost can be reduced. Furthermore, as will be described later, in an optical free circuit to which a 2D optical waveguide is applied, an optical circuit can be reconfigured basically only by controlling an optical port that is an optical input / output unit.

On the other hand, since the line waveguide is capable of high-speed signal transmission, it may be embedded in a 2D optical waveguide to carry out a predetermined fixed connection. For example, as shown in FIG. 13, a line waveguide 108 may be prepared for connection between distant chips 107. As an optical transmission medium, a method of propagating light in free space has been proposed. However, this method has a problem that the wiring size is high but the size becomes large. A configuration using an optical free circuit using a 2D optical waveguide can realize a thin and high-density circuit board.

The above-described reconfigurable optoelectronic circuit can reconfigure the optical connection in the optical free circuit in addition to the circuit configuration inside the FPGA. The information responsible for the reconfiguration will be referred to as configuration data. This is information output by the design of the photoelectric fusion circuit described above.

The reconfigurable optoelectronic circuit of this embodiment can read configuration data from the outside and reconfigure the entire circuit. By rewriting the configuration data, the design of the circuit inside the FPGA is changed and the electronic circuit (inside the FPGA and the electrical connection between the FPGAs) is reconfigured. In addition, the FPGA via the optical free circuit such as optical port selection The connection is changed (reconfigured). More specifically, the optical circuit is reconfigured by changing the radiation angle and the radiation direction at each optical port based on the configuration information.

In the reconfiguration, the entire circuit may be reconfigured or may be partially reconfigured. If similar functions can be satisfied, partial reconfiguration is more preferable because high-speed reconfiguration can be realized.

<Design method>
Next, a design method applied to the above-described reconfigurable optoelectronic circuit in this embodiment will be described. In this design method, as shown in FIG. 2, a system design 21 and a logic design 22 are performed based on a required specification 20, and a net list 10 at a gate level is output. The application includes contents obtained by adding an image processing function to a video signal decoder. In the logic design 22, as described above, it is described in RTL using a hardware description language, and logic synthesis is performed using a logic synthesis tool to obtain a gate level netlist 10.

Next, based on the netlist 10, a photoelectric fusion layout design 23 characteristic of the present invention is performed. Here, the design was performed using the optoelectronic circuit design apparatus shown in FIG. This optoelectronic circuit design device has input / output means, storage means 81, design means 82, and control means 83.

The storage means 81 is a part for storing the net list obtained as described above, various design parameters, design results, intermediate design results, design time, functional specifications as required specifications, design constraints, and the like. The input / output means is a means for allowing the above-described data to be input from the outside and outputting design results, evaluation results, and the like to the outside. The design means 82 includes electronic circuit layout design means (including arrangement means and wiring means), optical connection allocation means, optical connection design means, and design evaluation means. The control means 83 controls the entire design means 82. In the present embodiment, the design means 82 and the control means 83 are implemented as programs (software) in a general computing device.

  The design described below is performed using the design means 82 as appropriate. FIG. 3 (a) is a diagram showing a flow of optoelectronic layout design used in this embodiment. First, the first electronic circuit layout design is performed. As layout design, place and route, and circuit analysis. Here, the design is performed using only electric wiring under the restriction that no optical connection is used. A min cut method is used as a method for arrangement, and a channel wiring method is used for wiring. Also, the maximum time for placement and routing is 3 minutes, and when this time is exceeded, the process proceeds to the next step with provisional results. As the electronic circuit analysis, a delay value of a signal in each net is calculated from the wiring resistance and wiring capacitance of the wiring itself, and timing analysis is performed based on the delay value. In addition, power consumption is estimated.

Next, design evaluation is performed. In this embodiment, the following evaluation criteria are set based on the required specifications.
First evaluation criterion: The operating frequency is 50 MHz or higher.
Second evaluation standard: Power consumption is 0.8 W or less.
If the design result does not satisfy the evaluation criteria, the process proceeds to the optical connection flow as decision A, and aims to improve the design. If both evaluation criteria are satisfied (yes), layout information is output as decision B, the design is terminated, and the fact that no optical connection is used is output. In this case, in view of effective use of hardware, it is preferable for the designer to design again with a higher evaluation criterion. However, in the first design of this example, that is, in the design of only the electronic circuit, a result satisfying the specifications was not obtained.

In the case of determination A in the design evaluation, the process proceeds to the optical connection generation step. Before the transition, the layout result, the delay calculation result, and the like are stored and used in the subsequent steps. Here, a part of the net list is assigned to the optical connection, and an optical connection net and an electronic net are generated.

In the present embodiment, based on the previous analysis results (such as electrical wiring delay results), the optical connections are assigned with the following priorities as guidelines. A low number is assigned a high priority.
Guideline 1: Assign a net connected to a node (start point of a net) with a high Fan-out to an optical connection.
Guideline 2: Assign nets connected to nodes with high Fan-in to optical connections.
Guideline 3: When there are a plurality of nets having the same start point node and end point node, that is, the portion of the parallel electric wiring is assigned to the optical connection.
Guideline 4: Assign a net with a large electrical wiring delay to the optical connection.
Guideline 5: Assign a high-speed signal transmission network to the optical connection.
Guideline 6: Assign a net having a long wiring distance to the optical connection.
Guideline 7: Assign a net having a large (straight distance between nodes) / (wiring path) to the optical connection.

In the design of a photoelectric fusion circuit to which an optical free circuit is applied, it is more preferable to use the contents of the guidelines 1 and 2 with high priority from the viewpoint of obtaining a design that takes advantage of hardware (optical free circuit). In addition, since problems such as crosstalk are likely to occur in long parallel electric wirings, it is also preferable to preferentially assign these to optical connections. A guideline with a lower priority is adopted as a guideline in the optical network assignment process in which the number of trials is advanced.

Next, design and analysis of the optical connection is performed. Here, the optical port for transmission and the optical port for reception are selected for the assigned optical network, and the light transmission angle and the light emission angle are determined in what manner the light is transmitted in the optical port for transmission. Decide what you want to communicate. In this embodiment, the receiving optical port does not have a function of selecting which direction the light is received from. However, when hardware having such a function is used, this is used. You can also choose.

The optical port is selected by selecting an optical port close to the position of the transmission end of the net in the layout. The selection of the radiation direction and the radiation angle, that is, which light emitting element 306 is used in FIG. 12, is selected so as to be most effective in view of the position of the optical port for reception.

If necessary, electronic circuits such as registers, flip-flops, serializers, and deserializers are newly added around the optical port. At this time, these additional contents are added to the electronic net. For example, when the parallel electrical wiring portion is assigned to the optical connection, a serializer may be added to the transmission side optical port, and a deserializer may be added to the reception side optical port.

As the analysis of the optical connection, an analysis of the light amount used for the optical connection, a transmission rate analysis based on the light amount analysis, a delay analysis, and the like are performed. Thus, after confirming that the optical connection can achieve the desired data transmission, the optical connection design data is stored. In addition, if the optical connection design for the optical network is not successful, the selection of the optical network can be changed.

Subsequently, the second electronic circuit layout is designed. At this time, since a part of the net is assigned to the optical connection, the electronic net of the part is reduced compared to the previous time. On the other hand, the number of parts called optical ports has been increased, and wiring and electronic circuits to the optical ports have been added. As a result, the result of the electronic circuit layout design becomes different from the previous one. In the timing analysis, analysis is performed in consideration of both the delay result of the electric net and the optical net (including the added portion).

Next, the second time of the electronic circuit layout design is finished, and the second design evaluation is performed. Similar to the design evaluation described above, it can be implemented. That is, in the case of determination A, the process proceeds to the optical connection flow. In the case of determination B, the layout information is output and the design ends. However, from the second time onward, the following criteria are added by combining the comparison with the previous results as follows (see Fig. 3 (b)).
・ If the result is improved compared to the previous time and meets the specifications, it will be judged as A.
・ If the result is improved compared to the previous time and does not meet the specifications, it is also judged as A.
・ If the result is worse than the previous time but does not meet the specifications, it is judged as A.
-When the result is worse than the previous time and the specification is satisfied, as the decision B, the previous result is adopted and the design is finished.
Here, the case where the value of (operating frequency / power consumption) became large was improved, and the case where the value became small was made worse.

In the second and subsequent optical network assignments to be performed, if the result is improved as compared with the previous design evaluation, the previous optical network assignment is adopted, and a new optical network is added thereto. On the other hand, if the result is worse than the previous time, the previously assigned net is deleted, the process proceeds to the optical connection assignment again, and an attempt is made to connect another net to the light. Here, the same allocation guidelines as those used for the first time are used.

By repeating such a flow, the design can be gradually improved to a high quality. That is, after allocating a part of the net to the optical connection, the electronic circuit is laid out and evaluated many times, and a more optimal design can be realized. Further, for example, as in Example 2 described later, when the design evaluation is not improved even after repeating 10 times or more, the design may be terminated.

The table below shows an example of results (including intermediate results) designed using the design method of this example.
Design 1 shows that the operation speed and power consumption do not satisfy the specifications (50 MHz or more, 0.8 W or less) after the first electronic circuit design is completed.
Design 1a is an intermediate result after the second design evaluation using optical connection. Design 1b, which shows that the operating speed is improved and the number of gates is reduced, is the final design result. It is a result after repeating the step of design evaluation 60 times. It can be seen that both the operating speed and power consumption meet the specifications.
Design 2 is an example in which a new image processing algorithm is added to the application implemented in design 1. Here, the circuit used in the design 1 is not modified, and only a new part is added.
The design 2a is a result obtained by improving the circuit by repeating the assignment of the optical net, the optical design, and the electronic circuit layout design with the state of the design 2 as an initial state.
Number of gates used Number of optical ports used Operating speed Power consumption design 1 2 million 0 25MHz 0.9W
Design 1a 1 million 3 100MHz 0.85W
Design 1b 1.2 million 5 130MHz 0.6W
Design 2 1.6 million 4 95MHz 0.65W
Design 2a 1.5 million 7 110MHz 0.75W

From the above table, it can be seen that the specification has been insufficient due to the addition of the algorithm, but it was possible to satisfy the specification by improving the design with the method of this example. . As described above, in this embodiment, it was confirmed that the design was changed by changing the required specification, and different design results were output based on the change. In particular, design changes can be made flexibly in response to changes in installed algorithms and specifications.

In the design method of the present embodiment, in addition to the optimum design of the optical circuit and the electronic circuit, the optimization design of the device arrangement, the electrical wiring, and the configuration of the optical connection as a whole of the photoelectric fusion circuit is performed in a relatively short time. I was able to provide it. In the design method of the present embodiment, the best result can be output at that point even if the design is urgently stopped. Furthermore, in this embodiment, even when an electronic circuit layout design uses a lighter load (a program with a short program execution time) than a general design, a good design result was obtained.

Furthermore, the photoelectric fusion circuit designed in this way is designed to make the best use of the hardware performance as illustrated in FIGS. 5 and 6, and has high cost performance. An optoelectronic circuit having an optical free circuit has the advantage that the degree of freedom of optical connection is remarkably high. On the other hand, since the degree of freedom is high, there are many choices and it is difficult to perform optimal design. However, a sufficiently good design can be performed by using the design method as described above.

In the present embodiment, an FPGA is used as a reconfigurable electronic circuit. However, the present invention is not particularly limited to this. As shown in FIG. 5, the reconfigurable electronic circuit may be a circuit including a logic element 201 whose logic function can be changed and an electric connection network whose interconnection can be changed. An example of the logical element 201 is an LUT (Look Up Table) that has an input / output truth table relating to a logical function to be realized in a RAM format and outputs an output signal for an input combination. Further, AND, NAND, OR, NOR, XOR, flip-flops, latches, registers, inverters, multipliers, and the like, or a circuit combining any of these may be included. Furthermore, a memory may be included. In addition, an arithmetic unit (processor) such as integer arithmetic, floating point arithmetic, and function arithmetic may be included.

The electrical connection network can set the connection between the logic elements. For example, the electrical connection network may be composed of electrical wiring and switches arranged in a matrix that connects the logic elements arranged in an array (see FIG. 5). The switch is arranged at a connection portion between the logic element and the electric wiring, an intersection portion of the matrix wiring, or the like. In this embodiment, the reconfiguration system uses only the FPGA, but may have other chips such as ASIC, CPU, DSP, and memory. In this case, an optical port can be prepared for a chip such as an ASIC.

"Example 2"
Example 2 relates to a method for designing a custom photoelectric fusion circuit. In the first embodiment, the hardware is fixed. In other words, an optimal design was performed for a preset reconfiguration system called a photoelectric fusion circuit having nine FPGAs and nine optical ports. In addition, the configuration of the electronic circuit layer including the position of the FPGA and the electric wiring between the FPGAs, the configuration of the optical connection layer such as the number of optical ports, and the position thereof have been set in advance.

The second embodiment is an example in which the hardware includes an ASIC (custom chip) and the other is realized by an FPGA or a memory. The basic structure of the photoelectric fusion circuit is assumed to be the configuration shown in FIG. 6 as in the first embodiment, but the main restriction is to use one custom chip. In addition, as hardware limitations, the maximum number of FPGA chips is 4, the maximum number of electrical wiring layers is 10, the number of optical connection layers is 1, and the maximum number of optical ports is 16.

That is, the position of the FPGA is fixed in the first embodiment, but in this embodiment, the layout of the ASIC and the FPGA is also a design element. In the first embodiment, the configuration of the optical connection layer, such as the position and type of the optical port and the optical transmission medium, is also determined. In the present embodiment, these can also be designed within the range of the above restrictions.

In this embodiment, the outline of the design flow is the same as that of the first embodiment. Hereinafter, different points will be mainly described. Also in this embodiment, as shown in FIG. 2, the system design and logic design are performed based on the required specifications, and the process is the same as that in the first embodiment until the gate level netlist 10 is output. However, since the ASIC has already been designed, it is treated as a fixed block, and its internal circuit is fixed. For the inside of the FPGA, functional specifications were assigned to each chip, and the placement and routing design was performed in advance.

Next, photoelectric fusion layout design 23 is performed. In this embodiment, since the design in each chip has been completed, the design for the chip arrangement and the connection between the chips is performed. Similar to the first embodiment, the electronic circuit layout design 11, the design evaluation 12, the optical connection assignment 13, and the optical design 14 are repeatedly performed.

First, the layout design 11 of the electronic circuit used the same method as in the first embodiment. In the design evaluation of this example, the following objective function was set in order to judge the quality of the design.
Objective function = Operating speed / (Power consumption / Circuit area)
As shown in FIG. 4, in the first evaluation, the value of the objective function is stored and the process proceeds to decision A. In the second and subsequent evaluations, if no improvement is observed in the objective function for 10 consecutive times, layout information is output as decision B and the design is terminated. In other cases, as decision A, the process proceeds to the optical connection flow and aims to improve the design.

In the allocation of optical connections, the allocation method changes based on the previous design evaluation. In the design evaluation, when the objective function is larger than the previous evaluation, a new optical net is added. On the other hand, if the objective function is smaller than the previous time, the previously assigned net is deleted and another net is tried to connect to the light again. In the present embodiment, a net having the largest wiring delay is preferentially assigned to the optical connection based on the previous evaluation result (such as the electrical wiring delay result).

Next, design and analysis of the optical connection is performed. In this embodiment, the configuration of the optical connection layer is not determined in advance, so that the design including the configuration is made. That is, as shown in FIG. 4, the configuration of the waveguide layer, the number of optical ports, the configuration of the optical ports, and the arrangement of the optical ports are designed. Regarding the configuration of the optical port, a library having variations in the configuration shown in FIG. 12, the number of light emitting elements, the structure of the scatterers, and the like is prepared and selected from these.

The optical connection analysis is the same as in the first embodiment. However, in this embodiment, since the design range of the optical connection layer is wide, the design and analysis of the optical connection are repeated so that the design of the optical connection layer can be optimized for the allocation of the optical network. The improvement is planned by this.

FIG. 8 is a diagram showing how the design result of this embodiment changes. A to E are semiconductor chips. In this embodiment, A and D are assumed to be custom chips, and B, C, and E are assumed to be FPGAs. However, the present invention is not limited to this. This is just an example, and the same effect can be expected even if the number and type of chips are different. Further, in FIG. 8, for the sake of simplicity of the drawing and easy understanding of the effect, the number of layers of the electrical wiring is illustrated as one. In this embodiment, actually, there are eight electric wiring layers. The total number of electrical wiring layers and optical connection layers is not limited to the illustrated example.

FIG. 8 (a) shows the result after the first electronic circuit layout design is completed. The wiring indicated by the dotted line connecting A and D could not be connected by electrical wiring. Furthermore, since the wiring connecting B and C has a large delay, the overall speed cannot be increased. From this point of view, the result is insufficient for the specification.

FIG. 8B shows a state in which the first optical connection assignment and the optical connection design are completed, and only the wiring is redesigned as the second electronic circuit layout design. A line with an arrow is assigned to the optical connection. As a result, A and D can be connected by electrical wiring.

FIG. 8 (c) shows the result of further changing the design of the device arrangement. This shows that the circuit area has been reduced. Since the electrical wiring connecting B and C could be shortened, the operation speed of the circuit could be increased.

In this way, after allocating the optical connection, designing the layout of the electronic circuit not only improves performance by replacing part of the electrical wiring with the optical connection, but also changes the device layout along with the optical connection. Optimization is also done. Thus, it can be seen that the total optimization of the photoelectric fusion circuit is performed.

In the design method of the present embodiment, in addition to the optimum design of the optical circuit and the electronic circuit, the optimization design of the arrangement of the devices, the electrical wiring, and the configuration of the optical connection as a whole of the photoelectric fusion circuit is made in a relatively short time. I was able to provide it. In the design method of the present embodiment, the best result can be output at that time even if the design is urgently stopped.

"Example 3"
In Example 3, the type of hardware shown in FIG. 9 was used. In FIG. 9, 100 is a substrate, 101 is an optical transmission medium, 102 is an optical port, 103 is propagating light, 105 is an electric wiring layer, and 107 is a semiconductor chip (the electric wiring layer 105 has electric wiring, Is shown). 107a, 107b, and 107c are FPGAs, and 107d is a custom chip. FIG. 9 (a) is a plan view corresponding to the layout. Figure 9 (b)
FIG. 10 is a sectional view of FIG. 9 (a).

That is, in this embodiment, the optical module having the optical transmission medium 101 and the optical port 102 is arranged in a part of the substrate, and the semiconductor chip 107 is arranged in the other area. Moreover, as a restriction, the optical module is handled as a component, and a semiconductor chip cannot be placed at that position. Since the electric wiring layer is separately provided, it is possible to arrange the electric wiring at an in-plane position of the optical module. Other major hardware restrictions are: 3 FPGA chips, 1 custom chip, 4 electrical wiring layers, 1 cm square optical transmission medium, and optical connection layers Is one layer and the maximum number of optical ports is 10 (see FIG. 9 for arrangement). The optical port is arranged at the end of the optical transmission medium.

In this embodiment, circuits inside the FPGAs 107a, 107b, 107c, electrical wiring between the semiconductor chips 107, and optical connections between the semiconductor chips 107 are designed. The design method is in accordance with Example 2. However, in the step of optical connection design (optical module design), the surface shape, size and position of the optical transmission medium become design items, and in the layout design of the electronic circuit, the position of the optical module becomes a design item. This is a characteristic point of the present embodiment. In particular, the shape design of the optical module has a great influence on the layout of the semiconductor chip.

In the present embodiment, the first electronic circuit layout design (in the case of using only electrical wiring) did not satisfy the specifications, but finally the optical module is arranged in the center as shown in FIG. We were able to meet the specifications. In other words, after assigning optical connections, optical connection design and electronic circuit layout design are performed, so that not only the performance improvement by replacing part of the electrical wiring with optical connections, but also the design of the optical module shape, etc. Along with this, the device layout change is also optimized. In this way, it can be seen that the total optimization of the photoelectric fusion circuit is performed.

In the design method of this embodiment, in addition to the optimum design of the optical circuit and the electronic circuit, the optimization design of the arrangement of the devices, the electrical wiring, and the configuration of the optical connection as a whole of the photoelectric fusion circuit is performed in a relatively short time. I was able to provide it. In the design method of the present embodiment, the best result can be output at that time even if the design is urgently stopped.

"Example 4"
Example 4 is an example of a photoelectric fusion system (photoelectric fusion reconstruction system) that can be reconfigured in real time. An example of a reconfigurable photoelectric fusion system of this embodiment is shown in FIG. As shown in FIG. 10 (a), it has a circuit (device) 92 for designing an optoelectronic circuit, a reconfigurable optoelectronic circuit 91, a configuration memory 93, and an I / O (input / output means) 94.

The circuit 92 for designing the optoelectronic circuit has the means shown in FIG. 7 and is as described above. In this embodiment, these means are integrated into one chip and mounted as hardware.

In the reconfigurable optoelectronic system of the present embodiment, the circuit 92 for designing the optoelectronic circuit based on the input data from the I / O 94 forms (or changes) the design data and stores it in the configuration memory 93. Save design data. The reconfigurable optoelectronic circuit 91 sequentially reads design data from the configuration memory 93 and performs reconfiguration (change of internal configuration). The output from the reconfigurable optoelectronic circuit 91 is output to the I / O 94. In this way, the internal configuration of the optoelectronic circuit 91 can be optimized at any time based on the input data from the I / O 94.

In this embodiment, the optical circuit and the electric circuit are fused, and the design and further reconfiguration can be performed in real time by making the best use of the resources of the photoelectric fusion circuit 91 having high wiring flexibility. That is, it can function as a dynamic reconfigurable system in which the internal configuration of the photoelectric fusion circuit 91 can be freely changed in real time.

In addition, the reconfiguration system of this embodiment is designed to optimize the reconfigurable optoelectronic circuit 91 in a short time in a system that requires sequential hardware reconfiguration in response to continuous changes in the operating environment. Since reconfiguration can be performed, it can be suitably applied to a control system such as a robot. In particular, since repeated design improvements are made, it is possible to respond quickly and flexibly to design changes in response to continuous environmental (specification) changes.

In the present embodiment described above, description has been given along FIG. 10A in which the respective parts are interconnected. However, a configuration in which the respective parts are connected by the bus 95 as shown in FIG. 10B is also possible. is there. Further, the function of the memory 93 may be performed in the reconfigurable photoelectric fusion circuit 91 or the circuit 92 for designing the photoelectric fusion circuit.

"Example 5"
The fifth embodiment is an example in which a reconfigurable photoelectric fusion circuit is used for designing a photoelectric fusion circuit having a fixed circuit. That is, circuit verification and evaluation are performed using the reconfigurable photoelectric fusion circuit used in the first embodiment, and a custom photoelectric fusion circuit is created based on the output result.

The configuration of the design evaluation device used in this example is shown in FIG. A photoelectric fusion circuit design means 82 and a design evaluation means 87 for mounting the design result of the design means 82 on a reconfigurable photoelectric fusion circuit 91 and operating it to evaluate the design result are provided. That is, the design evaluation apparatus of the present embodiment includes design evaluation means 87 in addition to the optoelectronic circuit design apparatus (FIG. 7) used in the first embodiment. Here, as the reconfigurable photoelectric fusion circuit 91, the same hardware as that used in the first embodiment is used.

Using this design evaluation apparatus, a plurality of design results output from the design means 82 are mounted on a reconfigurable optoelectronic circuit 91 and operated to perform performance comparison and function verification. In view of the required specifications, a design result with the most favorable performance is selected. This is called the first design result. Here, the largest result of (operating frequency) / (power consumption) is adopted.

The optoelectronic layout design is performed again based on another custom specification using the electronic net and the optical net derived from the first design result. The main restriction is that the electronic net is realized with an electrical wiring layer and an ASIC or cell-based custom IC. The physical specification of the electrical wiring layer is the same as that of the reconfigurable photoelectric fusion circuit 91. The optical connection layer has the same configuration as that of the reconfigurable photoelectric fusion circuit 91, but the position of the optical port is arbitrary.

This method of optoelectronic layout design again conforms to the method used in the second embodiment. However, in this embodiment, the internal design of the ASIC is made in the electronic circuit layout design. In addition, a circuit realized over a plurality of FPGAs can be mounted on one ASIC. The substrate is square, but size is a design item. The substrate size is set to be as small as possible based on the electronic circuit layout design. Based on this, the position of the optical port is reduced while maintaining the positional relationship. The result obtained here will be referred to as a second design result.

Based on the obtained second design result, a new mask is created for the ASIC, the electrical wiring layer, and the optical connection layer to create a custom optoelectronic circuit. Although the reconfigurable photoelectric fusion circuit 91 can change the circuit configuration, the custom photoelectric fusion circuit is a circuit whose configuration is fixed. On the other hand, the custom optoelectronic circuit of this embodiment is not used in comparison with the case where it is realized by the reconfigurable optoelectronic circuit 91 using the first design result. Therefore, the circuit area can be greatly reduced. In addition, the internal configuration of the optical port, for example, the configuration of the optical coupling unit, the arrangement and number of the light emitting units, and the like are optimum configurations for each optical port, so that high performance and miniaturization can be achieved. This can also lead to an improvement in performance such as an increase in operating frequency and lower power consumption.

As described above, in this embodiment, a custom photoelectric fusion circuit is designed by using the reconfigurable photoelectric fusion circuit 91 as an emulator, thereby realizing a high-performance and highly reliable photoelectric fusion circuit. In addition, the design method of the optoelectronic circuit of this embodiment is more reliable than the design method using only simulation for verification. In particular, when the circuit scale is large, the design time can be shortened and the design cost can be reduced.

The figure which shows the design flow of the photoelectric fusion circuit of this invention (photoelectric fusion layout part). The figure which shows the design flow of the photoelectric fusion circuit of this invention. The figure which shows the design flow of the photoelectric fusion circuit of Example 1 (photoelectric fusion layout part). The figure which shows the design flow of the photoelectric fusion circuit of Example 2 (photoelectric fusion layout part). FIG. 3 is a diagram schematically illustrating a configuration of a reconfigurable photoelectric fusion circuit used in the first embodiment. 1 is a diagram (sectional view) illustrating a configuration of a reconfigurable photoelectric fusion circuit used in Example 1. FIG. The figure which shows the structure of the design apparatus of the photoelectric fusion circuit of this invention. The figure which shows the design improvement effect in Example 2 typically. FIG. 10 is a diagram (plan view) illustrating a configuration of a reconfigurable photoelectric fusion circuit used in Example 3; The figure which shows the structure of the photoelectric fusion system (photoelectric fusion reconstruction system) of the Example 4 which can be reconfigured. The figure which shows an optical free circuit. The figure which shows the example of the optical coupling part of an optical port. The figure which shows the optical free circuit which has a line waveguide. FIG. 10 is a diagram showing a configuration of a photoelectric evaluation circuit design evaluation apparatus used in Example 5. The figure which shows the design flow in the conventional integrated circuit. The figure which shows the design flow in the system which has the conventional optical connection and the electronic circuit.

Explanation of symbols

10 Netlist creation process
11 Electronic circuit layout design process
12 Design evaluation process
13 Network allocation to optical connections (optical network allocation) process
14 Optical connection design process
23 Photoelectric fusion layout design process
24 Design result output process
81 Memory means
82 Design methods
83 Control means
87 Design evaluation means
91 Reconfigurable optoelectronic circuit
92 Circuit for optoelectronic circuit design
93 memory
94 Input / output means (I / O)
95 Bus
100 substrates
101 Optical transmission medium (2D waveguide)
102 optical port
103, 304 Propagating light
104 Radiation angle
105 Electrical wiring layer
106 Electrical wiring
107 chip (electronic circuit)
108 line waveguide
201 logical elements
205 logical blocks
206 Intersection
207 connection
208 Matrix wiring
301 Optical coupling
302 Light irradiation position
303 Light from light emitter
305 Light output section
306 Light emitter

Claims (11)

A method for designing a circuit having electrical wiring and optical connection, comprising at least the following steps.
A first step of generating a circuit connection list;
A second step of designing the layout of the electronic circuit based on the circuit connection list;
A third step of generating an optical connection list comprising a part of the circuit connection list and an electronic circuit connection list comprising another part;
A fourth step of designing an optical connection based on the optical connection list;
A fifth step of designing the layout of the electronic circuit based on the electronic circuit connection list;
The second step of designing the electronic circuit layout, or the design evaluation of the fourth and fifth steps, is performed to determine whether to proceed to the third step or to finish the design. 6 steps. The method for designing a circuit having electrical wiring and optical connection according to claim 1, wherein the third, fourth, fifth, and sixth steps are repeated one or more times. 3. The fourth step according to claim 1, wherein a new electronic circuit is added to a connection portion between the optical connection and the electronic circuit, and a connection list corresponding to the new electronic circuit is added to the electronic circuit connection list. Design method of circuit having optical wiring and optical connection. The circuit having the electrical wiring and the optical connection has a package structure having a plurality of semiconductor chips, an electrical wiring layer, and an optical connection layer, and at least a part of the connection between the semiconductor chips is optically connected through the optical connection layer. A method for designing a circuit having an electrical connection and an optical connection according to any one of claims 1 to 3. The optical connection layer has an optical port for inputting / outputting an optical signal between the two-dimensional optical waveguide and the two-dimensional optical waveguide, and mutual optical connection is possible across any combination of optical ports. A method for designing a circuit having an electrical connection and an optical connection according to claim 4. The semiconductor chip has a reconfigurable circuit, and in addition to being able to change the internal configuration of the semiconductor chip, it is also possible to change the optical connection between the semiconductor chips via the optical connection layer. A method for designing a circuit having an electrical wiring and an optical connection according to claim 5. An apparatus for designing a circuit having electrical wiring and optical connection, comprising at least the following means.
A first means for storing a circuit connection list;
A second means for designing an electronic circuit layout based on the circuit connection list;
A third means for generating an optical connection list comprising a part of the circuit connection list and an electronic circuit connection list comprising another part;
A fourth means for designing an optical connection based on the optical connection list;
Fifth means for performing design evaluation of the electronic circuit layout design of the second means and the design of the fourth means;
Control means for controlling the execution order of the first to fifth means. A program for designing a circuit having electrical wiring and optical connection, wherein the computer executes at least the following steps.
A step of designing a layout of an electronic circuit based on a circuit connection list;
A branch step in which design evaluation is performed, and a next step is selected based on the result of the design evaluation;
Generating an optical connection list comprising a part of the circuit connection list and an electronic circuit connection list comprising the other part;
Designing optical connections based on the optical connection list. A circuit having an electrical wiring and an optical connection, wherein the circuit has a plurality of electronic circuits, an electrical wiring portion, and an optical connection portion, and is designed using the design method according to any one of claims 1 to 6. Using the circuit having reconfigurable electrical wiring and optical connection and the circuit designing apparatus having electrical wiring and optical connection according to claim 7, designing the design apparatus based on input information, and the result of the design Is mounted on a circuit having reconfigurable electrical wiring and optical connection. A method for reconfiguring a circuit having electrical wiring and optical connection. A circuit having reconfigurable electrical wiring and optical connection, and a design device for a circuit having electrical wiring and optical connection according to claim 7, and the electrical wiring and light capable of reconfiguring the design result of the design apparatus A design evaluation method for a circuit having electrical wiring and optical connection, wherein the design result is evaluated by mounting the circuit on a circuit having connection and operating the circuit.