JP2005167779A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which can control output impedance of an output circuit to a desired value even if driving ability of a transistor changes by a secular change, and perform high-speed data transfer. <P>SOLUTION: A conducting period controller 123 controls driving time of a dummy buffer 101 which adjusts driving ability of a PMOS transistor of an output buffer 2 and driving time of a dummy buffer 111 which adjusts driving ability of a NMOS transistor of the output buffer 2. The conducting period controller 123 makes accumulation drive time of the output buffer 2 and accumulation drive time of dummy buffers 101 and 111 to be the same by making the output '1' during a period corresponding to number of '1' data included in a data signal DQ. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device suitable for high-speed data transfer.

  In a high-speed SRAM used for a cache memory or the like of a computer system, various technical developments such as a layout technique and a circuit design technique have been performed to meet the demand for high-speed access, and the circuit operation inside the SRAM device has been accelerated.

  However, as the speed of memory access increases, the signal waveform is disturbed by the reflected wave caused by the mismatch between the impedance of the system bus of the system in which the high-speed SRAM is mounted and the output impedance of the SRAM connected to the system bus. There was a problem that data transfer became difficult.

  In order to solve this problem, a circuit called a program impedance circuit is provided in the SRAM output circuit, and the impedance of the output buffer is controlled so as to match the impedance of the transmission line of the system bus from which the data signal is output. It has been proposed to suppress disturbance of the signal waveform on the line (for example, see Non-Patent Document 1).

  This program impedance circuit is provided with a dummy buffer composed of a plurality of transistors having the same configuration as an output buffer composed of a plurality of transistors. The program impedance circuit makes this dummy buffer conductive at regular intervals, compares the dummy buffer output voltage at that time with the output voltage of the reference resistor having a resistance value corresponding to the impedance of the transmission line, and the value is equal. Thus, the conduction combination of the plurality of transistors of the dummy buffer is controlled. Then, the conduction combination of the plurality of transistors in the output buffer is controlled to be the same as the combination of conduction of the plurality of transistors in the dummy buffer. The impedance of the output buffer changes depending on the combination of conduction of the plurality of transistors.

In such a program impedance circuit, the impedance of the output buffer can be adapted to the impedance of the transmission line by adjusting the reference resistance connected to the external terminal according to the impedance of the transmission line.
"A 300MHz, 3.3V 1Mb SRAM Fabricated in a 0.5um CMOS Process" Harold Pilo et al. ISSCC Digest of Technical Papers, Feb., 1996 (pp. 148-149, Fig. 5)

  By the way, in the high-speed SRAM, in order to cope with high speed and large capacity, not only circuit technology development but also device performance improvement by miniaturization of a semiconductor is achieved.

  In such a miniaturized semiconductor, the driving power of the MOS transistor deteriorates over time due to hot carriers, and in particular, in the PMOS transistor, NBTI (Negative Bias Temperature Instability) deterioration occurs when voltage is continuously applied at a high temperature. Is known to deteriorate more than NMOS transistors. Further, such deterioration of the driving capability of the transistor proceeds according to the cumulative conduction time of the transistor.

  However, in the above-described program impedance circuit, the cumulative conduction time of the transistors is usually different between the dummy buffer and the output buffer. This is because the dummy buffer conducts for a certain period every certain time, whereas the output buffer varies in conduction time depending on the contents of the output data. Therefore, there is a difference in the cumulative conduction time of the transistors between the dummy buffer and the output buffer.

  If there is a difference in the accumulated conduction time, there is a difference between deterioration due to aging of the driving capacity of the dummy buffer and deterioration due to aging of the driving capacity of the output buffer.

  Therefore, in the above-described program impedance circuit, even if the impedance of the output buffer of the SRAM output circuit is controlled to match the impedance of the transmission line of the system bus by controlling the conduction of the transistor of the dummy buffer, the dummy buffer It is expected that the difference in aging between the driving powers of the transistors in the SRAM and the output buffer of the SRAM occurs, and the impedance of the output buffer does not become a desired value.

  In the above-described program impedance circuit, since the conduction of the PMOS transistor and the NMOS transistor in the output buffer are commonly controlled, when the above-described NBTI degradation occurs, the degradation of the PMOS transistor causes the degradation of the NMOS transistor. It is expected that the impedance of the output buffer will be different when the PMOS transistor is conductive and when the NMOS transistor is conductive.

  As a result, if the mismatch between the impedance of the output buffer and the impedance of the system bus increases, the disturbance of the signal waveform due to the reflected wave or the like also increases, and high-speed data transfer on the system bus becomes difficult.

  Accordingly, an object of the present invention is to provide a semiconductor device capable of controlling the output impedance of an output circuit to a desired value and capable of high-speed data transfer even when a change in the driving capability of the transistor due to aging occurs. .

  According to one aspect of the present invention, an output buffer including a plurality of PMOS transistors and a plurality of NMOS transistors, a first dummy buffer including a plurality of PMOS transistors having the same configuration as the plurality of PMOS transistors, A first reference resistor having a second dummy buffer composed of a plurality of NMOS transistors having the same configuration as the NMOS transistor and a combination of conduction of the plurality of PMOS transistors constituting the first dummy buffer connected to an external terminal; Based on the resistance value of the second reference resistor in which the combination of the conduction of the first NMOS controller that adjusts based on the resistance value and the plurality of NMOS transistors constituting the second dummy buffer is connected to the external terminal. A second conduction control unit to be adjusted and an adjustment result of the first conduction control unit; The first register that outputs the recorded data to the plurality of PMOS transistors of the output buffer and the adjustment result of the second conduction control unit are recorded, and the recorded data is stored in the output buffer. A second register that outputs to the plurality of NMOS transistors; a conduction period control unit that controls a conduction period of the first dummy buffer and the second dummy buffer; and the conduction period control unit includes: A semiconductor device is provided in which the first dummy buffer and the second dummy buffer are made conductive for a period corresponding to a conduction period of the output buffer.

  According to another aspect of the present invention, an output buffer unit having a plurality of output buffers each including a plurality of PMOS transistors and a plurality of NMOS transistors, and a plurality of PMOS transistors having the same configuration as the plurality of PMOS transistors. A first dummy buffer, a second dummy buffer composed of a plurality of NMOS transistors having the same configuration as the plurality of NMOS transistors, and a conduction combination of the plurality of PMOS transistors constituting the first dummy buffer. A first conduction control unit that adjusts based on a resistance value of a first reference resistor connected to an external terminal, and a combination of conduction of the plurality of NMOS transistors that constitute the second dummy buffer are connected to the external terminal. Second conduction adjusted based on the resistance value of the second reference resistor A control unit, a first register that records an adjustment result of the first conduction control unit, and outputs the recorded data to each of the plurality of PMOS transistors of the plurality of output buffers, and the second conduction A second register for recording an adjustment result of the control unit and outputting the recorded data to the plurality of NMOS transistors of each of the plurality of output buffers; the first dummy buffer; and the second dummy buffer; A conduction period control unit that controls the conduction period of the output buffer, and an average calculation unit that calculates an average number of data having a conduction level included in the entire data input to each output buffer of the output buffer unit for each predetermined period. Before the period corresponding to the average number of data having the conduction level calculated by the average calculation unit. Wherein a to conduct the first dummy buffer and the second dummy buffer is provided.

  According to the present invention, it is possible to realize a semiconductor device capable of controlling the output impedance of the output circuit to a desired value and capable of high-speed data transfer even when the driving capability of the transistor changes due to aging.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a circuit diagram showing an example of an output circuit according to the first embodiment of the present invention. The output circuit of the present embodiment includes an output buffer control unit 1 and an output buffer 2 that is a 3-state buffer. FIG. 1 shows an example in which the output buffer 2 is composed of four PMOS transistors and four NMOS transistors. However, this is an example of the configuration of the output buffer, and the configuration of the output buffer has four transistors. It is not limited to one.

  First, the output buffer 2 will be described.

  The output buffer 2 includes four PMOS transistors TP1, TP2, TP4, and TP8 whose driving capability connected in parallel between the power supply VDDQ and the output pad is sequentially increased by twice, and in parallel between the ground terminal and the output pad. There are four NMOS transistors TN1, TN2, TN4, and TN8, whose connected driving capabilities are sequentially increased twice.

  The output buffer 2 includes three-input NAND gates 201, 202, 203, and 204 and three-input NOR gates 211, 212, 213, and 214.

  Among these, the NAND gates 201, 202, 203, and 204 receive the data input DQ and the output enable signal OE in common, and individually receive the control signals from the output buffer control unit 1. The outputs of the NAND gates 201, 202, 203, and 204 are connected to the gate terminals of the PMOS transistors TP1, TP2, TP4, and TP8, respectively, and control the conduction of the PMOS transistors TP1, TP2, TP4, and TP8, respectively.

  Further, the NOR gates 211, 212, 213, and 214 receive in common a signal obtained by inverting the data input DQ and the output enable signal OE by the inverter 221, and individually receive a control signal from the output buffer control unit 1. . The outputs of the NOR gates 211, 212, 213, and 214 are connected to the gate terminals of the NMOS transistors TN1, TN2, TN4, and TN8, respectively, and control the conduction of the NMOS transistors TN1, TN2, TN4, and TN8, respectively.

  In the output buffer 2 having such a configuration, the driving capability is changed to 15 levels by changing the combination of conduction of the PMOS transistors TP1, TP2, TP4, and TP8 and the combination of conduction of the NMOS transistors TN1, TN2, TN4, and TN8. You can switch to That is, when the PMOS transistor TP1 or the NMOS transistor TN1 alone is turned on, the minimum driving capability is set, and when all the PMOS transistors or all the NMOS transistors are turned on, the maximum driving capability is set, and the interval between them corresponds to TP1 or TN1. There are 15 levels for engraving with the driving ability.

  From the viewpoint of output impedance, this means that the output impedance can be switched to 15 levels in a reciprocal relationship with the driving capability.

  Therefore, next, the output buffer control unit 1 that controls the conduction of the output buffer 2 will be described.

  The output buffer control unit 1 controls the combination of conduction of the PMOS transistors (TP1, TP2, TP4, TP8) and the conduction of the NMOS transistors (TN1, TN2, TN4, TN8) of the output buffer 2 individually. , A dummy buffer 101 composed of a PMOS transistor and a dummy buffer 111 composed of an NMOS transistor. In addition, in order to control the combination of conduction of the dummy buffer 101, the conduction control unit 10 and the dummy buffer control unit 102 are provided, and the register 105 that records the output of the conduction control unit 10 is provided. On the other hand, in order to control the combination of conduction of the dummy buffer 111, the conduction control unit 11 and the dummy buffer control unit 112 are provided, and a register 115 for recording the output of the conduction control unit 11 is provided.

  Here, the conduction control of the dummy buffer 101 and the dummy buffer 111 will be described. However, the configuration and control method of the circuit for controlling the conduction of the dummy buffer 101 and the circuit for controlling the conduction of the dummy buffer 111 are the same. Here, the description will focus on the circuit that controls the conduction of the dummy buffer 101.

  The dummy buffer 101 includes four PMOS transistors DP1, DP2, DP4, DP8 connected in parallel and having the same configuration as the PMOS transistors TP1, TP2, TP4, TP8 of the output buffer 2.

  The gates of the PMOS transistors DP1, DP2, DP4, and DP8 are connected to the output of the dummy buffer control unit 102, and their conduction is controlled.

  The dummy buffer control unit 102 receives the output of the conduction period control unit 123 and the output of the conduction control unit 10 described later, and inverts the output of the conduction control unit 10 while the output of the conduction period control unit 123 is “1”. And output.

  The conduction control unit 10 includes an up / down counter 103 and a comparator 104.

  The up / down counter 103 is a binary operation counter in which up / down is controlled by the output of the comparator 104 by using 64CLK, which is a divided clock of 64 of the basic clock CLK, as the clock input, and outputs A0, A1, A2, A3 is the output of the conduction control unit 10. Note that A0 is LSB, A3 is MSB, and the output value takes a value between “0001” and “1111”.

  The comparator 104 compares the terminal voltage VQP of the reference resistor RQP having a resistance value corresponding to the impedance value of the transmission line with the output voltage VEP of the dummy buffer 101. Here, the reference resistor RQP is an external resistor connected between the RQP pad and the power supply terminal VDDQ. The terminal voltage VQP is a divided voltage of the reference resistor RQP and the resistor R0P connected in series via the transistor DN0 between the power supply terminal VDDQ and the ground terminal. On the other hand, the output voltage VEP of the dummy buffer 101 is an impedance of the dummy buffer 101 connected in series between the power supply terminal VDDQ and the ground terminal via the transistor DN0 and a divided voltage of the resistor R1P.

  Note that the gate of the transistor DN0 is connected to the output of the conduction period control unit 123. Therefore, the transistor DN0 is turned on only when the output of the conduction period control unit 123 is “1”. Only at this time, VQP and VEP are output and the comparator 104 operates.

  The comparator 104 reduces the drive value of the dummy buffer 101 by decreasing the count value of the up / down counter 103 when VQP is greater than VEP. On the other hand, when VQP is smaller than VEP, the count value of the up / down counter 103 is increased to increase the driving capability of the dummy buffer 101.

  By such an operation of the comparator 104, when the impedance of the dummy buffer 101 is expressed as Zdp, the driving capability of the dummy buffer 101 is adjusted so that Zdp = (R1P / R0P) · RQP. Here, if R1P / R0P = 1, Zdp = RQP, and the impedance of the dummy buffer 101 is equal to the resistance value of the reference resistor RQP.

  Next, the counter 121 that counts the number of “1” included in the data signal DQ during the output enable period (output enable signal OE = “1”), and the period “1” level corresponding to the count value of the counter 121 are set. The conduction period control unit 123 to be output will be described.

  The counter 121 is a counter with an enable terminal using CLK as a clock input, and the output of the AND gate 122 is input to the enable terminal. Since the output enable signal OE and the data signal DQ are input to the AND gate 122, the counter 121 performs a count operation when the data signal DQ becomes “1” during the output enable period (output enable signal OE = “1”). Do. The counter 121 is reset every 64 clocks. Accordingly, the counter 121 is a counter that counts the number of “1” included in the data signal DQ during the 64 clock period when the output is enabled.

  The conduction period control unit 123 has a circuit composed of, for example, a flip-flop, receives the output of the counter 121, and outputs a ‘1’ level corresponding to the count value of the counter 121.

  FIG. 2 shows examples of operation waveforms of the conduction period control unit 123 and the conduction control unit 10. Here, an example is shown in which three ‘1 ’s are included in the data signal DQ during the 64 clock period when the output enable signal OE =‘ 1 ’.

  The counter 121 outputs a count value 3 corresponding to the number of “1” of the data signal DQ at the end of the 64 clock period. In response to this, the conduction period control unit 123 outputs “1” for a period of three clocks. Since the conduction of the dummy buffer 101 is controlled based on the output of the conduction period control unit 123, the cumulative conduction period of the dummy buffer 101 is equal to the cumulative conduction time of the output buffer 2.

  Further, when the output of the conduction period control unit 123 becomes ‘1’, the NMOS transistor DN <b> 0 is turned on and the inputs VQP and VEP are given to the comparator 104, and the comparator 104 outputs the result of comparing VQP and VEP. When the output of the comparator 104 is ‘1’, the count value of the up / down counter 103 is increased, and when the output of the comparator 104 is ‘0’, the count value of the up / down counter 103 is decreased. However, the count value of the up / down counter 103 changes in synchronization with 64 CLK. By such a change in the count value of the up / down counter 103, the combination of conduction of the PMOS transistors DP1, DP2, DP4, DP8 of the dummy buffer 101 is adjusted.

  Outputs A0 to A3 of the up / down counter 103 indicating the result of such adjustment are written in the register 105. The write signal of the register 105 is a signal obtained by inverting the output enable signal OE by the inverter 125. Therefore, when the output enable signal OE changes from “1” to “0”, writing to the register 105 is performed.

  FIG. 3 shows an example of operation waveforms of the register 105.

  When the output enable signal OE = '1', the output of the up / down counter 103 changes in synchronization with 64 CLK. Then, when the output enable signal OE changes from “1” to “0”, the value CNT 1 of the up / down counter 103 immediately before that is written to the register 105. The value CNT1 written in the register 105 is held for a period of “1” next to the output enable signal OE.

  Therefore, the value of CNT1 is output to the outputs P0 to P3 of the register 105 during the period “1” next to the output enable signal OE and is supplied to the PMO transistors TP1, TP2, TP4, and TP8 of the output buffer 2. That is, the result of adjusting the conduction combination of the PMOS transistors DP1, DP2, DP4, and DP8 of the dummy buffer 101 is reflected in the combination of conduction of the PMO transistors TP1, TP2, TP4, and TP8 of the output buffer 2.

  Similarly, the conduction of the dummy buffer 111 composed of the NMOS transistors DN1, DN2, DN4, and DN8 is controlled by the dummy buffer control unit 112. And the conduction control unit 11 including the comparator 114. However, since the NMOS transistors TN1, TN2, TN4, and TN8 of the output buffer 2 are turned on when the data signal DQ is “0”, the dummy buffer control unit 112 is a signal obtained by inverting the output of the conduction period control unit 123 by the inverter 124. Based on the above, the conduction of the NMOS transistors DN1, DN2, DN4, DN8 is controlled.

  The comparator 114 includes a divided voltage VQN of the resistor R0N and the reference resistor RQN connected in series between the power supply terminal VDDQ and the ground terminal via the PMOS transistor DP0, and a power supply terminal VDDQ and the ground terminal via the PMOS transistor DP0. Is compared with the resistor R1N connected in series with the divided voltage VEN of the impedance of the dummy buffer 112 to control up / down of the up / down counter 113. The reference resistor RQN is an external resistor connected to the RQN pad, and its resistance value is set to a value corresponding to the impedance of the transmission line, like the reference resistor RQP.

  The outputs B0 to B3 of the up / down counter 113 having 64 CLK as a clock input are input to the register 115 and are written to the register 115 when the output enable signal OE ‘1’ changes to ‘0’. Based on the outputs N0 to N3 of the register 115, the combination of conduction of the NMOS transistors TN1, TN2, TN4, and TN8 of the output buffer 2 is controlled. However, since the outputs N0 to N3 of the register 115 are connected to the gates of the NMOS transistors TN1, TN2, TN4, and TN8 via the NOR gates 211 to 214, the outputs N0 to N3 of the register 115 are inverted from the inputs B0 to B3. Output the value.

  FIG. 4 shows an example in which the output circuit of this embodiment is applied to a semiconductor device having a plurality of outputs controlled by different output enable signals.

  For the outputs 1 to n whose output enable is controlled by different output enable signals OE1 to OEn, an output buffer controller 1 and an output buffer 2 are provided for each output. As a result, the conduction period of the dummy buffers 101 and 111 in each output buffer control unit 1 is equal to the number of '1' included in each data signal DQ1 to DQn during the period when the output enable signals OE1 to OEn are '1', respectively. Will change accordingly. Therefore, the cumulative conduction period of the output buffer 2 and the cumulative conduction period of the dummy buffers 101 and 111 can be matched for each output.

  The conduction period of the dummy buffer of the output circuit of this embodiment changes in accordance with the number of data signals “1”, that is, the conduction period of the output buffer. Therefore, the deterioration of the driving ability due to the aging of the dummy buffer and the deterioration of the driving ability due to the aging of the output buffer occur equally. Therefore, it is possible to prevent an error from occurring between the driving capacity of the dummy buffer adjusted according to the reference resistance and the driving capacity of the output buffer.

  FIG. 5 is a block diagram showing an example of an output circuit according to the second embodiment of the present invention. In this embodiment, an example of a circuit for controlling a conduction period of a dummy buffer in a semiconductor device having a plurality of output circuits whose output enable is controlled by a common output enable signal is shown.

  The output buffer unit 20 includes n output buffers 2 whose output enable is controlled by a common output enable signal OE, and data DQ1 to DQn are input to each output buffer one by one, and the output is It is a circuit with outputs 1 to n.

  Here, the data DQ1 to DQn are data constituting one piece of information, and the ratio of ‘1’ and ‘0’ has the same tendency among the data DQ1 to DQn. That is, when averaged over a long period of time, the number of “1” included in each of the data DQ1 to DQn can be regarded as equal.

  Therefore, in this embodiment, the output buffer control unit 1 has only one common output buffer 2 of the output buffer unit 20, and the data input (terminal D) includes '1' included in the data DQ1 to DQn. The data indicating the average value of the number of the images is given. As a result, the output buffer control unit 1 makes the internal dummy buffer conductive for a period corresponding to the average number of “1” included in the data DQ1 to DQn.

  Then, an average calculation unit 3 is provided to calculate the average “1” number data of the data DQ1 to DQn given to the output buffer control unit 1. The average calculation unit 3 calculates the average value by counting the number of “1” included in each of the data DQ1 to DQn with a counter, obtaining the sum, and dividing by n.

  In this embodiment, it is not necessary to provide a control unit for each output buffer for a plurality of output buffers, and the number of elements constituting the semiconductor device can be reduced. In addition, it is not necessary to prepare a reference resistor for each output, and an increase in reference resistor connection pins can be suppressed.

1 is a circuit diagram illustrating an example of an output circuit according to a first embodiment of the invention. The wave form diagram which shows operation | movement of the conduction | electrical_connection period control part which concerns on Example 1 of this invention, and a conduction | electrical_connection control part. FIG. 4 is a waveform diagram showing a write timing to a register according to the first embodiment of the present invention. 1 is a diagram illustrating an example of a semiconductor device having a plurality of output circuits according to Embodiment 1 of the invention. FIG. 6 is a block diagram illustrating an example of an output circuit according to a second embodiment of the invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Output buffer control part 2 Output buffer 3 Average calculation part 10, 11 Conduction control part 20 Output buffer part 101, 111 Dummy buffer 102, 112 Dummy buffer control part 103, 113 Up / down counter 104, 114 Comparator 105, 115 Register 121 Counter 122 AND gate 123 conduction period control unit 124, 125, 221 inverter 201, 202, 203, 204 NAND gate 211, 212, 213, 214 NOR gate TP1, TP2, TP4, TP8, DP0, DP1, DP2, DP4, DP8 PMOS Transistors TN1, TN2, TN4, TN8, DN0, DN1, DN2, DN4, DN8 NMOS transistors RQP, RQN Reference resistors R1P, R2P, R1N, R2N resistors

Claims (4)

An output buffer comprising a plurality of PMOS transistors and a plurality of NMOS transistors;
A first dummy buffer comprising a plurality of PMOS transistors having the same configuration as the plurality of PMOS transistors;
A second dummy buffer comprising a plurality of NMOS transistors having the same configuration as the plurality of NMOS transistors;
A first conduction control unit that adjusts a combination of conduction of the plurality of PMOS transistors constituting the first dummy buffer based on a resistance value of a first reference resistor connected to an external terminal;
A second conduction control unit that adjusts a combination of conduction of the plurality of NMOS transistors constituting the second dummy buffer based on a resistance value of a second reference resistor connected to an external terminal;
A first register that records an adjustment result of the first conduction control unit and outputs the recorded data to the plurality of PMOS transistors of the output buffer;
A second register that records an adjustment result of the second conduction control unit and outputs the recorded data to the plurality of NMOS transistors of the output buffer;
A conduction period control unit for controlling a conduction period of the first dummy buffer and the second dummy buffer;
The semiconductor device, wherein the conduction period control unit conducts the first dummy buffer and the second dummy buffer for a period corresponding to a conduction period of the output buffer.   The output buffer has an enable terminal, and the conduction period control unit controls the conduction period of the first dummy buffer and the second dummy buffer during the output enable period of the output buffer, and the output buffer 2. The semiconductor device according to claim 1, wherein recording is performed in the first register and the second register when output is disabled. An output buffer unit having a plurality of output buffers each including a plurality of PMOS transistors and a plurality of NMOS transistors;
A first dummy buffer comprising a plurality of PMOS transistors having the same configuration as the plurality of PMOS transistors;
A second dummy buffer comprising a plurality of NMOS transistors having the same configuration as the plurality of NMOS transistors;
A first conduction control unit for adjusting a conduction combination of the plurality of PMOS transistors constituting the first dummy buffer based on a resistance value of a first reference resistor connected to an external terminal;
A second conduction control unit that adjusts a combination of conduction of the plurality of NMOS transistors constituting the second dummy buffer based on a resistance value of a second reference resistor connected to an external terminal;
A first register that records an adjustment result of the first conduction control unit and outputs the recorded data to the plurality of PMOS transistors of each of the plurality of output buffers;
A second register for recording the adjustment result of the second conduction control unit and outputting the recorded data to the plurality of NMOS transistors of each of the plurality of output buffers;
A conduction period control unit for controlling conduction periods of the first dummy buffer and the second dummy buffer;
An average calculation unit for calculating an average number of data having a conduction level included in the entire data input to each output buffer of the output buffer unit for each predetermined period;
The semiconductor in which the conduction period control unit conducts the first dummy buffer and the second dummy buffer for a period corresponding to an average number of data having the conduction level calculated by the average calculation unit. apparatus.   The plurality of output buffers in the output buffer unit each have an enable terminal to which a common enable signal is input, and when the enable signal is ON, the conduction period control unit performs the first dummy buffer and the second dummy buffer. 4. The semiconductor device according to claim 3, wherein the conduction period of the dummy buffer is controlled, and recording is performed in the first register and the second register when the enable signal is turned OFF.

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