JP2005167185A - Solid-state image pickup device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state image pickup device that can surely transfer signal charges by forming a transferring route to have an ideal potential grade. <P>SOLUTION: The solid-state image pickup device is provided with a first impurity diffusing area 112 of one conductivity formed on a substrate 111 of the other conductivity, a second impurity diffusing area 115 of the other conductivity formed on the surface of the substrate 111, and a source diffusing area 4 formed between the first and second impurity diffusing areas 112 and 115 by diffusing an impurity of one conductivity. The device is also provided with a destination diffusing area 114 formed on the surface of the substrate 111 at a prescribed distance from the source diffusing area 4, by diffusing the impurity of one conductivity and a gate electrode 116 formed on the surface of a substrate 1a between the source and destination diffusing areas 113 and 114 through an insulating film 118. The gate electrode 116 has a projecting section horizontally protruded toward the source diffusing area 4 side by the thickness of the area 4 from its end on the source diffusing area 4 side. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a solid-state imaging device in which a signal charge is reliably transferred with an appropriate potential gradient and a method for manufacturing the same.

  As a solid-state imaging device mounted on a cellular phone or the like, there are a CCD (charge coupled device) type image sensor and a CMOS type image sensor. A CCD type image sensor has excellent image quality, and a CMOS type image sensor has low power consumption and low process cost. In recent years, a MOS type solid-state imaging device of a threshold voltage modulation method that has both high image quality and low power consumption has been proposed.

  In general, an image sensor obtains an image output by arranging sensor cells in a matrix and repeating three states of initialization, accumulation, and readout. In the image sensor disclosed in Patent Document 1, each unit cell includes a photodiode for accumulation, a readout electrode, and a polysilicon electrode 105 for transferring signal charges from the photodiode to the readout electrode.

  FIG. 6 is a schematic cross-sectional view showing the vicinity of the polysilicon electrode of the image sensor disclosed in Patent Document 1. In FIG.

  In the image sensor of FIG. 6, an N-type region 102 of a photodiode and an N-type region 103 for transferring charges are formed in a P-type well 101 of a substrate 100. A shallow P-type layer 104 is formed on the substrate surface on the N-type region 102 of the photodiode. A polysilicon electrode 105 is formed on the surface of the substrate 100 via an insulating layer.

A channel is formed between the N-type regions 102 and 103 in the vicinity of the surface of the substrate 100 according to the voltage applied to the polysilicon electrode 105. As a result, the signal charge from the N-type region 102 of the photodiode is transferred to the N-type region 103 via the channel.
Japanese Patent No. 2723520

  The device of Patent Document 1 is to prevent the N-type region 102 from becoming narrow due to the shallow P-type layer 104 on the surface of the photodiode, and preventing a potential barrier from being easily generated in the bulk portion of the polysilicon electrode 105. The device of Patent Document 1 suppresses the generation of a potential barrier by controlling the length of the protruding portion of the polysilicon electrode 105.

  That is, the apparatus of Patent Document 1 is configured so that the length y of the protruding portion of the polysilicon electrode 105 protruding on the N-type region 102 is made longer than the width x of the N-type region 102. Even in this case, if the width x of the N-type region 102 of the photodiode is relatively short, there is no problem due to the protruding portion.

  However, when the width x of the N-type region 102 of the photodiode is short, the signal charge collection efficiency deteriorates. Therefore, the width x of the N-type region 102 is usually set to a certain length or more in order to improve the collection efficiency of signal charges generated by the photodiode. However, in this case, the device of Patent Document 1 has a problem that the length y of the protruding portion of the polysilicon electrode 105 becomes longer than necessary, and a potential pocket is generated in the region a in FIG.

  Further, since the protruding portion y is longer than necessary, the influence of the applied voltage of the source and drain is reduced in the vicinity of the end of the polysilicon electrode 105, and the change in the potential gradient in the channel is extremely small or vice versa. There was also a problem that a part to be turned might occur.

  The present invention has been made in view of such problems, and an object of the present invention is to provide a solid-state imaging device capable of obtaining an appropriate potential gradient in the transfer path of photogenerated charges and a method for manufacturing the same.

  The solid-state imaging device according to the present invention includes a first impurity diffusion region of the other conductivity type formed on the one conductivity type substrate, and a second impurity diffusion region of the other conductivity type formed on the surface of the substrate. A transfer source diffusion region formed between the first impurity diffusion region and the second impurity diffusion region by diffusing one conductivity type impurity, and the transfer source by diffusing one conductivity type impurity. A transfer destination diffusion region formed on the substrate surface at a predetermined distance from the diffusion region, and an insulating film formed on the substrate surface between the transfer source diffusion region and the transfer destination diffusion region A gate electrode, wherein an end on the transfer source diffusion region side protrudes from the transfer source diffusion region side toward the transfer source diffusion region side in the horizontal direction by the thickness of the transfer source diffusion region And a gate electrode having .

  According to such a configuration, the transfer source diffusion region formed between the first and second impurity diffusion regions is formed with an end portion extending below the gate electrode. The distance from the end of the gate electrode to the end of the transfer source diffusion region (the length of the protruding portion) matches the thickness of the transfer source diffusion region. As a result, potential pockets can be prevented from occurring in the transfer source diffusion region, and the potential gradient of the channel below the gate electrode can be made appropriate, so that signal charges can be reliably transferred from the transfer source diffusion region. can do.

  The solid-state imaging device according to the present invention includes a first impurity diffusion region of the other conductivity type formed on the one conductivity type substrate, and a second impurity diffusion of the other conductivity type formed on the surface of the substrate. A region, a source diffusion region formed between the first impurity diffusion region and the second impurity diffusion region by diffusing one conductivity type impurity, and diffusing the one conductivity type impurity A transfer destination diffusion region formed on the substrate surface at a predetermined distance from the transfer source diffusion region, and an insulating film formed on the substrate surface between the transfer source diffusion region and the transfer destination diffusion region A gate electrode having a sidewall on a side surface, wherein the end of the side wall on the transfer source diffusion region side is horizontally equal to the thickness of the transfer source diffusion region from the end of the transfer source diffusion region. Projecting toward the source diffusion area Characterized by comprising a structured gate electrode.

  According to such a configuration, the transfer source diffusion region formed between the first and second impurity diffusion regions is formed with an end portion extending below the gate electrode and the sidewall. The distance from the end of the sidewall to the end of the transfer source diffusion region (the length of the protruding portion) matches the thickness of the transfer source diffusion region. As a result, potential pockets can be prevented from being generated in the transfer source diffusion region, and the potential gradient of the channel below the gate electrode including the side wall can be made appropriate. Signal charge can be transferred.

  In addition, a photoelectric conversion element that is formed on the substrate and generates a photo-generated charge according to incident light, holds the photo-generated charge from the photoelectric conversion element, and the threshold voltage of the channel is determined by the held photo-generated charge. And a modulation transistor that outputs a pixel signal based on the photogenerated charge, and the transfer source diffusion region is formed in the photoelectric conversion element formation region on the substrate and is generated by the photoelectric conversion element It is characterized in that it constitutes a transfer path for photogenerated charges.

  According to such a configuration, the photo-generated charges generated by the photoelectric conversion element are accumulated in the transfer source diffusion region. The photo-generated charges accumulated in the transfer source diffusion region are transferred from the transfer source diffusion region to the transfer destination diffusion region in accordance with the voltage applied to the gate electrode. In this case, since the length of the protrusion matches the thickness of the transfer destination diffusion region, the potential gradient between the transfer transfer source diffusion region and the transfer destination diffusion region is appropriate, for example, uniform. And it can be made into a sufficient size. This enables reliable transfer of photogenerated charges from the transfer source diffusion region.

  In addition, a photoelectric conversion element that is formed on the substrate and generates a photo-generated charge according to incident light, holds the photo-generated charge from the photoelectric conversion element, and the threshold voltage of the channel is determined by the held photo-generated charge. And a modulation transistor that outputs a pixel signal based on the photogenerated charge, and the transfer source diffusion region is formed in the modulation transistor forming region on the substrate to hold the photogenerated charge And a transfer path for the photogenerated charges.

  According to such a configuration, the photo-generated charges generated by the photoelectric conversion element are held in the transfer source diffusion region formed in the modulation transistor formation region. The modulation transistor outputs an output corresponding to the photo-generated charge held in the transfer source diffusion region. At the time of clearing or the like, photogenerated charges are discharged from the transfer source diffusion region. In this case, since the length of the projecting portion matches the thickness of the transfer destination diffusion region, the potential gradient from the transfer transfer source diffusion region is made appropriate, for example, uniform and sufficient. Therefore, it is possible to reliably discharge the photogenerated charges from the transfer source diffusion region.

  The transfer source diffusion region is characterized in that a distance between the interface with the first impurity diffusion region and the interface with the second impurity diffusion region is constant.

  According to such a configuration, it is possible to more reliably prevent a potential pocket from being generated in the transfer source diffusion region, and to make the potential gradient of the channel below the gate electrode including the sidewall more appropriate. Can do.

  In the method for manufacturing a solid-state imaging device according to the present invention, a first diffusion step of forming an impurity diffusion region of the other conductivity type on the one conductivity type substrate, and a gate electrode is formed on the substrate surface via an insulating film. And a step of diffusing impurities of one conductivity type in a self-aligning manner using the gate electrode as a mask to form a transfer source diffusion region on the impurity diffusion region of the other conductivity type, wherein the transfer of the gate electrode The one conductivity type impurity is diffused in such a manner that an end portion on the source diffusion region side projects in the horizontal direction from the end portion of the transfer source diffusion region to the transfer source diffusion region side by the thickness of the transfer source diffusion region. And a second diffusion step to be performed.

According to such a configuration, the impurity diffusion region of the other conductivity type is formed on the substrate of one conductivity type by the first diffusion process. Next, a gate electrode is formed on the substrate surface via an insulating film.
Next, in the second diffusion step, a transfer diffusion region is formed on the other conductivity type impurity diffusion region by diffusing one conductivity type impurity in a self-aligning manner using the gate electrode as a mask. In this case, the one end of the gate electrode on the side of the transfer source diffusion region protrudes in the horizontal direction from the end of the transfer source diffusion region to the transfer source diffusion region side by the thickness of the transfer source diffusion region. Diffuse mold impurities. As a result, potential pockets can be prevented from occurring in the transfer source diffusion region, and the potential gradient of the channel below the gate electrode can be made appropriate, so that signal charges can be reliably transferred from the transfer source diffusion region. can do.

  The method for manufacturing a solid-state imaging device according to the present invention includes a first diffusion step of forming an impurity diffusion region of the other conductivity type on a substrate of one conductivity type, and a gate electrode via an insulating film on the substrate surface. A step of forming, a second diffusion step of diffusing impurities of one conductivity type in a self-aligning manner using the gate electrode as a mask to form a transfer source diffusion region on the impurity diffusion region of the other conductivity type, and the gate Forming a sidewall on the side surface of the electrode, wherein the second diffusion step is such that the end of the sidewall on the side of the transfer source diffusion region is in the horizontal direction and the end of the transfer source diffusion region The one conductivity type impurity is diffused so as to protrude toward the transfer source diffusion region by the thickness of the transfer source diffusion region.

  According to such a configuration, in the second diffusion step, the one conductivity type impurity is diffused in a self-aligning manner using the gate electrode including the sidewall as a mask, so that the transfer source is transferred onto the other conductivity type impurity diffusion region. A diffusion region is formed. In this case, the end of the gate electrode including the side wall on the side of the transfer source diffusion region protrudes in the horizontal direction from the end of the transfer source diffusion region to the transfer source diffusion region by the thickness of the transfer source diffusion region. As such, impurities of one conductivity type are diffused. As a result, potential pockets can be prevented from occurring in the transfer source diffusion region, and the potential gradient of the channel below the gate electrode can be made appropriate, so that signal charges can be reliably transferred from the transfer source diffusion region. can do.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a cross-sectional view schematically showing a cross-sectional shape of the solid-state imaging device according to the first embodiment of the present invention.

  The solid-state imaging device according to the present embodiment has the other conductivity type well 112 on the one conductivity type substrate 111. The well 112 is formed with an impurity diffusion region (hereinafter referred to as a transfer source diffusion region) 113 of one conductivity type that constitutes a photodiode. The transfer source diffusion region 113 is for holding and transferring photo-generated charges generated by the photoelectric conversion action of the photodiode.

  In the photodiode formation region on the surface of the substrate 111, an impurity diffusion region 115 of the other conductivity type is formed on the impurity diffusion region 113. The impurity diffusion region 115 functions as a pinning layer. The impurity diffusion region 115 is formed at a shallow and high concentration by low energy ion implantation.

  An impurity diffusion region (hereinafter referred to as a transfer destination diffusion region) 114 that is a transfer destination of photogenerated charges generated in the photodiode is formed in the vicinity of the surface of the substrate 111 that is separated from the impurity diffusion region 113 by a predetermined distance. A gate electrode 116 is formed on the surface of the substrate 111 between the opposing ends of the diffusion regions 113 and 114 via an insulating film 118. Sidewalls 117 are formed on the side surfaces of the gate electrode 116.

  By applying an appropriate voltage to the gate electrode 116, a channel 119 is formed between the impurity diffusion regions 113 and 114 near the surface of the substrate 111. The photo-generated charges generated in the photodiode are transferred from the impurity diffusion region 113 to the impurity diffusion region 114 via the channel 119 below the gate electrode 116.

  In this embodiment, if the thickness of the transfer source diffusion region 113 in the substrate depth direction is d, the horizontal dimension of the transfer source diffusion region 113 formed below the gate electrode 116 including the sidewall 117, that is, the gate The length from the end of the transfer source diffusion region 113 below the electrode 116 to the lower side of the edge of the side wall 117 is also set to substantially d. In other words, the gate electrode 116 including the sidewall 117 has a portion (projecting portion) whose length overlaps in the horizontal direction on the transfer source diffusion region 113 by d.

  In the embodiment configured as described above, the gate electrode including the sidewall 117 on the transfer source diffusion region 113 even when the transfer source diffusion region 113 has a sufficient thickness d in the depth direction. The length of the protruding portion 116 does not become longer than necessary. Thereby, it is possible to prevent a potential pocket from being generated in the transfer source diffusion region 113. In addition, since the length of the protruding portion of the gate electrode 116 including the sidewall 117 on the transfer source diffusion region 113 is relatively small, the channel 119 below the end of the gate electrode 116 has an appropriate potential gradient, for example, A substantially uniform and sufficient inclination can be set.

  In FIG. 1, the width of the transfer source diffusion region 113 below the gate electrode 116 including the sidewall 117 is set so that the distance between the junction interface with the diffusion region 115 and the junction interface with the well 112 is always equal. Is formed. In this case, the potential gradient from the transfer source diffusion region 113 to the transfer destination diffusion region 114 can be made more appropriate.

  The transfer source diffusion region 113 and the diffusion region 115 can be formed in a self-aligned manner using the gate electrode 116. Thereby, impurity diffusion into a desired region is possible without considering mask displacement or the like. Further, in order to diffuse the transfer source diffusion region 113 to below the gate electrode 116, ion implantation from an oblique direction is performed when the transfer source diffusion region 113 is formed.

  As described above, in the present embodiment, a potential pocket is prevented from being generated, and an appropriate potential gradient, for example, a substantially uniform and sufficient gradient, is provided from the transfer source diffusion region 113 to the transfer destination diffusion region 114. A potential gradient can be set, and signal charges can be transferred smoothly.

  It is obvious that this embodiment can be applied to all devices for transferring charges, such as charge reading transistors and charge discharging transistors.

  2 is a cross-sectional view showing a cross-sectional shape of the solid-state imaging device according to the present embodiment, FIG. 3 is a plan view showing a planar shape of one sensor cell of the solid-state imaging device according to the present embodiment, and FIGS. 4 and 5 are elements. It is process drawing for demonstrating this manufacturing method. This embodiment shows an example in which the present invention is applied to a specific solid-state imaging device.

<Structure of sensor cell>
As will be described later, the solid-state imaging device according to the present embodiment has a sensor cell array in which sensor cells as unit pixels are arranged in a matrix. Each sensor cell accumulates photogenerated charges generated according to incident light and outputs a pixel signal at a level based on the accumulated photogenerated charges. An image signal of one screen can be obtained by arranging the sensor cells in a matrix.

  First, the structure of each sensor cell will be described with reference to FIG. FIG. 3 shows one sensor cell. One sensor cell is a range indicated by a broken line in FIG. This embodiment shows an example in which holes are used as photogenerated charges. Even in the case where electrons are used as the photo-generated charges, the same configuration is possible. FIG. 2 shows a cross-sectional structure of the cell cut along the line A-A ′ of FIG. 3.

  As shown in the plan view of FIG. 3, a photodiode PD and a modulation transistor TM are provided adjacent to each other in a sensor cell 3 which is a unit pixel. As the modulation transistor TM, for example, an N-channel depletion MOS transistor is used. The unit pixel has a substantially rectangular shape, and each side thereof is inclined obliquely with respect to the column or row direction of the sensor cell array.

  In the photodiode PD formation region which is a photoelectric conversion element formation region, an opening region 2 is formed on the surface of the substrate 1, and a P-type well wider than the opening region 2 is formed at a relatively shallow position on the surface of the substrate 1. A well (hereinafter referred to as an accumulation well) 4 for accumulating photogenerated charges generated by the photoelectric conversion element is formed. The accumulation well 4 corresponds to the transfer source diffusion region 113 in FIG. A well (hereinafter referred to as a P-type well) that is spaced apart from the storage well 4 by a predetermined distance and controls the modulation transistor by transferring photogenerated charges stored in the storage well 4 to the modulation transistor TM formation region. (Referred to as a modulation well). The modulation well 5 corresponds to the transfer destination diffusion region 114 in FIG. 1 on the modulation well 4 side, and corresponds to the transfer source diffusion region 113 in FIG. 1 on the discharge and OD contact regions 15 and 11 described later.

On the modulation well 5, a ring-shaped portion (hereinafter referred to as a ring gate portion) 6 a of a gate (ring transfer gate) 6 having a ring shape at one end and a linear shape at the other end is formed on the surface of the substrate 1. A source region 7 which is a high-concentration N-type region is formed in a region near the surface of the substrate 1 in the central opening of the ring gate portion 6a. An N-type drain region 8 is formed around the ring gate portion 6a. An N ⁺ -layer drain contact region 9 is formed near the surface of the substrate 1 at a predetermined position of the drain region 8.

The modulation well 5 controls the threshold voltage of the channel of the modulation transistor TM.
In the modulation well 5, a carrier pocket 10 which is a P-type high concentration region is formed below the ring gate portion 6a. The modulation transistor TM is configured by the modulation well 5, the ring gate portion 6a, the source region 7 and the drain region 8, and the threshold voltage of the channel changes according to the electric charge accumulated in the modulation well 5 (carrier pocket 10). It is supposed to be.

  A depletion region (not shown) is formed in a boundary region between an N-type well 21 and a P-type accumulation well 4 (described later) formed on the substrate 1 below the opening region 2 of the photodiode PD. Then, photogenerated charges are generated by the light incident through the opening region 2. The generated photogenerated charges are stored in the storage well 4.

  The charges accumulated in the accumulation well 4 are transferred to the modulation well 5 and held in the carrier pocket 10. As a result, the source potential of the modulation transistor TM is in accordance with the amount of charge transferred to the modulation well 5, that is, the incident light to the photodiode PD.

  On the surface of the substrate 1 in the vicinity of the storage well 4, unnecessary charges (hereinafter referred to as unnecessary charges) that do not contribute to the image signal including charges overflowing from the storage well 4 among the photogenerated charges stored in the storage well 4 are discharged. A contact region (hereinafter referred to as an OD contact region) 11 is formed by a high concentration P-type diffusion layer. On the surface of the substrate 1 between the OD contact region 11 and the storage well 4 region, a path for unnecessary charges including charges overflowed between the OD contact region 11 and the storage well 4 region (hereinafter referred to as an unnecessary charge discharge path). A lateral overflow drain (hereinafter referred to as LOD) transistor TL LOD gate 12 for forming RL is formed. One end of the LOD gate 12 hangs over the region of the storage well 4 in plan view.

  By providing the LOD transistor TL as an unnecessary charge discharge control element, the potential barrier between the OD contact region 11 and the accumulation well 4 is controlled, and unnecessary charges are transferred from the OD contact region 11 to the substrate via the LOD transistor TL. Can be discharged through the wiring.

  A transfer transistor TT as a transfer control element is formed between the accumulation well 4 and the modulation well 5. The gate of the transfer transistor TT is constituted by a linear portion (hereinafter referred to as a transfer gate portion) 6b of the ring transfer gate 6. The transfer gate portion 6b is formed on the surface of the substrate 1 in the path between the accumulation well 4 and the modulation well 5 (hereinafter simply referred to as a transfer path) RT. The transfer transistor TT can control the potential barrier of the transfer path RT to control the transfer of charge from the accumulation well 4 to the modulation well 5.

  Further, in the present embodiment, a contact region for discharging residual charges (hereinafter referred to as discharge) for discharging charges remaining in the modulation well (hereinafter referred to as residual charges) on the substrate surface in the vicinity of the modulation well 5. 15 (referred to as a contact region) is formed by a high-concentration P-type diffusion layer. On the surface of the substrate 1 between the discharge contact region 15 and the modulation well 5 region, a potential barrier of RC (hereinafter referred to as residual charge discharge route) RC between the discharge contact region 15 and the modulation well 5 region. A clear gate 14 of the clear transistor TC is formed as a residual charge discharge control element for controlling the above. One end of the clear gate 14 hangs over the region of the modulation well 5 in plan view.

  Note that each of the LOD transistor TL, the transfer transistor TT, and the clear transistor TC moves the photogenerated charges in the horizontal direction (lateral direction) of the substrate.

<Sensor cell cross section>
Furthermore, with reference to FIG. 2, the cross-sectional structure of the sensor cell 3 is demonstrated in detail. In FIG. 2, the subscripts-and + of N and P indicate the state from the lighter portion (subscript ---) to the darker portion (subscript +++) depending on the number.

  FIG. 2 shows a cross section of one unit pixel (cell). One cell has a photodiode PD formation region and a modulation transistor TM formation region. An isolation region 22 is provided between the photodiode PD formation region and the modulation transistor TM formation region in the cell and between adjacent cells.

At a relatively deep position of the substrate 1, an N ⁻ N type well 21 is formed over the entire area of the P type substrate 1a. An isolation region 22 for element isolation by an N ⁻ layer is formed on the N-type well 21. On the N-type well 21, a P ⁻ layer is formed over the entire element except for the isolation region 22.

The P ⁻ layer in the photodiode PD formation region is the accumulation well 4. The P ⁻ layer in the modulation transistor TM formation region is the modulation well 5. In the modulation well 5, a carrier pocket 10 is formed by P ^- diffusion.

In the isolation region 22 between the photodiode PD formation region and the modulation transistor TM formation region in the cell, the transfer transistor TT is formed on the substrate surface side. The transfer transistor TT is formed by forming a P ^--- diffusion layer 24 constituting a channel on the substrate surface and forming a transfer gate portion 6b on the substrate surface via a gate insulating film 25. The P ^--- diffusion layer 24 is connected to the storage well 4 and the modulation well 5 to form a transfer path RT, and the potential barrier of the transfer path RT is controlled according to the voltage applied to the transfer gate portion 6b. .

In the modulation transistor TM formation region, a ring gate portion 6a is formed on the substrate surface via a gate insulating film 25, and an N 2 ⁻ diffusion layer 27 constituting a channel is formed on the substrate surface below the ring gate portion 6a. . An N ⁺⁺ diffusion layer is formed on the substrate surface at the center of the ring gate portion 6a to constitute the source region 7. Further, an N ⁺ diffusion layer is formed on the surface of the substrate around the ring gate portion 6 a to constitute the drain region 8. The N 2 ⁻ diffusion layer 27 constituting the channel is connected to the source region 7 and the drain region 8.

In the isolation region 22 between the photodiode PD formation region and the modulation transistor TM formation region of adjacent cells, the discharge contact region 15 and the OD contact region 11 are formed on the substrate surface side. In the present embodiment, the discharge contact region 15 and the OD contact region 11 are shared, but they may be configured separately. The discharge and OD contact regions 15, 11 are obtained by forming a P ⁺⁺ diffusion layer on the substrate surface.

A clear transistor TC is formed on the substrate surface side between the modulation transistor TM formation region and the discharge and OD contact regions 15 and 11. In the clear transistor TC, a P ^--- diffusion layer 28 constituting a channel is formed on the substrate surface between the modulation transistor TM formation region and the discharge and OD contact regions 15 and 11, and the gate insulating film 25 is formed on the substrate surface. And a clear gate 14 is formed. This P ^--- diffusion layer 28 is connected to the modulation well 5 and the discharge and OD contact regions 15 and 11 to form a residual charge discharge path RC, and this residual charge discharge path according to the voltage applied to the clear gate 14. The RC potential barrier is controlled.

An LOD transistor TL is formed on the substrate surface side between the photodiode PD formation region and the discharge and OD contact regions 15 and 11. In the LOD transistor TL, a P ^--- diffusion layer 30 constituting a channel is formed on the substrate surface between the photodiode PD formation region and the discharge and OD contact regions 15 and 11, and a gate insulating film 25 is formed on the substrate surface. The LOD gate 12 is formed through the configuration. This P ^--- diffusion layer 30 is connected to the storage well 4 and the discharge and OD contact regions 15 and 11 to form an unnecessary charge discharge path RL, and this unnecessary charge discharge path RL according to the voltage applied to the LOD gate 12. The potential barrier is controlled.

An N ⁺ diffusion layer 32 as a pinning layer is formed on the substrate surface side of the photodiode PD formation region. Further, the clear gate 14, the LOD gate 12, the transfer gate portion 6b, the discharge and OD contact regions 15 and 11, and the source region 7 are electrically connected to a wiring (not shown) formed on the substrate.

  Side walls 12 a and 12 b are formed at both ends of the LOD gate 12. In the present embodiment, when the thickness of the accumulation well 4 in the substrate depth direction is d1, the end of the sidewall 12a on the accumulation well 4 side extends in the horizontal direction from the end of the accumulation well 4 below the LOD gate 12. It is formed so as to protrude toward the accumulation well 4 by about d1.

  Side walls are formed at both ends of the ring transfer gate 6. In the present embodiment, the end portion of the side wall 6c on the transfer gate portion 6b side is formed to protrude from the end portion of the accumulation well 4 below the transfer gate portion 6b to the accumulation well 4 side in the horizontal direction by about d1. Yes.

  Side walls 14 a and 14 b are formed at both ends of the clear gate 14. Assuming that the thickness of the modulation well 5 in the substrate depth direction is d2, in this embodiment, the end of the side wall 14b on the modulation well 5 side is the end of the modulation well 5 below the clear gate 14. And projecting toward the modulation well 5 side by approximately d2 in the horizontal direction.

<Action>
In the embodiment configured as described above, the photodiode PD generates a photo-generated charge (hole) based on the light incident through the opening region 2. The photo-generated charges generated in the photodiode PD are accumulated in the accumulation well 4 that is a transfer source diffusion region.

The photogenerated charges in the storage well 4 are transferred to the modulation well 5 which is the transfer destination diffusion region by the transfer transistor TT. The storage well 4 is formed below the transfer gate portion 6b, and the end portion of the side wall 6c on the transfer gate portion 6b side is similar to the relationship between the transfer source diffusion region 113 and the gate electrode 116 including the sidewall in FIG. Is formed so as to protrude from the end of the storage well 4 below the transfer gate portion 6b toward the storage well 4 by the thickness of the storage well 4 in the horizontal direction. Thereby, it is possible to prevent a potential pocket from being formed in the storage well 4 during transfer of photogenerated charges from the storage well 4 to the modulation well 5. Further, since the potential gradient in the P ^--- diffusion layer 24 constituting the channel immediately below the transfer gate portion 6b can be set to an appropriate one, for example, a substantially uniform and sufficient gradient, all of the photogenerated charges can be surely obtained. Can be transferred to the modulation well 5.

The threshold voltage of the modulation transistor TM is changed by the photogenerated charge held in the modulation well 5, and an output corresponding to the photogenerated charge is obtained from the source region 7 of the modulation transistor TM.
At the time of clearing, the photo-generated charges held in the modulation well 5 are discharged and transferred to the OD contact regions 15 and 11 through the clear transistor TC and discharged.

  Also in this case, the relationship between the modulation well 5 and the clear gate 14 including the sidewall 14b is the same as the relationship between the transfer source diffusion region 113 and the gate electrode 116 including the sidewall in FIG. All of the photogenerated charges held in the well 5 can be transferred and discharged.

  Further, unnecessary photogenerated charges among the photogenerated charges accumulated in the accumulation well 4 of the photodiode PD are discharged and discharged to the OD contact regions 15 and 11 using the LOD transistor TL. Also in this case, since the relationship between the storage well 4 and the LOD gate 12 including the sidewall 12a is the same as the relationship between the transfer source diffusion region 113 and the gate electrode 116 including the sidewall in FIG. All of the photo-generated charges held in can be transferred and discharged.

<Process>
Next, a method for manufacturing the element will be described with reference to the process diagrams of FIGS. 4 and 5 show cross sections taken along the line AA ′ in FIG. 4 and 5, the frame on the substrate represents a mask.

First, a sacrificial oxide film (not shown) is formed on the surface of the prepared P substrate 1. Next, as shown in FIG. 4A, phosphorus (P31 +) ions are implanted so that the peak position is about 1.5 μm and the peak impurity concentration is 8 × 10 ¹⁶ cm ⁻³ . As a result, as shown in FIG. 4A, an N ⁻ N-type well 21 is formed at a relatively deep position.

Next, as shown in FIG. 4B, an isolation region 22 (N ⁻ layer) for element isolation is formed. That is, the isolation region 22 is formed in all regions between the storage well 4 and the modulation well 5 in the own cell and between adjacent cells. In this isolation region 22, for example, phosphorus (P31 +) ions are implanted through the resist 22 a so that the peak position is about 0.5 μm and the peak impurity concentration is 2 × 10 ¹⁷ cm ⁻³ .

Next, as shown in FIG. 4C, on the surface of the formed isolation region 22, P ^--- layers 24, 28, and 30 serving as channel dopes of the modulation transistor TM, the LOD transistor TL, and the clear transistor TC are formed. Form. In this channel dope, boron (B11 +) ions are implanted so as to have a peak position of about 0.03 μm and a peak impurity concentration of 4.5 × 10 ¹⁷ cm ^−3, and at this time, they are formed over the entire surface of the isolation region 22. .

Next, as shown in FIG. 4D, a carrier pocket 10 made of a dense P ⁻ diffusion layer is formed at a position corresponding to the P ⁻ layer 23 (modulation well 5) below the ring gate portion 6a. The carrier pocket 10 is formed, for example, by implanting boron (B11 +) ions at a peak position of about 0.1 μm and a peak impurity concentration of 1.5 × 10 ¹⁷ cm ⁻³ using the resist 10a. Further, an N ⁻ layer 27 for obtaining a channel of the modulation transistor TM is formed in the vicinity of the substrate surface on the carrier pocket 10. This N 2 ⁻ layer 27 is formed, for example, by ion implantation of arsenic (As75 +) ions so that the peak position is about 0.05 μm and the peak impurity concentration is 2 × 10 ¹⁷ cm ⁻³ .

  Next, after removing the sacrificial oxide film on the substrate surface, as shown in FIG. 4E, a gate insulating film 25 having a thickness of about 30 nm is formed on the substrate surface by thermal oxidation. Next, a polysilicon layer having a thickness of 250 nm and serving as the gate electrode of each transistor is deposited on the entire surface of the substrate 1.

  Next, the polysilicon layer on the gate insulating film 25 is patterned according to the modulation transistor TM formation region, the transfer transistor TT formation region, the LOD transistor TL formation region, and the clear transistor TC formation region, and the ring gate portion 6a, transfer gate The part 6b, the LOD gate 12 and the clear gate 14 are formed.

Next, as shown in FIG. 5A, a storage well 4 that is a P ⁻ layer is formed in the photodiode formation region PD on the N-type well 21. For example, boron (B11 +) ions are implanted through the resist 4a so that the peak position is about 0.2 μm and the peak impurity concentration is 1 × 10 ¹⁷ cm ⁻³ , thereby forming the accumulation well 4. Similarly, a modulation well 5 that is a P ⁻ layer is formed in the photodiode formation region PD on the N-type well 21.

  In the present embodiment, ion implantation for forming the storage well 4 and the modulation well 5 is performed in a self-aligning manner using the gates 6, 12, and 14. Further, as shown by an arrow in FIG. 5A, ion implantation from an oblique direction is performed.

  As a result, both end portions of the storage well 4 can be formed so as to sink under the ring transfer gate 6 and under the LOD gate 12, respectively. Further, the modulation well 5 can be formed so that the end on the clear gate 14 side is buried under the clear gate 14. In this case, the transfer path (portion connected to the channel from the transfer source) can be expanded by minimizing the diffusion under each gate.

  Next, as shown in FIG. 5B, the sidewalls 6c, 12a, 12b, 14a, and so on are respectively formed on the gates so as to cover the oxide films on the ring gate portion 6a, the LOD gate 12, and the clear gate 14. 14b is formed.

  In the present embodiment, the end portion of the side wall 6c on the transfer gate portion 6b side protrudes from the end portion of the accumulation well 4 below the transfer gate portion 6b toward the accumulation well 4 in the horizontal direction by the thickness of the accumulation well 4. To be formed. Further, the end portion of the sidewall 12a of the LOD gate 12 is formed so as to protrude from the end portion of the accumulation well 4 below the LOD gate 12 toward the accumulation well 4 in the horizontal direction by the thickness of the accumulation well 4. Yes. Further, the end of the side wall 14b of the clear gate 14 is formed so as to protrude from the end of the modulation well 5 below the clear gate 14 to the modulation well 5 in the horizontal direction by the thickness of the modulation well 5. It has become.

Next, as shown in FIG. 5C, the drain region 8 is formed on the substrate surface, and the resist 32a is used to form an N ⁺ diffusion layer 32 as a pinning layer on the substrate surface side of the photodiode PD formation region. Form.

Next, as shown in FIG. 5D, in order to form the discharge contact region 15 and the OD contact region 11 connected to the channel region of the clear transistor TC at a position adjacent to the clear gate 14, Forms a dense P ⁺⁺ layer. This P ⁺⁺ layer is formed by implanting, for example, boron (B11 +) ions so that the peak position is about 0.1 μm and the peak impurity concentration is 1 × 10 ¹⁸ cm ⁻³ using the resist 11a.

Next, as shown in FIG. 5E, N ⁺⁺ impurity implantation is performed at a position corresponding to the source region 7 through a resist 7a to form the source region 7.

  In the present embodiment, the discharge contact region 15 and the OD contact region 11 are combined, but the discharge contact region 15 and the OD contact region 11 may be provided separately.

<Effect of Embodiment>
As described above, in the present embodiment, the transfer path in the portion connecting from the transfer source diffusion region to the channel under the gate is widened, so that a potential barrier can be prevented from being formed. Further, since the transfer source diffusion region having the same thickness as the length of the protruding portion of the gate including the sidewall is formed, no potential pocket is formed. As a result, the transfer path from the transfer source diffusion region to the transfer destination diffusion region can be set to a substantially ideal potential gradient, and the photo-generated charges can be reliably transferred. As a result, the image sensor according to the present embodiment can exhibit an excellent afterimage prevention effect.

  In each of the above embodiments, the example in which the side wall is formed on the gate electrode has been described. However, the present invention can be applied to the case where the side wall is not formed. The end portion may be formed so as to protrude in the horizontal direction from the end portion of the transfer source diffusion region below the gate electrode to the transfer source diffusion region side by the thickness of the transfer source diffusion region.

1 is a cross-sectional view schematically showing a cross-sectional shape of a solid-state imaging device according to a first embodiment of the present invention. Sectional drawing which shows the cross-sectional shape of the solid-state imaging device concerning this Embodiment. The top view which shows the planar shape of 1 sensor cell of the solid-state imaging device which concerns on this Embodiment. Process drawing for demonstrating the manufacturing method of an element. Process drawing for demonstrating the manufacturing method of an element. The typical sectional view showing the polysilicon electrode neighborhood in a conventional example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 111 ... Substrate, 112 ... Well, 113, 114 ... One conductivity type impurity diffusion region, 115 ... The other conductivity type impurity diffusion region, 116 ... Gate electrode, 117 ... Side wall, 119 ... Channel.

Claims (7)

A first impurity diffusion region of the other conductivity type formed on the one conductivity type substrate;
A second impurity diffusion region of the other conductivity type formed on the surface of the substrate;
On the other hand, a source diffusion region formed between the first impurity diffusion region and the second impurity diffusion region by diffusing conductivity-type impurities;
On the other hand, a transfer destination diffusion region formed on the substrate surface at a predetermined distance from the transfer source diffusion region by diffusing conductivity type impurities,
A gate electrode formed on the substrate surface between the transfer source diffusion region and the transfer destination diffusion region via an insulating film, and an end portion on the transfer source diffusion region side in the horizontal direction, the transfer A solid-state imaging device comprising: a gate electrode having a protruding portion protruding from the end of the original diffusion region toward the transfer source diffusion region by the thickness of the transfer source diffusion region. A first impurity diffusion region of the other conductivity type formed on the one conductivity type substrate;
A second impurity diffusion region of the other conductivity type formed on the surface of the substrate;
On the other hand, a source diffusion region formed between the first impurity diffusion region and the second impurity diffusion region by diffusing conductivity-type impurities;
On the other hand, a transfer destination diffusion region formed on the substrate surface at a predetermined distance from the transfer source diffusion region by diffusing conductivity type impurities,
A gate electrode formed on the substrate surface between the transfer source diffusion region and the transfer destination diffusion region via an insulating film and having a side wall on the side surface; an end of the side wall on the transfer source diffusion region side; A solid-state imaging device comprising: a gate electrode configured to protrude in a horizontal direction from an end portion of the transfer source diffusion region to the transfer source diffusion region side by a thickness of the transfer source diffusion region; apparatus. A photoelectric conversion element that is formed on the substrate and generates photogenerated charges according to incident light;
A modulation transistor that holds the photogenerated charge from the photoelectric conversion element, controls a threshold voltage of a channel by the held photogenerated charge, and outputs a pixel signal based on the photogenerated charge;
3. The transfer source diffusion region is formed in a photoelectric conversion element formation region on the substrate, and constitutes a transfer path for photogenerated charges generated by the photoelectric conversion element. The solid-state imaging device described in one side. A photoelectric conversion element that is formed on the substrate and generates photogenerated charges according to incident light;
A modulation transistor that holds the photogenerated charge from the photoelectric conversion element, controls a threshold voltage of a channel by the held photogenerated charge, and outputs a pixel signal based on the photogenerated charge;
The transfer source diffusion region is formed in a modulation transistor formation region on the substrate, and holds the photogenerated charge and constitutes a transfer path of the photogenerated charge. A solid-state imaging device according to any one of the above.   3. The transfer source diffusion region according to claim 1, wherein a distance between the interface with the first impurity diffusion region and the interface with the second impurity diffusion region is constant. The solid-state imaging device described in one side. A first diffusion step of forming an impurity diffusion region of the other conductivity type on the one conductivity type substrate;
Forming a gate electrode on the substrate surface via an insulating film;
A step of diffusing impurities of one conductivity type in a self-aligning manner using the gate electrode as a mask to form a transfer source diffusion region on the impurity diffusion region of the other conductivity type, wherein the transfer source diffusion region of the gate electrode A second impurity that diffuses the one-conductivity type impurity in a horizontal direction so that the end of the transfer source diffusion region protrudes from the end of the transfer source diffusion region by the thickness of the transfer source diffusion region in the horizontal direction. A solid-state imaging device manufacturing method comprising: A first diffusion step of forming an impurity diffusion region of the other conductivity type on the one conductivity type substrate;
Forming a gate electrode on the substrate surface via an insulating film;
A second diffusion step of diffusing impurities of one conductivity type in a self-aligning manner using the gate electrode as a mask to form a transfer source diffusion region on the impurity diffusion region of the other conductivity type;
Forming a sidewall on a side surface of the gate electrode,
In the second diffusion step, the end of the sidewall on the side of the transfer source diffusion region is in the horizontal direction from the end of the transfer source diffusion region by the thickness of the transfer source diffusion region. A method of manufacturing a solid-state imaging device, wherein the one conductivity type impurity is diffused so as to protrude to the side.

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