JP2005167124A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of precisely controlling the thickness of a dielectric film to have a highly precise electrostatic capacity value in a semiconductor device having a MIM capacitive element. <P>SOLUTION: After a lower electrode and a second silicon oxide film are formed on a first silicon oxide film, the second silicon oxide film is selectively etched to form a capacitance formation region and a through hole. Then, after reverse sputter etching, Ti and TiN are formed continuously as a contact layer, and further a dielectric film is formed on the capacitance formation region. Then, a tungsten layer is formed over the entire surface without implementing the reverse sputter etching, and a resist film is formed in the capacitance formation region, which is used to etch the tungsten layer. Further, a metal layer is formed over the entire surface, and upper electrode and lower electrode lead wirings are formed. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a structure of a semiconductor device in which a metal-insulating film-metal (MIM) capacitor element is mounted on a semiconductor substrate, and a manufacturing method thereof.

  In recent years, there have been many proposals regarding semiconductor devices on which a metal-insulating film-metal (hereinafter referred to as MIM) capacitive element is mounted. Since the MIM capacitor element has a very low parasitic resistance, it can be applied to various circuits. Here, a method for manufacturing a conventional MIM capacitor will be described with reference to the drawings (for example, see Patent Document 1).

  As shown in FIG. 6, the lower electrode 202 is formed on the first insulating film 201 on the semiconductor substrate 200, and the second insulating film 203 is formed on the entire surface. Next, the second insulating film 203 in the capacitor formation region is selectively removed. Next, as shown in FIG. 7, a dielectric film 204 is deposited on the entire surface.

Next, as shown in FIG. 8, a part of the dielectric film 204 and the second insulating film 203 is etched to form a connection hole 205 for extracting the lower electrode. Next, as shown in FIG. 9, a metal layer is formed on the entire surface after reverse sputter etching. Next, the upper electrode 206 and the lower electrode lead wiring 207 are formed by selective etching. The MIM capacitor element is completed through the above steps.
Japanese Patent Laid-Open No. 08-306862

  However, the conventional method for manufacturing a semiconductor device has a problem in that the capacitance value of the MIM capacitor element cannot be obtained with high accuracy, the withstand voltage characteristics vary greatly, and the yield is low. These problems are caused by reverse sputter etching when the upper electrode is formed. In reverse sputter etching, when the upper electrode metal layer is deposited, the surface oxide film layer of the lower electrode 202 in the connection hole 205 is deposited before deposition in order to improve electrical connection with the lower electrode 202 through the connection hole 205. For example, alumina is removed by collision of ion particles generated in an inert gas plasma such as Ar. In the conventional example, when the surface oxide film layer of the lower electrode 202 is removed by this reverse sputter etching, a part of the dielectric film 204 is also etched at the same time, and the film thickness is reduced as compared with the deposition. In reverse sputter etching, the etch rate is likely to vary due to residual gases such as oxygen and moisture in the sputter atmosphere, and the thickness of the dielectric film 204 varies. For this reason, the capacitance value cannot be obtained with high accuracy, the variation in withstand voltage characteristics is increased, and the yield is lowered. Accordingly, there is a problem that it is difficult to stably realize the capacitance value of the MIM capacitor element with high accuracy.

  The present invention solves the above-described problems, and in the MIM capacitor element, the dielectric film thickness can be precisely controlled, and the structure of the element having a highly accurate capacitance value and high reliability, and its An object is to provide a manufacturing method.

  In order to achieve the above object, a semiconductor device according to the present invention includes a lower electrode made of a first metal layer formed on a semiconductor substrate, a dielectric film formed on a capacitance forming region on the lower electrode, In the semiconductor device including the upper electrode made of the second metal layer formed on the dielectric film, the portion of the lower electrode in contact with the dielectric film of the first metal layer is nitrided of the first refractory metal The portion of the upper electrode in contact with the dielectric film of the second metal layer is made of the second refractory metal.

  With the above configuration, the first refractory metal nitride, which is an adhesion layer, is formed immediately below the dielectric film. That is, since reverse sputter etching is performed before the formation of the dielectric film, the film thickness of the dielectric film does not vary.

  In the above semiconductor device, it is preferable that the first metal layer includes an aluminum layer and a first refractory metal nitride layer, and the first refractory metal is titanium.

  In the above semiconductor device, the second metal layer is preferably composed of an aluminum layer and a second refractory metal layer, and the second refractory metal is preferably tungsten.

  In the above semiconductor device, the dielectric film is preferably a silicon nitride film.

  The method for manufacturing a semiconductor device according to the present invention includes a step of forming a first metal layer serving as a lower electrode on a first insulating film formed on a semiconductor substrate, and a second insulation on the semiconductor substrate. A step of forming a film, a step of selectively opening a second insulating film to form a capacitance formation region on the lower electrode, and nitriding a first refractory metal on the entire surface of the semiconductor substrate after reverse sputter etching A step of forming a physical layer, a step of forming a dielectric film on the capacitance forming region, a step of forming a second refractory metal layer on the entire surface of the semiconductor substrate without performing reverse sputter etching, and a capacitance forming region Forming a resist film, etching the second refractory metal layer using the resist film as a mask, and forming a second metal layer serving as an upper electrode on the capacitance forming region. .

  With the above configuration, a first refractory metal nitride layer as an adhesion layer is formed on the entire surface after reverse sputter etching, and then a dielectric film is formed. Further, a second refractory metal layer is formed on the entire surface without performing reverse sputter etching thereafter. Therefore, the dielectric film is not etched by reverse sputter etching. That is, the thickness of the dielectric film does not change after deposition. Therefore, the dielectric film does not vary, and an MIM capacitive element having a highly accurate capacitance value can be formed.

  According to the semiconductor device and the manufacturing method thereof of the present invention, since the dielectric film is formed after the reverse sputter etching, the film thickness of the dielectric film does not change after the deposition. Therefore, the dielectric film does not vary, and an MIM capacitive element having a highly accurate capacitance value can be formed.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. 1 to 5 are cross-sectional views showing the manufacturing steps of the semiconductor device according to this embodiment. Note that the description of the resist film removal step is omitted unless otherwise specified.

  First, as shown in FIG. 1, a first silicon oxide film 101 having a thickness of about 1000 nm is formed on a P-type semiconductor substrate 100 made of a silicon single crystal whose principal surface is a (100) plane having a specific resistance of 10 to 15 Ω · cm. Form. Next, a metal layer is formed by sputtering, and a lower electrode 102 is formed using a resist film (not shown). Next, after a second silicon oxide film 103 having a thickness of about 2100 nm is formed on the entire surface, the thickness of the second silicon oxide film 103 is set on the lower electrode 102 by using, for example, CMP (Chemical Mechanical Polishing). Planarization polishing is performed so that the thickness becomes 1000 nm. Next, the second silicon oxide film 103 is selectively etched using a resist film (not shown) to form the capacitor formation region 104 and the lower electrode lead-through hole 105.

  Next, as shown in FIG. 2, after performing reverse sputter etching, Ti and TiN are successively formed as the adhesion layer 106. Next, after depositing a silicon nitride film of about 60 nm, the silicon nitride film is etched using a resist film (not shown) to form a dielectric film 107 in the capacitance forming region 104.

  Next, as shown in FIG. 3, a tungsten layer 108 is formed on the entire surface without performing reverse sputter etching. At this time, the through hole 105 is filled with tungsten.

  Next, as illustrated in FIG. 4, a resist film 109 is formed in the capacitor formation region 104, and the tungsten layer 108 is etched using the resist film 109. At this time, the portion of the tungsten layer 108 covered with the resist film 109 is not etched.

  Next, as shown in FIG. 5, after removing the resist film 109, a metal layer is formed on the entire surface by sputtering, and an upper electrode 110 and a lower electrode lead-out wiring 111 are formed using the resist film (not shown). At this time, unnecessary portions of the adhesion layer 106 are also etched.

  As described above, according to the present embodiment, the TiN layer 106 as the adhesion layer is formed on the entire surface after the reverse sputter etching, and then the dielectric film 107 is formed. Further, the tungsten layer 108 is formed on the entire surface without performing reverse sputter etching thereafter. Therefore, the dielectric film 107 is not etched by reverse sputter etching. That is, the thickness of the dielectric film 107 does not change after deposition. Therefore, the dielectric film does not vary, and an MIM capacitive element having a highly accurate capacitance value can be formed.

  In this embodiment, CMP is used as a planarization method, but this may be resist etch back or the like. Further, although the silicon nitride film is used as the dielectric film, it may be a silicon oxide film or a silicon oxynitride film.

  As described above, the semiconductor device and the manufacturing method thereof according to the present invention have a highly accurate MIM capacitance element having a high capacitance value and high reliability, and are useful for application circuits of semiconductor devices.

Sectional drawing of the manufacturing process of the semiconductor device in embodiment of this invention Sectional drawing of the manufacturing process of the semiconductor device in embodiment of this invention Sectional drawing of the manufacturing process of the semiconductor device in embodiment of this invention Sectional drawing of the manufacturing process of the semiconductor device in embodiment of this invention Sectional drawing of the manufacturing process of the semiconductor device in embodiment of this invention Cross-sectional view of conventional semiconductor device manufacturing process Cross-sectional view of conventional semiconductor device manufacturing process Cross-sectional view of conventional semiconductor device manufacturing process Cross-sectional view of conventional semiconductor device manufacturing process

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 P-type semiconductor substrate 101 1st silicon oxide film 102 Lower electrode 103 2nd silicon oxide film 104 Capacitance formation area 105 Through hole 106 Adhesion layer 107 Dielectric film 108 Tungsten layer 109 Resist film 110 Upper electrode 111 Lower electrode extraction wiring

Claims (5)

A lower electrode made of a first metal layer formed on a semiconductor substrate, a dielectric film formed on a capacitance forming region on the lower electrode, and a second metal layer formed on the dielectric film In the semiconductor device including the upper electrode, the portion of the lower electrode in contact with the dielectric film of the first metal layer is made of a first refractory metal nitride, and the second electrode of the upper electrode A portion of the metal layer in contact with the dielectric film is made of a second refractory metal. 2. The semiconductor device according to claim 1, wherein the first metal layer includes an aluminum layer and a nitride layer of the first refractory metal, and the first refractory metal is titanium. 2. The semiconductor device according to claim 1, wherein the second metal layer includes an aluminum layer and the second refractory metal layer, and the second refractory metal is tungsten. The semiconductor device according to claim 1, wherein the dielectric film is a silicon nitride film. Forming a first metal layer serving as a lower electrode on a first insulating film formed on a semiconductor substrate; forming a second insulating film on the semiconductor substrate; and Selectively opening a film to form a capacitance forming region on the lower electrode; forming a first refractory metal nitride layer on the entire surface of the semiconductor substrate after reverse sputter etching; Forming a dielectric film on the capacitance forming region, forming a second refractory metal layer on the entire surface of the semiconductor substrate without performing reverse sputter etching, and forming a resist film on the capacitance forming region. Manufacturing a semiconductor device comprising: a step; a step of etching the second refractory metal layer using the resist film as a mask; and a step of forming a second metal layer serving as an upper electrode on the capacitance forming region Method.

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