JP2005167103A5 - - Google Patents

Download PDF

Info

Publication number
JP2005167103A5
JP2005167103A5 JP2003406666A JP2003406666A JP2005167103A5 JP 2005167103 A5 JP2005167103 A5 JP 2005167103A5 JP 2003406666 A JP2003406666 A JP 2003406666A JP 2003406666 A JP2003406666 A JP 2003406666A JP 2005167103 A5 JP2005167103 A5 JP 2005167103A5
Authority
JP
Japan
Prior art keywords
semiconductor device
manufacturing
stage
tape
mounting table
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2003406666A
Other languages
Japanese (ja)
Other versions
JP4249003B2 (en
JP2005167103A (en
Filing date
Publication date
Application filed filed Critical
Priority to JP2003406666A priority Critical patent/JP4249003B2/en
Priority claimed from JP2003406666A external-priority patent/JP4249003B2/en
Publication of JP2005167103A publication Critical patent/JP2005167103A/en
Publication of JP2005167103A5 publication Critical patent/JP2005167103A5/ja
Application granted granted Critical
Publication of JP4249003B2 publication Critical patent/JP4249003B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Claims (9)

（ａ）ボンディングツールと、前記ボンディングツールと対向するように設けられ、かつ金属からなり、かつ断面形状が台形からなるステージを有するボンディング装置を準備する工程と、(A) preparing a bonding tool and a bonding apparatus having a stage provided to face the bonding tool and made of metal and having a trapezoidal cross-sectional shape;
（ｂ）フィルムと、前記フィルム上に形成されたリードと、前記リード上に形成されたソルダーレジストを有するテープを準備する工程と、(B) preparing a tape having a film, a lead formed on the film, and a solder resist formed on the lead;
（ｃ）バンプを有する半導体チップを前記ステージ上に配置する工程と、(C) placing a semiconductor chip having bumps on the stage;
（ｄ）前記テープを前記ボンディングツールと前記半導体チップの間に配置する工程と、(D) placing the tape between the bonding tool and the semiconductor chip;
（ｅ）前記ボンディングツールに荷重を加えて前記テープのインナーリードと前記半導体チップのバンプを電気的に接続する工程と、(E) applying a load to the bonding tool to electrically connect the inner leads of the tape and the bumps of the semiconductor chip;
を有することを特徴とする半導体装置の製造方法。A method for manufacturing a semiconductor device, comprising: 請求項１記載の半導体装置の製造方法において、前記（e）工程の後に、前記半導体チップと前記テープの間を樹脂封止する工程を行うことを特徴とする半導体装置の製造方法。2. The method of manufacturing a semiconductor device according to claim 1, wherein a step of resin-sealing between the semiconductor chip and the tape is performed after the step (e). 請求項１記載の半導体装置の製造方法において、前記ステージは、ステージ載置台と、前記ステージ載置台上に設けられたステージ部で構成されており、The method of manufacturing a semiconductor device according to claim 1, wherein the stage is composed of a stage mounting table and a stage unit provided on the stage mounting table.
前記ステージ載置台は、平面形状が円盤で構成され、The stage mounting table is composed of a disk in a planar shape,
前記ステージ部は、前記ステージ載置台の平面と垂直方向に交差する断面形状が台形で構成されていることを特徴とする半導体装置の製造方法。The method of manufacturing a semiconductor device, wherein the stage portion has a trapezoidal cross-sectional shape that intersects the plane of the stage mounting table in a vertical direction. 請求項３記載の半導体装置の製造方法において、前記ステージ部の傾斜角度は７０度であることを特徴とする半導体装置の製造方法。4. The method of manufacturing a semiconductor device according to claim 3, wherein the inclination angle of the stage portion is 70 degrees. 請求項３記載の半導体装置の製造方法において、前記ステージ載置台は、コバルトからなることを特徴とする半導体装置の製造方法。4. The method of manufacturing a semiconductor device according to claim 3, wherein the stage mounting table is made of cobalt. 請求項１記載の半導体装置の製造方法において、前記（e）工程では、前記ステージの設定温度が前記半導体チップの表面実測値の温度よりも高いことを特徴とする半導体装置の製造方法。2. The method of manufacturing a semiconductor device according to claim 1, wherein in the step (e), the set temperature of the stage is higher than the temperature of the surface measurement value of the semiconductor chip. 請求項１記載の半導体装置の製造方法において、前記（e）工程の後に製造される半導体装置は、ＣＯＦまたはＴＣＰであることを特徴とする半導体装置の製造方法。2. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device manufactured after the step (e) is COF or TCP. 請求項１記載の半導体装置の製造方法において、前記ボンディング装置は、さらにガイドと、前記ガイドと対向するように設けられたクランパを有し、2. The method of manufacturing a semiconductor device according to claim 1, wherein the bonding apparatus further includes a guide and a clamper provided so as to face the guide.
前記（ｄ）工程では、前記テープは前記ガイドと前記クランパで挟持されていることを特徴とする半導体装置の製造方法。In the step (d), the tape is sandwiched between the guide and the clamper. 請求項８記載の半導体装置の製造方法において、前記（ｄ）工程では、前記テープのインナーリードと前記半導体チップのバンプを位置合わせした状態で行うことを特徴とする半導体装置の製造方法。9. The method of manufacturing a semiconductor device according to claim 8, wherein in the step (d), the inner lead of the tape and the bump of the semiconductor chip are aligned.
JP2003406666A 2003-12-05 2003-12-05 Manufacturing method of semiconductor device Expired - Fee Related JP4249003B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2003406666A JP4249003B2 (en) 2003-12-05 2003-12-05 Manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003406666A JP4249003B2 (en) 2003-12-05 2003-12-05 Manufacturing method of semiconductor device

Publications (3)

Publication Number Publication Date
JP2005167103A JP2005167103A (en) 2005-06-23
JP2005167103A5 true JP2005167103A5 (en) 2007-01-18
JP4249003B2 JP4249003B2 (en) 2009-04-02

Family

ID=34728951

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003406666A Expired - Fee Related JP4249003B2 (en) 2003-12-05 2003-12-05 Manufacturing method of semiconductor device

Country Status (1)

Country Link
JP (1) JP4249003B2 (en)

Similar Documents

Publication Publication Date Title
TW498516B (en) Manufacturing method for semiconductor package with heat sink
JP5227501B2 (en) Stack die package and method of manufacturing the same
US6351029B1 (en) Stackable flex circuit chip package and method of making same
TW526598B (en) Manufacturing method of semiconductor device and semiconductor device
JP4757398B2 (en) Manufacturing method of semiconductor device
TWI654721B (en) Solder column for embedding semiconductor grains
JP2002353403A (en) Ultra-thin semiconductor package and manufacturing method therefor
TW200913202A (en) Semiconductor die package including stand off structures
JP2008078367A (en) Semiconductor device
JP3301355B2 (en) Semiconductor device, TAB tape for semiconductor device, method of manufacturing the same, and method of manufacturing semiconductor device
JP4339309B2 (en) Semiconductor device
JP2003060154A (en) Semiconductor device and its manufacturing method
JP2012028774A (en) Bonding structure and method
TW201626527A (en) Flat no-leads package with improved contact leads
JP2001338932A (en) Semiconductor device and method of manufacturing semiconductor device
JP2007027699A (en) Polygonal, round and circular flip chip ball grid array substrate
TWI274406B (en) Dual gauge leadframe
JP2005167103A5 (en)
JPH0344040A (en) Semiconductor device and its manufacture
JP2001127244A (en) Multichip semiconductor device and method of manufacturing the same
JP3964515B2 (en) Semiconductor device cutting and separating method
US20030214019A1 (en) Packaging system for semiconductor devices
JP4249003B2 (en) Manufacturing method of semiconductor device
JP4115556B2 (en) Manufacturing method of semiconductor package
JP2004014637A (en) Semiconductor device and wire bonding method