JP2005165784A - Sdram control circuit and backup control method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To surely keep CKE signal in L-level in a period deviating from the range of power source voltage permitted to a logic circuit. <P>SOLUTION: This SDRAM control circuit comprises a reset detection part 5 for monitoring the power source voltage supplied from a main power source Vcc and outputting a first detection signal RST1_L showing the comparison result of the power source voltage with a predetermined threshold and a second detection signal RST2_L changed with a delay of a predetermined time from the change of the first detection signal; and signal protection means 6, 7, Rpu and Rpd connected to the signal line of the CKE signal to connect the signal line to a ground level with a low impedance according to the state of the second detection signal. The SDRAM control circuit outputs a signal for entering SDRAM to a self-refresh mode according to the state of the first detection signal. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an SDRAM control circuit and a backup control method thereof, and more particularly to an SDRAM control circuit for holding data stored in a memory when a main power supply is stopped and a backup control method thereof.

  In contrast to the conventional DRAM (Dynamic Random Access Memory) that is asynchronous, SDRAM (Synchronous DRAM) that outputs data in synchronization with a clock signal having a fixed period is known. Yes. The SDRAM can be accessed at high speed from the external bus interface by synchronizing the clocks. The SDRAM is used as a large-capacity backup memory in addition to being used as a primary storage device for a general-purpose computer. For example, in a facsimile machine, it is used to protect image data received on behalf of an image and image data reserved for memory transmission from loss due to a power failure.

  When the SDRAM is used as a backup, the control circuit outputs a signal (hereinafter referred to as a CKE signal) that enables a clock signal supplied to the SDRAM to a logic low (L) level in the process in which the main power supply voltage drops. To maintain. As a method for maintaining the CKE signal at the L level, a method in which a pull-down resistor is always connected to a digital signal line output from a logic circuit (see, for example, Patent Document 1), and a method in which driving power is continuously supplied to an SDRAM control circuit (for example, in FIG. Patent Document 2) is known.

  In the example of backup using the RAS signal and CAS signal in the DRAM, a method of switching a control signal used during normal access and a signal used only during the rise and fall of the power supply voltage by a selector driven by the backup power supply. Is known (see, for example, Patent Document 3).

JP 2001-250377 A (paragraph number [0026], FIG. 1) JP 2002-108725 A (paragraph numbers [0016], [0021], [0029], FIG. 1, FIG. 5, FIG. 6, FIG. 7) JP 09-034806 (paragraph number [0033], FIG. 1)

  The logic circuit is guaranteed to maintain correct logic operation only within the allowable power supply voltage range. However, in the process in which the power supply voltage drops when the main power supply is turned off, there is always a period that deviates from the allowable power supply voltage range. During this deviation period, normal operation as a logic circuit cannot be expected. That is, the output logic level output within the allowable power supply voltage range is not necessarily maintained until the power supply voltage is completely lost. Therefore, according to the configurations described in Patent Document 1 and Patent Document 2, in the process where the power supply voltage disappears, the CKE signal may change to a signal level that the SDRAM recognizes as a logic high (H) level. was there. When such an unintended change in the CKE signal occurs, there is a problem that the SDRAM changes to a state other than self-refresh depending on the state of other control signals.

  On the other hand, when the configuration described in Patent Document 3 is applied to an SDRAM, a control signal such as a CKE signal is input from the control circuit block to each SDRAM via a selector. Since some delay time is required when the control signal passes through the selector, it is necessary to design the timing of signal generation in consideration of the delay time in the control circuit block. In the SDRAM that enables high-speed access, the delay time in the selector also has a problem that the timing design is difficult.

  The present invention has been made in view of such problems, and an object of the present invention is to reliably maintain the CKE signal at the L level during a period that deviates from the range of the power supply voltage allowed for the logic circuit. It is an object of the present invention to provide an SDRAM control circuit and a backup control method thereof.

  In order to achieve the above object, the present invention provides a SDRAM control circuit for generating a control signal for accessing an SDRAM by monitoring a power supply voltage supplied from a main power supply. A power supply voltage that outputs a first detection signal indicating a comparison result between the power supply voltage and a predetermined threshold value, and a second detection signal that changes after a predetermined time delay from a change in the first detection signal. A monitoring unit connected to a signal line of a signal for enabling a clock signal supplied to the SDRAM among the control signals, and the signal line is set to a ground level according to a state of the second detection signal; The SDRAM control circuit connects the SDRAM among the control signals according to a state of the first detection signal according to a state of the first detection signal. And outputs a signal to an entry in the mode.

  According to a second aspect of the present invention, in the SDRAM control circuit according to the first aspect, a secondary battery power supply means that charges when the main power source is in operation and discharges when the main power source is stopped, and a state of the second detection signal And a backup power supply means for switching the main power supply and the secondary battery power supply means to connect to the SDRAM.

  According to a third aspect of the present invention, the predetermined time according to the first or second aspect of the present invention is required until the SDRAM finishes executing the self-refresh mode after outputting the first detection signal. It is characterized by being longer than the time to perform.

  A fourth aspect of the invention is characterized in that the minimum drive power supply voltage of the signal protection means according to the first, second, or third aspect is not more than the upper limit voltage of the L level of the logic circuit.

  According to a fifth aspect of the present invention, in the backup control method in the SDRAM control circuit for generating a control signal for accessing the SDRAM, the power supply voltage supplied from the main power supply is monitored by the power supply voltage monitoring means. A step of outputting a first detection signal when a predetermined threshold value is exceeded, and a step of outputting a second detection signal by the power supply voltage monitoring means after a predetermined time delay from a change in the first detection signal And a signal protection means connected to a signal line of a signal for enabling a clock signal supplied to the SDRAM among the control signals, and the signal line and the ground level according to the state of the second detection signal. And a step of changing from low impedance to high impedance.

  According to a sixth aspect of the present invention, in the backup control method in the SDRAM control circuit for generating a control signal for accessing the SDRAM, the power supply voltage supplied from the main power supply is monitored by the power supply voltage monitoring means. A step of outputting a first detection signal when the threshold value is below a predetermined threshold; and the SDRAM control circuit self-refreshes the SDRAM among the control signals in accordance with the state of the first detection signal. A step of outputting a signal for entering a mode, a step of outputting a second detection signal by the power supply voltage monitoring means after a predetermined time delay from a change in the first detection signal, and the SDRAM among the control signals The signal detection means connected to the signal line of the signal for enabling the clock signal supplied to the second detection signal Depending on the state, characterized by comprising the steps of: a low-impedance connection of the signal line to the ground level.

  According to a seventh aspect of the present invention, in the backup control method according to the sixth aspect, the main power source and a secondary battery power source means that discharges while the main power source is stopped according to the state of the second detection signal. And a step of switching to the SDRAM.

  According to an eighth aspect of the present invention, the predetermined time according to the sixth or seventh aspect is required until the SDRAM finishes executing the self-refresh mode after outputting the first detection signal. It is characterized by being longer than the time to perform.

  As described above, according to the present invention, the control signal is connected to the signal line of the signal (CKE) that enables the clock signal supplied to the SDRAM, and depends on the state of the second detection signal (RST2_L). Since the signal protection means for connecting the signal line to the ground level with low impedance is provided, the CKE signal can be reliably maintained at the L level even when the main power supply is stopped, and the SDRAM is driven by the backup power supply. By doing so, it becomes possible to hold the stored data.

  Further, according to the present invention, the signal protection means changes the signal line and the ground level to a high impedance, so that the influence on the signal propagation delay characteristic can be greatly reduced. As a result, when the SDRAM control circuit is made into an IC and is operated at a very high speed, the signal propagation characteristic can be approximated to the design value.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 shows an SDRAM backup control circuit according to an embodiment of the present invention. An SDRAM control unit 4 that controls access to the SDRAM 3 and a backup power supply control unit 2 that supplies a backup power supply Vbu are connected to the SDRAM 3. The SDRAM control unit 4 is connected to a reset detection unit 5 that is a power supply voltage monitoring unit that compares the main power supply Vcc and a predetermined threshold voltage Vth and outputs the result as active L logic signals RST1_L and RST2_L. ing. The backup power supply controller 2 is connected to a chargeable / dischargeable secondary battery 1 in which the main power supply Vcc is charged during the active period and discharged while the main power supply Vcc is inactive.

  The SDRAM control unit 4 generates a control signal that matches the specifications of the SDRAM 3 in response to a data access request to the SDRAM 3 from an arithmetic control unit (not shown). When a change in the logic level H → L of the RST1_L signal described later is detected, a signal for entering the self-refresh mode is output to the SDRAM 3. The backup power supply controller 2 supplies the backup power supply Vbu based on the power while the main power supply Vcc is active, and charges the secondary battery 1 while the main power supply Vcc is inactive. The backup power supply Vbu is supplied by the discharge power from 1.

  The SDRAM 3 and the SDRAM control unit 4 are connected by a clock enable control signal CKE and control signals signals such as a clock signal and an address signal. CKE is connected via a damping resistor R0 having a relatively small resistance value for waveform shaping, and further connected to the drain terminal D of the second FET 7 via a resistor Rpd having a small resistance value. . The gate terminal G of the second FET 7 is pulled up by the backup power supply Vbu and the resistor Rpu and connected to the drain terminal D of the first FET 6. The logic signal RST2_L is input to the gate terminal G of the first FET 6.

  With such a configuration, the reset detection unit 5 becomes the first power supply voltage drop detection signal RST1_L that becomes L level when the main power supply Vcc is lower than the predetermined threshold voltage Vth and becomes H level when the main power supply Vcc is equal to or higher than Vth, and RST1_L. The second power supply voltage drop detection signal RST2_L that changes after a predetermined time delay is output. The first FET 6 inputs the RST2_L signal to the gate terminal G. When the RST2_L is at the logic level H, the first FET 6 connects the signal out1 and the ground. When the RST2_L is at the logic level L, the first FET 6 Set to impedance state.

  The second FET 7 inputs the signal out1 to the gate terminal G. When the signal out1 is at the logic level H (that is, when RST2_L is at the logic level L), the second FET 7 connects the signal out2 and the ground. When it is at the logic level L (that is, when RST2_L is at the logic level H), a high impedance state is set between the signal out2 and the ground. In this way, when RST2_L is at the logic level L, the circuit that connects the CKE signal to the ground level corresponds to the signal protection means.

  The operation of the SDRAM backup control circuit will be described using a time chart on the assumption that the backup power supply Vbu supplies a predetermined power supply voltage when the main power supply Vcc is stopped. FIG. 2 shows a time chart of the SDRAM backup control circuit according to the embodiment of the present invention. Each section shown in FIG. 2 will be described.

[Period Tr1 (Vcc <Vmin)]
This is an initial state in which the main power supply Vcc is completely stopped or has just been started and has not reached the minimum power supply voltage Vmin at which the SDRAM control unit 4 can operate. Although a slight power supply voltage equal to or lower than the voltage Vmin is applied to the SDRAM control unit 4, since the power supply voltage is too low, it cannot be expected to operate as a logic circuit. For example, the same applies even if a signal instructing hardware reset is input. Therefore, the CKE signal output from the SDRAM control unit 4 during this period should be considered indefinite.

  On the other hand, a commercially available reset monitoring IC is designed to have a very low minimum drive power supply voltage as compared with a logic circuit. That is, the minimum operating power supply voltage of the reset monitoring IC is designed to be lower than the upper limit of the L level of the logic circuit. Therefore, by using a reset monitoring IC as the reset detection unit 5, the signals RST1_L and RST2_L are maintained at the ground level during this period.

  At this time, the signal out1 is maintained at the H level by the pull-up resistor Rpu of the backup power supply Vbu. Further, the source S and the drain D of the second FET 7 are in a low impedance state. Therefore, even if the SDRAM control unit 4 outputs a signal of any level lower than the power supply voltage Vcc during the period Tr1 as the CKE signal, the CKE signal passes through the resistor Rpd connected to the signal line and the second FET 7. Is connected to the ground. The CKE signal is reliably maintained at the L level for the SDRAM 3 which is kept in the operating state by the backup power supply Vbu.

[Period Tr2 (Vmin <Vcc ≦ Vth)]
The SDRAM control unit 4 can operate as a logic circuit and recognizes the RST2_L signal as a reset signal. Since the RST2_L signal remains at the L level, the SDRAM control unit 4 outputs the CKE signal at the L level. Similarly to the period Tr1, the CKE signal is maintained at the L level also by the second FET 7.

[Period Tr3 (Vth ≦ Vcc and before Td1 has elapsed)]
The reset detection unit 5 detects that the potential of the main power supply Vcc has risen above the predetermined threshold value Vth, but maintains the RST1_L and RST2_L signals at the L level until the delay time Td1 elapses. Therefore, the state of the period Tr2 described above is maintained.

[Period Tr4 (Vth ≦ Vcc and after Td1 has elapsed)]
The reset detection unit 5 changes the RST1_L signal to the H level, but the RST2_L signal maintains the L level until Td2 time elapses. The SDRAM control unit 4 does not perform any processing due to the change of the RST1_L signal from the L level to the H level.

[Period Tnml (Vth ≦ Vcc and after Td1 + Td2 has elapsed)]
The reset detection unit 5 changes the RST2_L signal to the H level. As a result, the impedance between the drain and source of the first FET 6 becomes low, and the impedance between the drain and source of the second FET 7 changes to high impedance. This cancels the pull-down of the CKE signal to the ground level by the resistor Rpd.

  On the other hand, since the SDRAM control unit 4 receives the RST2_L signal as a reset signal, the reset is released. Similarly, the operation control unit (not shown) is also reset to instruct the SDRAM control unit 4 to initialize the SDRAM 3. In this process, the CKE signal is driven to the H level. At this time, since the pull-down of the CKE signal to the ground level by the resistor Rpd has already been canceled, a desired signal is transmitted to the SDRAM 3.

  The initialization process is necessary for starting up the SDRAM 3 from the main power supply Vcc when the backup period of the secondary battery 1 is a long time exceeding its charge capacity. Note that this initialization process is not necessary if only the SDRAM 3 is to be returned from the self-refresh state. Therefore, in any case, initialization processing is executed. Thereafter, the SDRAM 3 becomes in a state where it can be normally accessed by a control signal driven by the SDRAM control unit 4. At this time, since the resistor Rpd is only attached to the CKE signal as a high impedance branch wiring pattern, the influence on the propagation delay time of the CKE signal output from the SDRAM control unit 4 can be greatly reduced.

[Period Tf1 (Vcc <Vth)]
When the supply of the main power supply Vcc is cut off and the power supply voltage gradually decreases and becomes equal to or lower than the predetermined threshold value Vth, the reset detection unit 5 detects this and changes the RST1_L signal to the L level. When the SDRAM control unit 4 recognizes that the RST1_L signal has changed to the L level, the SDRAM control unit 4 automatically outputs a signal for causing the SDRAM 3 to enter the self-refresh mode. As a result, the SDRAM control unit 4 subsequently outputs an L level as the CKE signal, and completely blocks all data access to the SDRAM 3.

  On the other hand, the RST1_L signal is output as an interrupt request signal to an arithmetic control unit (not shown) to notify that the system is being stopped. The arithmetic control unit receives this interrupt request signal and thereafter executes a special stop / standby process in which access to the SDRAM 3 is not performed.

[Period Tf2 (Vcc <Vth and after Td3 has elapsed)]
After a predetermined delay time Td3 has elapsed after the RST1_L signal has changed to the L level, the reset detection unit 5 changes the RST2_L signal to the L level. This change resets the SDRAM backup control circuit as well as the SDRAM control unit 4. The delay time Td3 must be a period that is guaranteed to be a sufficient time to complete the self-refresh mode processing of the SDRAM control unit 4 in the period Tf1. On the other hand, similarly, due to the change of RST2_L to the L level, the CKE signal is connected to the ground level with a low impedance via the first FET 6, the second FET 7, and the resistor Rpd.

[Period Tf3 (Vcc <Vmin)]
Since the power supply voltage of the main power supply Vcc is lower than the minimum operating voltage Vmin, the SDRAM control unit 4 cannot function as a normal logic circuit, and the CKE signal driven by the SDRAM control unit 4 becomes indefinite. However, since the CKE signal is electrically connected to the ground with a low impedance through the second FET 7 and the resistor Rpd, a signal having a potential such that the SDRAM 3 erroneously recognizes the CKE signal as H level by mistake. Does not occur.

  In this embodiment, the embodiment in which the CKE signal is controlled by the FET element has been described. However, it is possible to easily implement the SDRAM control circuit as an IC by using a monolithic configuration using other circuit elements such as transistors. it can.

It is a circuit diagram showing an SDRAM backup control circuit according to an embodiment of the present invention. It is a time chart of the SDRAM backup control circuit concerning one Embodiment of this invention.

Explanation of symbols

1 Secondary battery 2 Backup power supply controller 3 SDRAM
4 SDRAM control unit 5 Reset detection unit 6, 7 FET

Claims (8)

In an SDRAM control circuit that generates a control signal for accessing an SDRAM,
The power supply voltage supplied from the main power supply is monitored, and the first detection signal indicating the comparison result between the power supply voltage and a predetermined threshold value is changed with a predetermined time delay from the change of the first detection signal. Power supply voltage monitoring means for outputting a second detection signal;
A signal that is connected to a signal line of a signal that enables a clock signal supplied to the SDRAM among the control signals, and that connects the signal line to a ground level with a low impedance according to a state of the second detection signal. Protective means,
The SDRAM control circuit outputs a signal that causes the SDRAM to enter a self-refresh mode among the control signals in accordance with the state of the first detection signal. Rechargeable battery power supply means for charging during operation of the main power supply and discharging during stoppage;
The backup power supply means for switching the main power supply and the secondary battery power supply means to connect to the SDRAM according to the state of the second detection signal. SDRAM control circuit.   3. The predetermined time is longer than a time required from when the first detection signal is output to when the SDRAM finishes executing the self-refresh mode. SDRAM control circuit.   4. The SDRAM control circuit according to claim 1, wherein the minimum drive power supply voltage of the signal protection means is equal to or lower than an L level upper limit voltage of the logic circuit. In a backup control method in an SDRAM control circuit for generating a control signal for accessing an SDRAM,
Monitoring the power supply voltage supplied from the main power supply by the power supply voltage monitoring means, and outputting the first detection signal when the power supply voltage exceeds a predetermined threshold;
After the power supply voltage monitoring means outputs a second detection signal after a predetermined time delay from the change of the first detection signal;
A signal protection means connected to a signal line for enabling a clock signal supplied to the SDRAM among the control signals, and depending on the state of the second detection signal, the signal line and the ground level. And a step of changing the interval from low impedance to high impedance. In a backup control method in an SDRAM control circuit for generating a control signal for accessing an SDRAM,
Monitoring the power supply voltage supplied from the main power supply by the power supply voltage monitoring means, and outputting the first detection signal when the power supply voltage falls below a predetermined threshold;
The SDRAM control circuit outputs a signal that causes the SDRAM to enter a self-refresh mode among the control signals in accordance with a state of the first detection signal;
After the power supply voltage monitoring means outputs a second detection signal after a predetermined time delay from the change of the first detection signal;
A signal protection unit connected to a signal line of a signal that enables a clock signal supplied to the SDRAM among the control signals is lowered to the ground level according to the state of the second detection signal. A backup control method comprising: a step of connecting by impedance. According to the state of the second detection signal, there is further provided a step of switching between the main power source and a secondary battery power source means that discharges when the main power source is stopped, and connecting to the SDRAM. The backup control method according to claim 6.   8. The predetermined time is longer than a time required from when the first detection signal is output to when the SDRAM finishes executing the self-refresh mode. The backup control method described in 1.

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