JP2005159542A - Bridge type drive circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a bridge type drive circuit wherein a charge pump circuit for a plurality of bridge type drive output circuits whose output power supply voltages differ from each other is configured by few numbers of components and each of level shift circuits is realized by means of a MOS transistor with a low gate-source withstanding voltage. <P>SOLUTION: The charge pump circuit is configured with one oscillator for generating a plurality of voltages higher by a prescribed voltage from each of the output power supply voltages, and each level shift circuit is configured by using resistors and Zener diodes so as to avoid a high output voltage of the charge pump circuit from being applied between the gate and the source of the MOS transistor as it is. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a bridge type drive circuit that can drive a plurality of inductance loads by outputs of a plurality of bridge circuits having different power supply voltages and can be configured using a high power supply voltage.

  This type of conventional bridge-type drive circuit is configured as schematically shown in FIG. In FIG. 6, 101 and 104 are N channel MOS transistors having a small current supply capability, 102, 103, 105 and 106 are N channel MOS transistors having a large current supply capability, 107 is a power source, 108 is an inductance, 109 is a resistor, and 110 is a resistor. This is the current flowing through the inductance 108.

  When the current 110 is large and the current 110 flows in the direction of the arrow in FIG. 6, the N-channel MOS transistors 101, 103, 104, and 105 are turned off, the N-channel MOS transistor 106 is turned on, and the N-channel MOS transistor 102 is PWM (pulsed). The current 110 is controlled by turning on / off based on the width conversion signal. When the current 110 is small and the current 110 flows in the direction of the arrow in FIG. 6, the N-channel MOS transistors 102, 103, 104, and 105 are turned off, the N-channel MOS transistor 106 is turned on, and the N-channel MOS transistor 101 is turned into a PWM signal. The current 110 is controlled by turning it on and off based on this.

  When the current 110 is small, it is driven by the N-channel MOS transistor 101 having a small current supply capability, so that the peak current is difficult to increase and PWM noise is not easily generated. The above operation is the same when the current 110 is passed in the direction opposite to that in FIG.

  Next, FIG. 7 is a circuit showing a detailed configuration of a conventional bridge type drive circuit, where 107 is a power source, 101 is an N-channel MOS transistor having a small current supply capability, and 102 and 105 are N-channel MOS transistors having a large current supply capability. 108, inductance, 110, current flowing in the inductance 108, 111, 112, 113, 114, 115, 116, 117, 118 are N channel MOS transistors, 119, 120, 121, 122 are P channel MOS transistors, 123, 124 , 125, 126, 127, 128, 129, 130, 131, 132, and 133 are diodes, 134, 135, 136, and 137 are resistors, and 138 and 139 are capacitors.

  As boosting means for driving the gate of the N-channel MOS transistor 102 when the current 110 is large, two types of bootstrap and charge pump are described at the same time. When the voltage generated between the terminals of the diode 130 when the channel MOS transistor 102 is OFF and the N-channel MOS transistor 105 is ON is approximated to V130, the voltage V139 generated between the terminals of the capacitor 139 is (V107) Equation 1)

コンデンサ１３９は（数１）の電圧を保持したまま、ＮチャネルＭＯＳトランジスタ１０５，１１６，１１７がオフ、ＮチャネルＭＯＳトランジスタ１１５がオンし、ＮチャネルＭＯＳトランジスタ１１８のゲート・ソース間電圧をＶＧＳ１１８、ダイオード１２９に発生する電圧をＶ１２９とすると、ＮチャネルＭＯＳトランジスタ１０２のゲートに印加される電圧ＶＧ１０２ａは、（数２）となる。

The capacitor 139 holds the voltage of (Equation 1), the N-channel MOS transistors 105, 116, 117 are turned off, the N-channel MOS transistor 115 is turned on, and the gate-source voltage of the N-channel MOS transistor 118 is set to VGS 118, diode Assuming that the voltage generated at 129 is V129, the voltage VG102a applied to the gate of the N-channel MOS transistor 102 is (Expression 2).

なお、ＮチャネルＭＯＳトランジスタ１１５のオン・オフするタイミングとＮチャネルＭＯＳトランジスタ１１６，１１７のオン・オフするタイミングは逆であり、また、ＮチャネルＭＯＳトランジスタ１１５のオン・オフするタイミングとＮチャネルＭＯＳトランジスタ１０５のオン・オフするタイミングも基本的に逆であるが、ＮチャネルＭＯＳトランジスタ１０２とＮチャネルＭＯＳトランジスタ１０５間で貫通電流が流れないようなタイミング関係になっている。

The on / off timing of N channel MOS transistor 115 and the on / off timing of N channel MOS transistors 116 and 117 are opposite, and the on / off timing of N channel MOS transistor 115 and the N channel MOS transistor The timing of turning on and off 105 is basically opposite, but the timing relationship is such that no through current flows between the N channel MOS transistor 102 and the N channel MOS transistor 105.

  Next, when the voltage is boosted by the charge pump, a clock signal is input to the gate of N channel MOS transistor 113 only during a period in which N channel MOS transistor 115 turns on N channel MOS transistor 102 corresponding to the on period. Assuming that the voltages generated in the diodes 125 and 126 when the MOS transistor 113 is on are V125 and V126, the voltage V138 generated at both ends of the capacitor 138 at this time becomes (Equation 3)

この電圧を保持したまま、ＮチャネルＭＯＳトランジスタ１１３がオフした時のＮチャネルＭＯＳトランジスタ１１４のゲート・ソース間電圧をＶＧＳ１１４、ダイオード１２７に発生する電圧をＶ１２７とすると、ＮチャネルＭＯＳトランジスタ１０２のゲート電圧ＶＧ１０２ｂは、（数４）となる。

With this voltage held, if the gate-source voltage of the N-channel MOS transistor 114 when the N-channel MOS transistor 113 is turned off is VGS114 and the voltage generated in the diode 127 is V127, the gate voltage of the N-channel MOS transistor 102 The VG 102b becomes (Expression 4).

次に、電流１１０が小さい時は、ＮチャネルＭＯＳトランジスタの電流供給能力が小さい方が好ましいため、ＮチャネルＭＯＳトランジスタ１０１のゲート電圧は、昇圧されることなく、電源１０７のＶ１０７の電圧が印加される構成になっている。
特許第３１９９７２２号公報

Next, when the current 110 is small, it is preferable that the current supply capability of the N-channel MOS transistor is small. Therefore, the gate voltage of the N-channel MOS transistor 101 is not boosted and the voltage of V107 of the power supply 107 is applied. It is the composition which becomes.
Japanese Patent No. 3199722

  However, in the bridge-type driving circuit having such a configuration, the voltage for driving the gate of the N-channel MOS transistor 102 depends on VGS118, VGS114, etc. as shown in (Equation 2) for the bootstrap and (Equation 4) for the charge pump. The on-resistance of the N-channel MOS transistor 102 cannot be sufficiently reduced because the voltage drop is not sufficiently high.

  In addition, when the bridge type driving circuit as shown in FIG. 7 has multiple channels, the bootstrap requires two large capacitors corresponding to the capacitor 139 shown in FIG. 7 for every channel. When the circuit of FIG. 7 is configured, the number of external parts increases, and in the charge pump, the period corresponding to the N-channel MOS transistor 115 is turned on for each channel (the part corresponding to the N-channel MOS transistor 102 is turned on). In this period, since it is necessary to input a clock signal for turning on / off the N-channel MOS transistor 113 for each channel, it is necessary to configure a charge pump circuit for each channel.

  In addition, when the voltage corresponding to the power supply 107 differs depending on the channel, a voltage higher than the voltage corresponding to the power supply 107 is generated in each channel by a gate corresponding to the N-channel MOS transistor 102 of each channel. I can't let you.

  When the voltage corresponding to the power source 107 is high depending on the channel, in the case of bootstrap, the voltage VZ1 between the gate and the source of the N-channel MOS transistors 121 and 122 is expressed as V129 when the diode 129 is turned on. Then, (Equation 5)

ＮチャネルＭＯＳトランジスタ１２１，１２２のゲート・ソース間耐圧が高いものが必要となるという問題があった。

There is a problem that the N-channel MOS transistors 121 and 122 must have high gate-source breakdown voltage.

  The present invention is directed to solving the problems of the prior art, and can increase the voltage corresponding to the gate of the N-channel MOS transistor 102 to a sufficiently high voltage. When a plurality of circuits are required, an external capacitor required for bootstrap and a charge pump that operates by a clock signal for a period that turns on a portion corresponding to the N-channel MOS transistor 102 are not required for each channel, In addition, when the voltage corresponding to the power supply 107 differs depending on the channel, a voltage higher than the voltage corresponding to the power supply 107 is generated in each channel by a gate corresponding to the N-channel MOS transistor 102 of each channel. N channel MOS transistor 102 An object of the present invention is to provide a bridge type drive circuit that can be configured with a low gate-source breakdown voltage of a MOS transistor constituting a circuit even when a boosted voltage required for driving a portion corresponding to a gate is high. And

  To achieve this object, a bridge-type drive circuit according to the present invention includes a control circuit power supply, an oscillator using the control circuit power supply as a voltage supply source, at least one bridge-type drive output circuit, At least one output power supply that supplies a voltage to the bridge type drive output circuit, and each output power supply is higher than the output power supply by a voltage obtained by subtracting two diodes from the control circuit power supply voltage Charge pump circuit to be generated for each, a level shift circuit provided for each bridge type drive output circuit using each output voltage of the charge pump circuit as a voltage supply source, and each bridge using a power supply for the control circuit as a voltage supply source And a second pulse output from the dead time generation circuit is the first N channel of the level shift circuit. The third pulse output from the dead time generation circuit is in an inverted relationship with the first pulse output, and is applied to the gate of the second N-channel MOS transistor with the source of the level shift circuit grounded. Protection that clamps the voltage drop from the output of the charge pump circuit and at least one or more series connected resistance components that are input and cause a voltage drop between the drain of the first N-channel MOS transistor and the output of the charge pump circuit The source is connected to the output of the charge pump circuit by the voltage drop from the output of the charge pump circuit generated based on the resistance component between the drain of the first N-channel MOS transistor and the output of the charge pump circuit and the protection element. Gate-source voltage of the first P-channel MOS transistor Controlled and synchronized with the fourth pulse output outputted from the connection point of the drain of the first P-channel MOS transistor and the drain of the second N-channel MOS transistor and the second pulse output from the dead time generating circuit. A bridge type drive output circuit is driven by the pulse output of 1, and a zener diode is provided between the gate and source of the third N-channel MOS transistor constituting the bridge type drive output circuit driven by the fourth pulse output. It is comprised as follows.

  According to the above configuration, the bridge-type drive output circuit can be driven at a voltage higher than each output power source by a voltage obtained by subtracting two diodes from the first control power supply voltage. A capacitor and a charge pump circuit for each bridge type drive output circuit are not required, and the voltage between the gate and source of the first and second N-channel MOS transistors constituting the level shift circuit is the voltage of the power supply for the control circuit. Because the output voltage of the charge pump circuit and the resistance component between the drain of the first N channel MOS transistor and the voltage controlled by the protection element are applied between the gate and source of the first P channel MOS transistor. No overvoltage is applied, and the third N-channel MOS transistor has a Zener Resistance component between the source and the drain of the first P-channel MOS transistor serving as a diode and a current limiting element by pressure-proof protection.

  As described above, according to the present invention, since a high output voltage of the charge pump circuit can be realized, the on-resistance of the N-channel MOS transistor constituting the bridge type drive output circuit can be reduced, and the configuration of the charge pump circuit As described above, since a plurality of voltages obtained by boosting each of the plurality of output power supply voltages by the same voltage is generated by a pulse output of one oscillator, a plurality of voltages can be obtained even in multi-channels having different output power supply voltages. A charge pump circuit composed of an oscillator is not required, many capacitors required for a bootstrap configuration when there are multiple channels (external capacitors when configured on a semiconductor substrate) are also unnecessary, and as a level shift circuit, Gate and source of MOS transistors constituting the level shift circuit Be those rce low withstand voltage advantageously possible to configure.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a circuit diagram showing an outline of a basic configuration of a bridge-type drive circuit according to Embodiment 1 of the present invention. 1, 2, 3, 4 are N-channel MOS transistors, 5 is a power source, 6 is an inductance, and 7 is A resistor 8 is a current flowing through the inductance 6.

  When the current 8 flows in the direction of the arrow in FIG. 1, the N-channel MOS transistors 2 and 3 are turned off, the N-channel MOS transistor 4 is turned on, and the N-channel MOS transistor 1 is turned on / off according to the PWM signal. Can be controlled.

  When the N-channel MOS transistor 3 is turned off and the N-channel MOS transistor 1 is switched from on to off, a current 8 flows through a diode between the body and the drain of the N-channel MOS transistor 3. The on / off timing of the N channel MOS transistor 1 and the N channel MOS transistor 3 is reversed, and the through current through the N channel MOS transistor 1 and the N channel MOS transistor 3 does not flow from the power source 5 to the ground terminal. Even in a synchronous rectification type configuration in which a dead time period in which both transistors are turned off at the time of on / off switching is provided, this can be realized with reduced power consumption.

  When the current 8 shown in FIG. 1 is flowed in the reverse direction, the N channel MOS transistors 1 and 4 are turned off, the N channel MOS transistor 3 is turned on, and the N channel MOS transistor 2 is turned on and off according to the PWM signal. It becomes the operation.

  The above explanation is a case where the N-channel MOS transistor 4 or 3 is turned on and the N-channel MOS transistor 1 or 2 is turned on / off according to the PWM signal. However, the N-channel MOS transistor 1 or 2 is turned on, The current 8 can be similarly controlled when the N-channel MOS transistor 4 or 3 is turned on / off according to the PWM signal.

  Next, FIG. 2 is an example of a detailed configuration in the first embodiment, and shows a two-channel bridge type driving circuit using a voltage different from that of the power source 10 and the power source 11 as an output power source, and the N channel in the circuit of FIG. 2 shows a circuit in which one terminal of the resistors 38 and 39 in FIG. 2 is grounded, assuming that the MOS transistor 2 is off and the N-channel MOS transistor 4 is on. Different voltages of the boosted signals 57 and 58 are shown. Are generated based on one oscillator 46.

  In FIG. 2, 9, 10, 11 are power supplies, 12, 13, 14, 15, 16, 17, 18, 19, 20 are N channel MOS transistors, 21, 22, 23 are P channel MOS transistors, 24, 25, 26, 27 are capacitors, 28, 29 are inverters, 30, 31, 32, 33 are diodes, 34, 35, 36, 37 are Zener diodes, 38, 39, 40, 41, 42, 43 are resistors, 44, 45 Is an oscillator, 46 is an oscillator, 47 and 48 are first and second dead time generating circuits, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58 and 60 are signals.

  The operation of the bridge type driving circuit according to the first embodiment configured as described above is the same as the signal 51 of the input / output terminals of the first input terminal and the first to third output terminals of the first dead time generation circuit of FIG. , 52, 53 will be used to explain.

  Note that the signal 60 that is the output of the oscillator 46 is a sufficiently low impedance output, the H level outputs the voltage of the power supply 9 and the L level outputs 0 V. Generally, the duty of the oscillator 46 is about 50. %, The frequency of the oscillator 46 is about 500 kHz, and the values of the capacitors 24, 25, 26, and 27 are about 0.1 μF.

  When the voltages of the power supplies 9, 10, and 11 are V9, V10, and V11, respectively, and the voltage generated between the terminals of the diode 30 when the signal 60 is 0V is approximated to V30, the voltage V24 generated in the capacitor 24 when the signal 60 is 0V. Becomes (Equation 6).

そして、コンデンサ２４に電圧Ｖ２４を保持したまま、信号６０がＶ９のＨレベルの電圧になった時のダイオード３１の端子間に発生する電圧をＶ３１と近似すると、信号５７の電圧Ｖ５７は（数７）のようになる。

When the voltage generated between the terminals of the diode 31 when the signal 60 becomes the H level voltage of V9 while the voltage V24 is held in the capacitor 24 is approximated to V31, the voltage V57 of the signal 57 is )become that way.

ダイオード３１は信号５７からダイオード３１方向への電流の逆流を防止している。

The diode 31 prevents the backflow of current from the signal 57 toward the diode 31.

  Similar to (Equation 7), the voltage V58 of the signal 58 is given by (Equation 8).

図３に示すように第１デッドタイム作成回路４７の第１入力端子の信号４９から作成した第１〜第３出力端子の信号５１，５２，５３のタイミング関係としては、信号５１と信号５２は反転関係、信号５１と信号５３の関係は、ｔ１，ｔ２のようなＮチャネルＭＯＳトランジスタ１３とＮチャネルＭＯＳトランジスタ１４が共にオフになるような期間を設け、ＮチャネルＭＯＳトランジスタ１３のソースに接続されるインダクタンス４４、抵抗３８などの負荷にかかわらず、電源１０と接地間にてＮチャネルＭＯＳトランジスタ１３とＮチャネルＭＯＳトランジスタ１４を経由して貫通電流が流れないようにしている。

As shown in FIG. 3, the timing relationship between the signals 51, 52, 53 of the first to third output terminals created from the signal 49 of the first input terminal of the first dead time creation circuit 47 is as follows. The inversion relationship, the relationship between the signal 51 and the signal 53, is connected to the source of the N-channel MOS transistor 13 by providing a period in which both the N-channel MOS transistor 13 and the N-channel MOS transistor 14 are turned off, such as t1 and t2. Regardless of the load such as the inductance 44 and the resistor 38, the through current does not flow between the power supply 10 and the ground via the N-channel MOS transistor 13 and the N-channel MOS transistor 14.

  The H level of the signals 51, 52, 53 is the voltage of the power supply 9 that is equal to or lower than the gate-source breakdown voltage of the N channel MOS transistors 14, 15, 16, and the gate of the P channel MOS transistor 22 when the signal 51 is H level. The connection point of the resistors 40 and 41 connected in series between the signal 57 and the drain of the N-channel MOS transistor 16 is connected between the source and the P-channel MOS transistor 22 so that a voltage equal to or lower than the gate-source breakdown voltage is applied. At the same time, the cathode of a Zener diode 34 having a Zener voltage equal to or lower than the gate-source breakdown voltage of the P-channel MOS transistor 22 is used as the source of the P-channel MOS transistor, and the anode is used as the gate of the P-channel MOS transistor 22. Connected.

  When signal 51 is at H level and signal 52 is at L level, the gate of N channel MOS transistor 13 is at H level (voltage V57 of signal 57), but the zener voltage is the gate-source breakdown voltage of N channel MOS transistor 13. By connecting the cathode of the lower Zener diode 36 to the gate of the N-channel MOS transistor 13 and connecting the anode to the source of the N-channel MOS transistor 13, the P-channel MOS transistor 22 becomes a current limiting element (resistance component). The gate-source breakdown voltage protection of the N channel MOS transistor 13 is performed.

  Similarly to the drive of the inductance 44 and the resistor 38 based on the signal 49, the drive of the inductance 45 and the resistor 39 based on the signal 50 is also performed. However, when the voltages of the power supply 10 and the power supply 11 are different, (Equation 7) , (Equation 8), V57 and V58 are different, and it is preferable to adjust the ratio of the resistor 42 and the resistor 43 for protecting the gate-source breakdown voltage of the P-channel MOS transistor 23.

  As described above, according to the first embodiment, the voltage of (Equation 7) is applied to the signal 57 and the voltage of (Equation 8) is applied to the signal 58 from only one oscillator 46, that is, for output of each channel. A constant voltage higher than the power supplies 10 and 11 (a voltage obtained by subtracting two diode voltages from the voltage V9 of the power supply 9) can be generated in the signals 57 and 58, and the configuration is the same for all channels. The signals 51, 52, 53 from the first dead time generating circuit 47 set the voltage of the power source 9 lower than the gate-source breakdown voltage of the N-channel MOS transistors 14, 15, 16 to the H level, and the P-channel MOS transistor 22 A voltage higher than the gate-source breakdown voltage of the P-channel MOS transistor 22 is not applied between the gate and the source by the resistors 40 and 41 and the Zener diode 34. Way, a structure obtained by inserting a Zener diode for breakdown voltage protection current can be restricted by the on-resistance of the P-channel transistor 22 between the gate and source of the N-channel MOS transistor 13.

  As a result, for each channel, one oscillator can be shared without requiring separate oscillators for generating signals 57 and 58, and signals 51 to H whose H level is the voltage of power supply 9 can be used. Even when the voltage of the signal 57 is higher than the gate-source breakdown voltage of the MOS transistor constituting the circuit when the gate of the N-channel MOS transistor 13 is driven by the signal whose level is converted to the signal 57, each MOS A voltage higher than the breakdown voltage between the gate and the source is not applied to the transistor (the same applies to other channels).

  Further, the gates of the N-channel MOS transistors 13 and 17 are voltages higher than the power sources 10 and 11 by the voltage obtained by subtracting two diodes from the power source 9 and 11, respectively, as in (Equation 7) and (Equation 8). Can be applied to reduce the on-resistance of the N channel MOS transistors 13 and 17, and when the gates of the N channel MOS transistors 13 and 17 are at the H level, the difference voltage between the gate of the N channel MOS transistor 13 and the signal 57 can be reduced. Since the difference voltage between the N channel MOS transistor 17 and the signal 58 is the same, uniform control can be performed for each channel.

  Also, even if the current values that need to flow through the inductances 44 and 45 are greatly different, it is possible to change the voltages of the power supplies 10 and 11 and set the optimal current by using multiple oscillators or using bootstrap capacitors. It will be possible. Furthermore, in order to reduce the influence of PWM noise, it becomes easy to lower the power supply voltage for each channel as much as possible and to reduce the rate of change of the current flowing through the inductance.

  Naturally, FIG. 2 shows an example in which only one channel is driven by each of the power sources 10 and 11, but when adding a channel that requires a power source having the same voltage as the power source 10, the power source 10 and the signal 57 are shared. May be used as

  Next, as a similar example to the first embodiment shown in FIG. 2, there is a configuration like the second embodiment as shown in FIG. In FIG. 4, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72 are N channel MOS transistors, 73, 74, 75, 76, 77, 78, 79, 80, 81. , 82, 83, 84 are P-channel MOS transistors, 85, 86, 87, 88 are inverters, 89 is a third dead time generating circuit, 90 is a fourth dead time generating circuit, 91, 92, 93, 94, 95, Reference numerals 96, 97, 98, 99, and 100 denote signals.

  FIG. 5 is a timing chart of signals 93, 94, 95, and 96 which are output signals from the first input terminal and the first to fourth output terminals of the third dead time generating circuit. The pulse of the timing relation which does not produce a through-current in is output. The same applies to the output signal from the fourth dead time generation circuit 90.

  In the second embodiment, the voltages of the signals 91 and 92 are applied as they are between the gate and source of the MOS transistor in the level shift circuit using the signals 91 and 92 as a power source. There is a limit to the maximum allowable voltage of 91,92.

  However, the other effects are the same as those of the first embodiment, and the circuit configuration from the signals 93 and 94 to the gate of the N-channel MOS transistor 13 and the signals 95 and 96 to the gate of the N-channel MOS transistor 14 are achieved. Since the circuit configuration is exactly the same including the power supply, it becomes easy to design the timing relationship between the signal of the gate of the N-channel MOS transistor 13 and the signal of the gate of the N-channel MOS transistor 14, and the through current in the N-channel MOS transistors 13 and 14 is reduced. A configuration that does not occur is easy to implement.

  The bridge type drive circuit according to the present invention realizes a high output voltage of the charge pump circuit, reduces the on-resistance of the N-channel MOS transistor constituting the bridge type drive output circuit, and makes the charge pump circuit configuration of one oscillator pulse. Since multiple voltages are generated for each of multiple output power supply voltages at the output, multiple charge pump circuits are not required for multiple channels with different output power supply voltages, and many of the necessary bootstrap configurations are required for multiple channels. This eliminates the need for the capacitor, so that a plurality of inductance loads can be driven by outputs of a plurality of bridge circuits having different power supply voltages, and can be configured using a high power supply voltage, which is useful as a bridge-type drive circuit or the like.

1 is a circuit diagram showing an outline of a basic configuration of a bridge-type drive circuit according to Embodiment 1 of the present invention. The circuit diagram which shows the detailed structure of the bridge type drive circuit in this Embodiment 1. Timing chart showing input / output signals of the first input terminal and the first to third output terminals of the first dead time generating circuit constituting the bridge type driving circuit according to the first embodiment. The circuit diagram which shows the detailed structure of the bridge | bridging type drive circuit in Embodiment 2 of this invention. Timing chart showing input / output signals of the first input terminal and the first to fourth output terminals of the fourth dead time generating circuit constituting the bridge type driving circuit in the second embodiment A circuit diagram showing a schematic configuration of a conventional bridge-type drive circuit Circuit diagram showing the detailed configuration of a conventional bridge-type drive circuit

Explanation of symbols

1, 2, 3, 4, 12, 13, 14, 15, 16, 17, 18, 19, 20, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 101, 102, 103, 104, 105, 106, 111, 112, 113, 114, 115, 116, 117, 118 N-channel MOS transistor 5, 9, 10, 11, 107 Power supply 6, 44, 45, 108 Inductance 7 , 38, 39, 40, 41, 42, 43, 109, 134, 135, 136, 137 Resistance 8, 110 Current 21, 22, 23, 73, 74, 75, 76, 77, 78, 79, 80, 81 , 82, 83, 84, 119, 120, 121, 122 P-channel MOS transistors 24, 25, 26, 27, 138, 139 Capacitors 28, 29, 85, 86, 8 , 88 Inverters 30, 31, 32, 33 Diodes 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133 Diodes 34, 35, 36, 37 Zener diode 46 Oscillator 47 First dead time creation Circuit 48 Second dead time generation circuit 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 60, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100 signal 89 Third dead time creation circuit 90 Fourth dead time creation circuit

Claims (2)

A power supply for a control circuit, an oscillator, a plurality of bridge-type drive output circuit groups, two or more output power supply groups serving as a power supply for the bridge-type drive output circuit group, and the output by the pulse output of the oscillator A charge pump circuit that boosts each of the voltages of the power supply group to generate a plurality of voltages, a plurality of dead time generation circuit groups that use the power supply for the control circuit as a power source, and a signal from the dead time generation circuit group A level shift circuit group that converts the signal based on the output voltage of the charge pump circuit and drives the bridge-type drive output circuit group, and a load group that is driven by the bridge-type drive output circuit group,
As a pair that combines one each of the bridge type drive output circuit group, the dead time generation circuit group, and the level shift circuit group,
The bridge-type drive output circuit group connects a third N-channel MOS transistor and a fourth N-channel MOS transistor in series, and the source of the third N-channel MOS transistor and the drain of the fourth N-channel MOS transistor The load group is driven by the connection point of
A bridge type driving circuit, wherein the charge pump circuit drives a plurality of boosting capacitors paired with the output power supply group by a pulse output of the oscillator. A power supply for a control circuit, an oscillator, a plurality of bridge-type drive output circuit groups, one or more output power supply groups serving as a power supply for the bridge-type drive output circuit group, and a pulse output of the oscillator A charge pump circuit that boosts each of the voltages of the power supply group to generate a plurality of voltages, a plurality of dead time generation circuit groups that use the power supply for the control circuit as a power source, and a signal from the dead time generation circuit group A level shift circuit group that converts the signal based on the output voltage of the charge pump circuit and drives the bridge-type drive output circuit group, and a load group that is driven by the bridge-type drive output circuit group,
As a pair that combines one each of the bridge type drive output circuit group, the dead time generation circuit group, and the level shift circuit group,
The dead time generation circuit group uses the first pulse output, the second pulse output, and the third pulse output as a first pulse output, and the first pulse output is switched from the first polarity to the second polarity after a predetermined time. The second pulse output is switched from the third polarity to the fourth polarity, and the second pulse output is switched from the fourth polarity to the third polarity. The output is switched from the second polarity to the first polarity, and the third pulse output is configured to output a polarity opposite to the second pulse output,
Each of the level shift circuit groups uses the output voltage of the charge pump circuit that has boosted the voltage of the output power supply group, which is the power supply of each of the bridge-type drive output circuit groups present as a pair, as the power supply. Is input to the gate of the first N-channel MOS transistor whose source is grounded, and between the portion generating the output voltage of the charge pump circuit and the drain of the first N-channel MOS transistor, The third pulse is composed of one or more resistors or one or more resistors and a zener diode for controlling the gate-source voltage of the first P-channel MOS transistor having a source connected to a location where an output voltage is generated. The output is input to the gate of the second N-channel MOS transistor whose source is grounded, and the first By the fourth pulse output from a connection point between the drain and the drain of the second N-channel MOS transistor channel MOS transistors, and configured to drive the bridge type driving circuit group,
The bridge-type drive output circuit group connects a third N-channel MOS transistor and a fourth N-channel MOS transistor in series, and the source of the third N-channel MOS transistor and the drain of the fourth N-channel MOS transistor A bridge type driving circuit, wherein the load group is driven by a connection point of the third N channel MOS transistor, and a Zener diode is connected between the gate and the source of the third N channel MOS transistor.

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