JP2005158694A - Wafer-based ion trap - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a monolithic structure for quadrupole ion traps each having a cavity for trap located in a thin layer structure, wherein each thin layer structure is located on a front surface of a substantially thick wafer, and has a linear dimension remarkably smaller than the width of the wafer, and the wafer provides a support part robust against the thin film structure having a small ion trap therein. <P>SOLUTION: An apparatus for an ion trap includes: a semiconductor or insulation wafer with front and back surfaces; a sequence of alternating conductive and insulation layers formed over the front surface; and a bottom conductive layer. The sequence includes top and middle conductive layers, wherein the middle conductive layer is closer to the wafer than the top conductive layer. The middle conductive layer includes a generally erected cylindrical cavity that crosses a width of the middle conductive layer. The top and bottom conductive layers cap respective first and second ends of the cavity. The top conductive layer includes a hole that forms a first access port to the cavity. The wafer includes via through the width of the wafer. The via provides another access to the cavity via the back surface of the wafer. The wafer is substantially thicker than the sequence of layers. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an ion trap and a method for manufacturing the ion trap.

  Conventional ion traps allow the accumulation of ionized particles and the separation of the accumulated ionized particles by their mass (M) to charge (Q) ratio. Accumulation of ionized particles involves applying a time-varying voltage to the ion trap so that the particles propagate along a stable trajectory in the ion trap. Separation of ionized particles typically involves applying an additional time-varying voltage to the trap so that the accumulated particles are selectively pushed out by their M / Q ratio. The ion trap can be used as a mass spectrometer because of its ability to push particles according to their M / Q ratio.

  Exemplary ion traps are described, for example, in W. W., which is incorporated herein by reference in its entirety. U.S. Pat. No. 2,939,952, issued June 7, 1960 to Paul et al.

FIG. 1 shows one type of quadrupole ion trap 10 having an axially symmetric cavity 18. The ion trap 10 includes metallic upper and lower end cap electrodes 12, 13 and a metallic central ring electrode 14 between the end cap electrodes 12, 13. The points on the inner surfaces 15-17 of the electrodes 12-14 have a transverse radius coordinate “r” and an axis coordinate “z”. These coordinates, hyperbolic equation, i.e., the central ring-shaped electrode ^14, with respect to _{^{r 2 / r 0 2 -z 2}} / z 0 2 = + 1, the end cap electrodes 12, ^{13, r} 2 / r ₀ ² −z ² / z ₀ ² = −1 is satisfied. Here, 2r ₀ and 2z ₀ are the minimum lateral diameter and minimum vertical height of the trapping cavity 18 formed by the inner surfaces 15-17. A typical trapping cavity 18 has a shape ratio r ₀ / z ₀ that satisfies (r ₀ / z ₀ ) ² ≈2, although the ratio may be smaller to compensate for the finite size of the electrodes 12-14. is there. A typical cavity 18 has a size described by a value of r _{0 in} the approximate range of about 0.707 centimeters (cm) and about 1.0 cm.

In the case of the electrode and cavity shapes described above, the electrodes 12-14 generate an electric field having a quadrupole distribution within the trapping cavity 18. One method of generating such an electric field involves grounding the end cap electrodes 12, 13 and applying a radio frequency (RF) voltage to the central ring-shaped electrode 14. In an RF electric field with a quadrupole distribution, ionized particles with a small Q / M ratio will propagate along a stable trajectory. To accumulate particles in the trapping cavity 18, the cavity 18 is applied with a voltage bias as described above, causing the particles to ionize, after which the particles are trapped via the inlet port 19 of the top end cap electrode 12. Into the cavity 18 for use. During the introduction of ionized particles, the trapping cavity 18 is maintained at a low back pressure of helium (He) gas, eg, about 10 ⁻³ Torr. Thereafter, collisions between background He atoms and ionized particles reduce particle momentum, thereby allowing such particles to be trapped in the central region of the trapping cavity 18. A low RF voltage may be applied to the lower end cap 13 to push the trapped particles out of the cavity 18 while gradually increasing the low voltage so that the accumulated particles It is selectively pushed through the exit orifice 20 by the M / Q ratio.

  In the case of the quadrupole ion trap 10, machining techniques can be used to make the hyperbolic electrodes 12-14 from a metal base piece. Unfortunately, such machining techniques are often complex and expensive due to the need for hyperbolic inner surfaces 15-17. For this reason, other types of ion traps are desirable.

  The second type of ion trap has a trapping cavity having an upright and circular cylindrical shape. This trapping cavity is also formed by the inner surface of the two end cap electrodes and the central ring-shaped electrode between the end cap electrodes. Here, the end cap electrode has a flat disk-shaped inner surface, and the ring-shaped electrode has a circular cylindrical inner surface. For such a trap cavity, applying a voltage to the central ring-shaped electrode while grounding the two end cap electrodes will result in an electric field that does not have a true quadrupole distribution. Nevertheless, by properly selecting the trapping cavity height-to-diameter ratio, the contribution of the higher number of multipoles to the resulting electric field distribution will be reduced. In particular, if the height to diameter ratio is between about 0.83 and 1.00, the octupole contribution to the electric field distribution is small, for example, if the ratio is about 0.897, this contribution disappears. For these values of shape ratio, the effect of multipole contribution with a higher number of poles is often small enough that the cavity can trap and accumulate ionized particles.

For this second type of ion trap, standard machining techniques can be used to make the electrodes from the metal matrix. This is because the electrode has a simpler surface than the complex hyperbolic surface of the electrodes 12-14 of FIG. For this reason, the fabrication of this second type of ion trap is generally less complex and less expensive than the fabrication of a quadrupole ion trap whose electrodes have hyperbolic inner surfaces.
U.S. Pat. No. 2,939,952 US Pat. No. 5,501,893

  Various embodiments provide a monolithic structure for a quadrupole ion trap whose trapping cavity is in a thin layer structure. Each thin layer structure is on the front side of a significantly thicker wafer. Thus, the ion trap has a linear dimension that is significantly smaller than the width of the wafer. The wafer is substantially thick so that it can provide a robust support for thin film structures with small ion traps therein. There are methods for fabricating new structures at low cost using integrated circuit fabrication techniques.

  One embodiment features an apparatus for an ion trap. The apparatus includes a semiconductor or insulator wafer having a front surface and a back surface, an alternating sequence of conductive and insulating layers formed over the front surface, and a lower conductive layer. The sequence includes an upper and a central conductive layer, the central conductive layer being closer to the wafer than the upper conductive layer. The central conductive layer includes a generally upright cylindrical cavity that traverses the width of the central conductive layer. The upper and lower conductive layers cover the first and second ends of the cavity, respectively. The upper conductive layer includes a hole that forms a first access port for the cavity. The wafer includes vias that penetrate the width of the wafer. Vias allow another access to the cavity through the backside of the wafer. The wafer is significantly thicker than the layer sequence.

Another embodiment features a method of making an ion trap. The method forms an alternating sequence of conductive and insulating layers on the flat front side of the wafer, etches an upright cylindrical cavity through one conductive layer of the sequence, thereby forming the central electrode of the ion trap. Including creating. The method includes forming another conductive layer over the central electrode and etching a hole through the another conductive layer to create a first end cap electrode of the ion trap. The hole forms an access port for the cavity. The method also includes etching through the backside of the wafer to create a via that allows access to the second end cap electrode for the ion trap. The second end cap electrode includes one of the other conductive layers in the sequence and the conductive region of the wafer.
In some figures, the dimensions of the features have been enlarged or reduced to show the features more clearly.
In the drawings and specification, the same reference numerals indicate parts having similar functions or properties.

  2A and 2B show a monolithic structure 22 for an array of quadrupole ion traps. The monolithic structure 22 includes a semiconductor or insulator wafer 23, such as a silicon wafer or a silica glass wafer. For clarity, the central point of the monolithic structure 22 has been omitted in FIG.

  The monolithic structure 22 includes a thin layer structure 21 on the front surface of the wafer 23. Thin layer structure 21 includes alternating sequences of conductive layers 24-26 and relatively thin insulating layers 28-30. Exemplary materials for the conductive layers 24-26 are metals, heavily doped semiconductors, conductive silicon compounds, and combinations of these materials. Exemplary conductive layers 24-26 have a thickness between about 0.2 μm and a few μm. Often, the central conductive layer 25, which determines the height of the ion trap, is thick and the upper and lower conductive layers 24, 26 are relatively much thinner. The insulating layers 28-30 electrically insulate the conductive layers 24-26 from each other and from the wafer 23. Exemplary materials for the insulating layers 28-30 are inorganic nitrides or oxides and polymer compound insulators. Exemplary insulating layers 28-30 have a thickness of less than 0.1 μm. The exemplary thin layer structure 21 has a thickness d that is about 1/10 or less than the thickness D of the wafer substrate 23. The wafer 23 has a thickness that is significantly thicker than the thin layer structure 21, ie, at least several times the thickness of the thin layer structure 21. The significantly thicker configuration allows the wafer 23 to provide physical operational support for the entire monolithic structure 22. An exemplary thin layer structure 21 on a silicon (Si) wafer has a thickness of 20 micrometers (μm) or less, preferably 5 μm or less, while an exemplary Si wafer 23 typically has a thickness of more than 250 μm. Have

  In the monolithic structure 22, the thin layer structure 21 includes an array of quadrupole ion traps. The ion trap has upper, middle, and lower end cap electrodes 32-34 formed by portions of the upper, middle, and lower conductive layers 24-26, respectively. The central electrode 33 includes an upright cylindrical hole which is an ion trap cavity 36. Each of the upper and lower electrodes 32, 33 includes cylindrical ports 37, 38 that introduce ions into the upright cylindrical trapping cavity 36 and expel the ions from the upright cylindrical trapping cavity 36, or vice versa. The trapping cavity 36 has a central axis that is transverse to the conductive layer 25.

  As used herein, an upright cylindrical cavity refers to a surface that is swept out by a straight segment when a point on the straight segment traces out a closed curve while keeping the segment perpendicular to the curved surface. Have. FIG. 2C shows an exemplary upright cylindrical cavity cross-sectional shape, ie, the shape associated with a circle C, an ellipse O, a square S, and a cut hyperbola H. In various embodiments, the trapping cavity 36 may have one of these cross-sectional shapes or other shapes. A cavity having a generally upright cylindrical shape can be created by standard mask controlled anisotropic dry etching techniques.

  Conductive layers 24-26 include electrical contacts (not shown) for applying individual bias voltages to each of electrodes 32-34. The electrical contacts are individually connected to the individual ion trap electrodes 24-26 or are connected in parallel to the individual ion trap equivalent electrodes 24-26.

  For each trapping cavity 36, one or more inlet ports 37 open out to the front of the monolithic structure 22 and one or more inlet ports 38 open to the back of the monolithic structure 22. In embodiments having one inlet port 37 and one outlet port 38 per trap cavity 36, the port diameter is less than one-half the diameter of the associated trap cavity 36, so that the port 37 , 38 do not substantially deform the approximate quadrupole field distribution of the trapping cavity 36.

  In the monolithic structure 22, the height of the trapping cavity 36 is less than the width of the thin layer structure 21. This width is usually one tenth or less of the width of the supporting wafer 23 and the height of the cavity 36 is one tenth or less of the width of the wafer 23. That is, the trapping cavity 36 is very small. Wafer 23 must be significantly thicker, eg, 10 times thicker than thin layer structure 21, so that wafer 23 provides robust physical support for an array of small ion traps. Nevertheless, the exit port 38 must be accessible through the back side of such a thick wafer 23. To address these two needs, the monolithic structure 22 includes deep vias 39 that traverse the entire width of the thick wafer 23 and allow physical access to the exit port 38 through the back of the wafer 23. The sidewalls of the deep vias 39 typically have a regular series of bump-like bumps 40 that indicate the repetitive steps of the deep etch process used to create such deep vias 39.

The operation of the quadrupole ion trap of the monolithic structure 22 is the same as the operation of the conventional quadrupole ion trap. Accumulating molecules in the ion trap introduces ionized molecules into the trap cavity 36 by projecting a molecular flow toward the inlet port 37 while colliding the molecules with electrons (causing ionization). Including doing. The ionized molecules then enter the trapping cavity 36 via the port 37. Accumulating molecules can also be performed while applying an RF voltage to the central electrode 33 such that a trapping RF electric field exists in each trapping cavity 36 when ionized particles are introduced into the trapping cavities 36. Including grounding the cap electrodes 32 and 34. Each trapping cavity 36 has a shape that ensures that the trapping electric field in the cavity closely approximates the quadrupole field distribution. For an upright circular cylindrical trapping cavity 36 whose height-to-diameter ratio is in the range of about 0.83 to about 1.0, preferably approximately equal to 0.897, the voltage bias scheme described above is typically , An electric field whose distribution closely approximates the electric field of the quadrupole distribution of the trapping cavity 36 is generated. Accumulating molecules also includes maintaining a low pressure of helium (He) in the trapping cavity 36, eg, 10 ⁻³ Torr, while ionized particles are introduced into the cavity. The He atoms of the gas collide with the introduced ionized molecules, thereby reducing the molecular momentum so that the molecules can be trapped in the central region of the trapping cavity 36. Extruding ionized molecules from the trapping cavity 36 may increase the amplitude of the RF voltage that biases the central electrode and / or lower end to resonate the ions trapped through the exit port 38. Applying a smaller RF voltage to the cap electrode 34.

  Various embodiments of the monolithic structure 22 provide several advantages over conventional ion traps. First, the trap cavity 36 is generally small, which means that the bias voltage during operation is usually low. For this reason, the ion trap of the monolithic structure 22 typically consumes electrical energy at a lower rate during operation. Second, the small size of the ion trap may help to incorporate the monolithic structure 22 into a new type of device, such as a handheld mass spectrometer. Third, some embodiments of the monolithic structure 22 incorporate multiple ion traps. Some of these large arrays must accumulate ions at a higher surface density than traditional single ion traps because ion traps typically only accumulate ions in the central portion of the trapping cavity. . The accumulation of higher surface density allows the creation of mass spectrometers with higher sensitivity and / or mass sweep rate.

  FIG. 3 illustrates a monolithic structure including a thin layer structure for one or more ion traps and / or to support a relatively thick wafer, eg, the structure 22 of FIGS. 2A and 2B. Method 41 is shown. In the final fabricated structure, each ion trap has a trapping cavity formed by two end cap electrodes and one central electrode such that the central electrode is between the end cap electrodes.

  The method 41 includes forming alternating sequences of conductive and insulating layers (step 42) on a flat front surface of an insulator or semiconductor wafer. In the sequence, the one or more insulating layers are significantly thinner than the one or more conductive layers. The insulating layer allows one or more conductive layers to be electrically isolated from each other, and the one or more conductive layers can be isolated from the underlying conductive surface region of the wafer. Forming the one or more conductive layers includes vapor deposition-depositing a metal, chemical vapor deposition (CVD) of a doped semiconductor, and / or depositing a conductive silicon compound. If the sequence includes a single conductive layer, forming the sequence also first forms a conductive surface region on the wafer, for example by implant doping a surface portion of the silicon wafer. Next, annealing the wafer to activate the buried dopant atoms. Forming the one or more insulating layers includes chemical vapor deposition of oxides or nitrides, or spin coating and curing of the polymeric precursor layer.

  The method 41 includes dry etching (step 43) an upright cylindrical cavity through at least one conductive layer of the sequence to create an ion trap central electrode. The central electrode may include a single conductive layer or two or more adjacent conductive layers. Either the underlying conductive layer of the sequence or the conductive surface area of the wafer forms the lower end cap electrode of the cavity.

  Method 41 includes forming an upper conductive layer over the central electrode (step 44). Forming the upper conductive layer involves performing one of the processes for forming the conductive layer described in step 42 above. If the underlying layer sequence does not include an upper insulating layer, another deposition creates a layer that allows the subsequently formed upper conductive layer to be electrically isolated from the underlying central electrode of the ion trap. The top conductive layer and the underlying sequence of conductive and insulating layers together form a thin layer structure that will contain the trapping cavities of the final ion trap.

  Prior to forming the top conductive layer, the method 41 may include forming a sacrificial material layer that fills the cavity of the central electrode and covers the top end of the cavity to create a flat top surface. An exemplary process for forming the sacrificial material layer includes depositing a sacrificial material and then performing a chemical mechanical polishing (CMP) process to create a flat top surface on the sacrificial material. The flat top surface allows a subsequent deposition step to create a suitable surface for the flat bottom surface for the top conductive layer, ie, the end cap electrode of the upright cylindrical trapping cavity. After forming the top conductive electrode, another etch will remove the sacrificial material from the trapping cavities.

  As used herein, sacrificial material refers to a material that is added to an intermediate structure to provide structural support in subsequent fabrication steps, and is then substantially removed before the final structure is completed.

  Method 41 includes dry etching (step 45) through the top conductive layer to complete the fabrication of the top end cap electrode for the ion trap. The etched holes form an upright cylindrical cavity, ie, one access port to the trapping cavity.

  Method 41 also includes performing a deep etch (step 46) through the backside of the wafer to create a deep via that provides physical access to the lower end cap electrode of the trap. The deep via is aligned to expose the second port, ie, the port at the lower end cap electrode, to the trapping cavity. The lateral length of the deep via is limited so as not to sacrifice the structural operational support provided by the thick wafer. Performing a deep etch is a mask-controlled series of shallow plasma etches with a depth of, for example, 2-3 μm and high until the resulting vias cross the entire thickness or almost the entire thickness of the wafer. Including alternately performing molecular compound deposition. Deep etching forms a back via with substantially vertical walls and typically exposes the portion of the lower electrode of the ion trap. The deep via sidewalls will have a regular series of bump-like bumps showing the series of repeated etch and polymer deposition steps used to create the deep via. An exemplary method for deep etching of the wafer is described in F.W. No. 5,501,893 (the '893 patent), issued March 26, 1996 to Laermer et al., Which is incorporated herein by reference in its entirety.

FIG. 4 shows an embodiment of a mass spectrometer 2 that incorporates an array of quadrupole ion traps. The mass spectrometer 2 includes a vacuum pump 3, a sprayer 4, the monolithic structure 22 of FIGS. 2A and 2B, an electron gun 5, a vacuum vessel 6, a variable voltage source 7, an ion detector 8, and a computer 9. The nebulizer 4 injects molecules onto the top surface of the monolithic structure 22 for accumulation in the ion trap. The electron gun 5 causes the atomized molecules to collide with electrons in order to cause ionization. The nebulizer 4 and the electron gun 5 are configured such that a portion of the ionized molecules enter the inlet port 37 to the trapping cavity 36 of the monolithic structure 22. The vacuum pump 3 and the container 6 maintain the pressure in the ion trap and in the vicinity of the connected inlet and outlet ports 37, 38 at a low pressure of, for example, 10 ⁻³ Torr or less. The variable voltage source 7 appropriately biases the trap electrode of the monolithic structure 22 in order to accumulate ionized molecules and / or push out the accumulated ionized molecules at a selected Q / M ratio. The ion detector 8 is adjacent to the rear side of the monolithic structure 22 and is spatially separated so that ions from different exit ports 38 of the monolithic structure 22 are detected at individual segments of the ion detector 8. . The computer 9 operates the pump 3, the atomizer 4, the electron gun 5, and the variable voltage source 6, receives ion count data from the ion detector 7, and uses that data to determine the Q / M for the detected ionized particles. Find the ratio and bundle.

  Various embodiments of the mass spectrometer 2 provide an advantageous method for analyzing mass spectra. In some embodiments, mass analysis is performed in a bulk mode in which multiple ion traps of the monolithic structure 22 have an equivalent voltage bias. In bulk mode, multiple ion traps accumulate and / or push out simultaneously with the same Q / M ratio. The presence of an ion trap that operates equivalently in this way increases the overall sensitivity of the mass spectrometer 2, for example, and enables faster spectral analysis than an equivalent mass spectrometer that uses only a single ion trap. . In some embodiments, the mass spectrometry is performed in a parallel mode in which unequal voltage biases are applied to different ion traps of the monolithic structure 22. In parallel mode, different ion traps accumulate and / or push out ions with different Q / M ratios. This allows different ion traps of the monolithic structure 22 to analyze individual parts of the QM spectrum, ie parallel spectral analysis. The parallel mode allows a faster sweep of the mass spectrum of the sample gas being analyzed.

FIG. 5 illustrates an exemplary method 50 for making a monolithic structure 22 ′ having an array of micro ion traps according to the method 41 of FIG. The method 50 includes performing first and second sequences of steps I and II from the front and back surfaces, respectively, of a silicon (Si) support wafer 23. The process creates structures 71-77, 22 'of FIGS. In FIGS. 6-13, the gap “G” indicates the portions of structures 71-77, 22 ′ that have been omitted for clarity.
From the front side of the Si wafer 23, the method 50 includes performing the following sequence of fabrication steps.

  Initially, the structure 71 of FIG. 6 containing the sequence of layers is created by depositing layers on a series of wafers 23 and a series of dry etching (step 51). The sequence includes a conductive Al layer 90 and a relatively thin insulating layer 91-92 surrounding the Al layer 90. The lateral portion of the Al layer 90 will form the bottom end cap electrode of the final ion trap. The Al layer 90 includes a circular hole 93 that will be the exit port of the ion trap and an electrical contact 94 for the lower end cap electrode. Wafer 23 is a standard Si wafer having an initial thickness of about 750 μm.

To create the structure 71, a series of layer depositions includes depositing a SiO ₂ layer 91 to a thickness of about 0.2 μm, depositing an aluminum (Al) layer 90 to a thickness of about 0.3 μm, and Depositing a SiO ₂ layer 92 to a thickness of about 0.1 μm. The deposition for the SiO ₂ layers 91, 92 is a plasma enhanced chemical vapor deposition (PECVD) performed at about 250 ° C to 400 ° C. Deposition for the Al layer 90 is physical vapor deposition (PVD), sputter deposition at 20 ° C. to 250 ° C., or evaporation-deposition.

To make structure 71, a series of dry etches are controlled by photoresist mask 89, reactive ion (RIE) plasma etch stopping on oxide and residual exposure of SiO ₂ layer 91. Includes a second RIE plasma etch to remove portions. The portion of the mask 89 defines an outlet port 93 and an electrode contact 94. A typical outlet port 93 has a diameter of about 0.33 μm. After dry etching, a conventional plasma or wet strip removes the photoresist mask 89.

Next, a second conductive Al layer 95 and an upper insulating layer 96 for the central electrode of the ion trap are formed by a series of depositions on the structure 71 as shown in the structure 72 of FIG. 7 (step 52). . To form layers 95 and 96, an Al layer 95 having a thickness of about 1.0 μm is first formed on structure 71 by deposition. Next, an insulating layer 96 is formed by depositing a SiO ₂ layer or silicon nitride of about 0.1 μm on the Al layer 95 by a second deposition. The deposition of Al and insulator involves a process of the type already discussed with respect to step 51 above.

Next, the etching sequence on the structure 72 completes the central electrode of the ion trap and the lower electrode outlet port 93 and electrical contacts 94 are re-formed as shown in structure 73 of FIG. 8 (step 53). ). The central electrode has a circular cylindrical cavity aligned on a corresponding one of the outlet ports 93. The cavity 97 has a diameter of about 1 μm. The etching sequence consists of lithographically forming a photoresist mask 98 on the structure 72, removing the exposed portion of the top insulating layer 96 by RIE plasma etching, either by mask 98 or SiO ₂ layer 92. This includes removing portions of the unprotected Al layers 95 and 90 by RIE plasma etching, and then removing the remaining exposed portions of the SiO ₂ layer 92 by RIE etching. The RIE plasma etch forms trapping cavities 97 and center electrode electrical contacts 99 and recreates the corresponding lower end cap electrode outlet ports 93 and electrical contacts 94. The etching sequence also includes plasma stripping the photoresist mask 98.

  Next, a layer of sacrificial amorphous silicon 100 is formed on the structure 73 by deposition as shown in structure 74 of FIG. 9 (step 54). The sacrificial amorphous silicon fills the central electrode trapping cavity 97. Deposition includes performing PECVD of Si at 250 ° C. to 400 ° C., sputtering deposition of Si at 20 ° C. to 250 ° C., or deposition-deposition of Si. After deposition, the top surface 101 of the structure 74 is not flat due to the non-trivial topography of the structure 73 on which amorphous silicon has been deposited.

  Next, CMP of the top surface 101 of the sacrificial material produces a structure having a smooth and flat top surface, i.e., a surface suitable as a base for fabricating the top end cap electrode (step 55). CMP uses chemicals that selectively remove the sacrificial amorphous silicon. For this reason, CMP stops on the flat surface of the insulating layer 96, thereby producing a flat top surface in the final structure.

  Next, a third conductive Al layer 102 for the upper end cap electrode is formed by deposition on the last described structure, as shown in structure 75 of FIG. 10 (step 56). Deposition uses one of the Al deposition techniques of step 51 to produce the Al layer 102 to a thickness of about 0.3 μm. The deposited Al layer 102 has a flat bottom surface because the base surface generated by depositing the sacrificial material and performing CMP is flat.

  At this point, the Al layer 102 is generally highly reflective and thus obscures any underlying optical alignment marks. In general, one or more sets of such alignment marks are formed on unused portions of layers 90-92, 95-96 and / or in substrate 23 by an etching and / or deposition process. I came. The alignment mark serves to optically align the mask used to make the structure 75. To re-expose the alignment mark, dry etching is performed on the Al layer 102 deposited over the entire area where the alignment mark was previously formed. The re-exposed alignment mark will provide an optical reference point for aligning subsequent front and back dry etch masks.

Next, the upper end cap electrode is completed by a series of two-step etching on the structure 75 as shown in the structure 76 of FIG. 11 (step 57). The first series of etches involves performing a mask controlled dry etch of the A1 layer 102 to create the inlet port 104 for the trapping cavity 97 and the contact electrode 105 for the top end cap electrode. The inlet port 104 is a cylindrical hole whose diameter is less than 0.5 times the diameter of the corresponding trapping cavity 97. For the exemplary trapping cavity 97 having a diameter of about 1.0 μm, the exemplary inlet port 104 has a diameter of about 0.33 μm or less. An optical alignment of a contact mask (not shown) used to lithographically produce the photoresist mask 103, which controls dry etching with previously formed alignment marks, is possible. Dry etching stops on the underlying SiO ₂ layer 96 and on the sacrificial amorphous silicon, thereby completing the Al top end cap electrode. Since the first Al layer 102 of the structure 75 has a flat lower surface, the final Al upper end cap electrode has a flat lower surface. A suitable dry etch for Al has already been described with respect to previous step 51. The series of etching in the second step involves performing dry etching in order to remove the exposed portion of the SiO ₂ layer 96. This second dry etching stops on the underlying SiO ₂ layer 95 and on the sacrificial amorphous silicon. A second dry etch exposes the top surface of electrical contact 98. Appropriate dry etching for SiO ₂ has already been described with respect to step 51. After two dry etches, a conventional strip removes the photoresist mask.

  Finally, the Si layer 106 having a thickness of about 0.2 μm is formed by plasma enhanced CVD so as to cover the upper surface of the thin layer structure (step 58). The Si layer 106 physically protects the thin layer structure 21 during operations corresponding to performing a sequence of steps from the back side of the wafer 23. An alternative embodiment may form a protective layer 106 of photoresist rather than Si.

The production of the trap electrode is completed by a sequence of steps from the front surface of the Si wafer 23. The fabricated end cap electrode and corresponding center electrode form a circular cylindrical cavity 97 for the ion trap. The trapping cavity 97 has a height h smaller than the thickness of the layer structure 21. In one embodiment, trapping cavity 97 has an upright circular cylindrical shape and has a height to diameter ratio in the range of about 0.83 and 1.00, preferably about 0.897. Configured so that the octupole contribution to the electric field distribution is small during operation of the ion trap.
From the back side of the wafer 23, the method 50 includes performing the following steps.

  Initially, to reduce the time required for backside etching, the thickness of wafer 35 in structure 77 is reduced from about 750 μm to about 300 μm by a conventional mechanical polishing process (step 59). After the polishing step, the wafer 23 is preferably as thin as possible for safe and convenient operation.

Next, deep deep vias 108 that expose the Al lower end cap electrodes are formed by deep etching, as shown in structure 77 of FIG. 12 (step 60). Deep etching removes any portion of the moiety and Si0 ₂ layer 91 of the Si wafer 23 which remains on the bottom of the deep vias 108. The front alignment mark provides an optical reference for aligning the contact mask used to lithographically produce the photoresist mask 110, which controls deep etching.

Performing a deep etch includes forming a photoresist mask 110 on the back side of the wafer 23, followed by a series of alternating shallow plasma etches, ie, etch and polymer deposition to a depth of 2 μm to 3 μm. Including performing. A series of plasma etch sub-processes and polymer compound deposition sub-processes create deep vias 108 with substantially vertical sidewalls 111. Exemplary conditions for the plasma etch sub-process are: a reactive gas mixture of SF ₆ and Ar, a gas flow of less than 100 sccm, a pressure of 10 ⁻⁵ to 10 ⁻⁴ bar, and 2.45 GHz for generating a plasma. 300 to 1200 watts of microwave energy. Polymer compound deposition substep is on partially etched vias, substantially uniform coating of fluorocarbon, for example, to create a layer of CHF _3. Each coating reduces lateral etching during subsequent plasma etch sub-steps. Exemplary conditions for the polymer compound deposition sub-process include a gas mixture of CHF ₃ and Ar, flow rates, pressures, and microwave irradiation conditions similar to the etching sub-process. A method for performing such deep etching on Si wafers is described in the previously incorporated '893 patent.

Next, sacrificial material is removed from both exit port 93 and trapping cavity 97 by chemical etching of structure 77 (step 61). Exemplary conditions for chemical etching include exposing the front side of structure 77 to XeF ₂ for about 10 seconds at about 2.9 torr and then venting the resulting gas for the following process: , With repetition of about 50-100 times.

  In the previous steps 59 to 61, the sacrificial material is removed from the trap cavity 97 and the outlet port 93, and the protective Si layer 106 is removed.

  In some embodiments, chemical etching proceeds from the back side or from both sides of the structure 77, thereby also removing the protective Si layer 106 from the inlet port 104. In embodiments where the backside chemical etch cleans the trapping cavity 97 and the exit port 93, another front side etch is performed to remove the protective Si layer 106, thereby removing material from the entrance port 104. This produces the final monolithic structure 22 'for the ion trap array as shown in FIG.

  In various embodiments of structure 22 ', the individual ion traps have electrical contacts that allow either a parallel trap operation or separate trap operations. In embodiments having separately operable ion traps, the front-end process sequence also creates a lateral isolation barrier between sets of electrodes for different ion traps. The barrier may be, for example, a trench that penetrates the Al layers 102, 95, 90 surrounding the individual ion traps. Etching to form trap electrodes from the Al layers 102, 95, 90 will create such trenches if the corresponding photoresist mask has the appropriate features.

  While performing method 50, preferably, Si wafer 23 and structures 71-77, 22 'are maintained at a temperature below about 200 ° C, unless otherwise specified. These low processing temperatures tend to reduce bending stresses caused by lattice mismatch between the thin layer structure 21 and the underlying Si substrate 23. Such stresses can cause substantial deflection of the Si wafer 23 when the processing steps 51-61 are advanced at high temperatures.

Another exemplary method of making the monolithic structure 22 ′ of FIG. 13 includes modifying the method 50 of FIG. 5 by replacing it with a different material. The replacement involves using doped polysilicon for the conductive layers 90, 95, 102, and using a SiO ₂ or spin-on curable polymer for the sacrificial material in step 54. For such replacement, the sequence of the front side process requires the following changes. Deposition for the conductive material of layers 90, 95, 102 involves performing a plasma enhanced CVD deposition for polysilicon doped n-type or p-type with 10 ¹⁹ or more dopant atoms / cm ³ . Dry etching to form features in the conductive material of the doped polysilicon layers 90, 95, 102 involves performing a conventional RIE plasma etch adapted to selectively remove the polysilicon. CMP for planarizing the upper surface 101 of the intermediate structure 74 of FIG. 9 uses chemical polishing chemicals that selectively remove the cured polymeric compound of SiO2 or sacrificial material. The backside chemical etch to remove the sacrificial material is performed under conditions designed to remove chemicals and, if appropriate, the SiO ₂ or spin-on curable polymer (eg, HF wet etch is SiO ₂ sacrificial Is suitable for the material).

In other embodiments, the thin layer structure 21 and the trapping cavities have other sizes, but the height to diameter ratio of the cavities may be increased to reduce the magnitude of the octupole contribution to the trapping field. It is preferable to be in the range described in.
Other embodiments of the invention will be apparent to those skilled in the art in light of the specification, drawings, and claims of the present application document.

It is sectional drawing of the conventional quadrupole ion trap. FIG. 6 is a partial cross-sectional view of a monolithic structure having an array of quadrupole ion traps. 2B is a cross-sectional view of a portion of the monolithic structure according to FIG. 2A where the thin layer structure and relative thickness of the wafer are shown. 2B illustrates an exemplary cross-sectional shape of the monolithic trapping cavity of FIG. 2A. FIG. 3 is a flow chart illustrating a method for fabricating an array of quadrupole ion traps on a wafer. FIG. 2 illustrates one embodiment of a mass spectrometer incorporating an array of quadrupole ion traps. FIG. 4 is a flow chart illustrating a particular method of fabricating a monolithic structure for an array of quadrupole ion traps according to the method of FIG. FIG. 6 is a cross-sectional view of an intermediate structure created during the fabrication method of FIG. 5 and related fabrication methods. FIG. 6 is a cross-sectional view of an intermediate structure created during the fabrication method of FIG. 5 and related fabrication methods. FIG. 6 is a cross-sectional view of an intermediate structure created during the fabrication method of FIG. 5 and related fabrication methods. FIG. 6 is a cross-sectional view of an intermediate structure created during the fabrication method of FIG. 5 and related fabrication methods. FIG. 6 is a cross-sectional view of an intermediate structure created during the fabrication method of FIG. 5 and related fabrication methods. FIG. 6 is a cross-sectional view of an intermediate structure created during the fabrication method of FIG. 5 and related fabrication methods. FIG. 6 is a cross-sectional view of an intermediate structure created during the fabrication method of FIG. 5 and related fabrication methods. FIG. 3 is a cross-sectional view of a monolithic structure in which an array of quadrupole ion traps is fabricated on a silicon wafer.

Claims (10)

A semiconductor or insulator wafer having a front surface and a back surface;
An alternating conductive and dielectric sequence of conductive and insulating layers formed over the front surface, the sequence including an upper and a central conductive layer, the central conductive layer being more than the upper conductive layer Alternating sequence of conductive and insulating layers close to the wafer;
A device comprising a lower conductive layer,
The central conductive layer has a generally upright cylindrical cavity across the width of the central conductive layer; the upper and lower conductive layers cover the first and second ends of the cavity;
The upper conductive layer includes a hole forming a first access port to the cavity;
The wafer includes a via that penetrates the width of the wafer, the via including a via that allows access to the cavity through the back surface of the wafer, the wafer being significantly more than the sequence of layers. Thick device.   The apparatus of claim 1, wherein the sequence comprises the lower conductive layer covering a second end of the cavity.   The apparatus of claim 1, wherein the wafer comprises a conductive region forming the lower conductive layer covering the second end of the cavity.   The apparatus of claim 1, wherein the cavity has a circular cross section. The central conductive layer includes a second cylindrical cavity that crosses the width of the central conductive layer, the upper conductive layer that covers a first end of the second cavity, and the lower that covers a second end of the two cavities. A conductive layer,
A second hole extending through the upper conductive layer forms a first access port for the second cavity;
The apparatus of claim 1, wherein vias that penetrate the width of the wafer allow access to the second cavity through the backside of the wafer. A method of making an ion trap,
Forming an alternating sequence of conductive and insulating layers on a flat front surface of an insulator or semiconductor wafer;
Etching an upright cylindrical cavity through one conductive layer of the sequence, thereby creating a central electrode of an ion trap;
Forming another conductive layer over the central electrode;
Etching a hole through the another conductive layer to create a first end cap electrode of the cavity, the hole forming an access port to the cavity, etching the hole ,and,
Etching through the backside of the wafer to create a via that allows access to the second end cap electrode for the cavity, wherein the second end cap electrode is another in the sequence A method comprising one of a conductive layer and a conductive region of the wafer. Depositing a sacrificial material to fill the cavity and creating a flat top surface over the end of the cavity before performing the formation of another conductive layer; and
The method of claim 6, further comprising etching the sacrificial material from the cavity after performing the formation of another conductive layer.   7. The method of claim 6, further comprising etching one of the other conductive layers of the sequence and the conductive region of the wafer to form the second access port of the cavity.   The method of claim 6, wherein the second end cap electrode is another conductive layer of the sequence. Forming a sequence
Forming another conductive layer of the sequence over the surface of the wafer;
Forming one insulating layer on another conductive layer of the sequence;
10. The method of claim 9, further comprising subsequently forming the one conductive layer of the sequence on the one insulating layer.

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