KR20160053115A - Apparatus for Trapping Ion Using Sacrificial Layer and Method for Fabricating the Same - Google Patents

Abstract

The purpose of the present invention is to fabricate an ion trapping structure minimizing an area in which a sidewall of an insulating layer is exposed to an ion trapping position by realizing an electrode overhang having a uniform and accurate length on an ion trapping electrode through a sacrificial layer process, and is to improve performance and stability of trapping through the ion trapping structure. An embodiment of the present invention provides an apparatus for trapping ions by using a sacrificial layer and a method for fabricating the same. The apparatus for trapping ions comprises: one or more central DC electrodes including a DC connection pad on a semiconductor substrate and a DC rail connected to the DC connection pad; an RF electrode which includes at least one RF rail disposed adjacent to the DC rail and an RF pad connected to the at least one RF rail; at least one lateral electrode which includes at least one lateral electrode pad disposed opposite to the central DC electrode with respect to the RF electrode; and an insulating layer which is disposed between the respective electrodes and the semiconductor substrate and supports the respective electrodes. At least one among the respective electrodes has an overhang which protrudes from the insulating layer in a widthwise direction.

Description

TECHNICAL FIELD [0001] The present invention relates to an ion trap device using a sacrificial layer,

An embodiment of the present invention relates to an ion trap apparatus using a sacrificial layer and a method of manufacturing the same.

The contents described in this section merely provide background information on the embodiment of the present invention and do not constitute the prior art.

A major limitation of the currently commercially implemented Quantum Key Distribution (QKD) system is that there is a limit to the distance that a single photon can send at one time due to attenuation while passing through the optical fiber. In order to overcome this disadvantage, it is necessary to amplify the signal using a quantum repeater. The ion trap is one of the most popular methods of implementing a quantum memory, which is essential for the fabrication of a quantum repeater.

1 is a view for explaining the principle of a three-dimensional trap.

The ion trap can be variously shaped according to the arrangement of the electrodes, but it can be explained basically as the shape of the field generated by the four electrodes (e1, e2, e3, e4) as shown in FIG. 1 (a), when an e1 and an e4 are grounded and a high-voltage RF signal is applied to e2 and e3, an electric field as shown in Fig. 1 (b) is formed, and the electric field E The direction changes continuously. At this time, if the amount of electric charge, the mass, the intensity of electric field, and the RF frequency satisfy a specific mathematical condition, the electrically charged particles are averaged in the middle of the electrodes (e1, e2, e3, e4) And the potential created by this average force is called the ponderomotive potential.

1 (c) is a view showing the shape of a panda-shaped motive potential formed between the electrode rods e1, e2, e3 and e4. Here, the panda-motive potential is independent of the sign of the charge trapped between the electrode rods e1, e2, e3, and e4. The potential thus created pulls the charge away from the z axis steadily toward the center, but does not specify where along the z axis the charge particles will be trapped. Therefore, in order to trap the charged particles at the same position as in FIG. 1 (a), a voltage is applied so that the relationship of V1 > V2 is established instead of e1 and e4 being grounded.

FIG. 2 (a) is a view for explaining the principle of a two-dimensional trap, and FIG. 2 (b) is a view showing a direction of an electric field to be generated and a motive potential corresponding to the direction.

The ion trap device having a three-dimensional structure as shown in FIG. 1 is difficult to precisely fabricate and it is difficult to integrate a plurality of traps. Therefore, a modification is made to a design that can be fabricated on a two-dimensional wafer using a MEMS process for application of quantum information. 2 (a) shows a method of performing conformal mapping on a two-dimensional electrode in one dimension. 2 (a), when an RF voltage is applied to the red portion of the circumference and the rest of the circumference is grounded, an electric field similar to that of FIG. 1 (b) is formed inside the circle. In this case, as shown in FIG. 2 (a), by extending the tangent of the RF electrodes on the circumference, finding the portion intersecting the underlying line, applying an RF voltage to these portions and grounding the remaining portion, 2 (b) shows the direction of the electric field generated when the electrodes are arranged in one dimension as shown in FIG. 2 (b) and the motive potentials corresponding to the directions of the electric fields Put RF on the red electrodes and ground both outside and center of the RF).

When the electrode structure is fabricated using the above-described principle, charged particles are trapped at the triangular display position of FIG. 2 (b).

The structure of the ion trap fabricated by the MEMS process technology is largely divided into an insulating layer between the electrode and the electrode. During ion trap fabrication or ion capture experiments, unexpected atoms can be deposited on the sidewalls of the insulation layer, which transforms the electric field to cause micromotion of the trapped ions. The fine movement of the ions increases the heating rate of the ions and increases the probability of leaving the captured ions.

In order to solve such a problem, an embodiment of the present invention provides an ion trap structure in which uniform and precise electrode projections are realized through a sacrificial layer process in the ion trap electrode, thereby minimizing the area of the side wall of the insulating layer exposed at the ion trap position And to improve the performance and stability of traps.

In order to accomplish the above object, one embodiment of the present invention provides a semiconductor device comprising: at least one central DC electrode comprising a DC connection pad on a semiconductor substrate and a DC rail connected to the DC connection pad; An RF electrode including at least one RF rail positioned adjacent to the DC rail, and an RF pad coupled to the at least one RF rail; At least one lateral electrode comprising at least one lateral electrode pad located on the opposite side of the DC electrode with respect to the RF electrode; And an insulating layer for supporting the electrodes between the electrodes and the semiconductor substrate, wherein at least one of the electrodes has an overhang protruding in the width direction from the insulating layer. Thereby providing a trap device.

Wherein the central DC electrode comprises a first central DC electrode and a second central DC electrode, the first DC rail being a DC rail of the first central DC electrode and the second DC rail being a DC rail of the second central DC electrode, The first DC rail and the second DC rail being spaced apart from each other and having a trap region, and the semiconductor substrate portion corresponding to the trap region is penetrated.

Here, the electrode having the protrusion may be an electrode adjacent to the trap region, and the protrusion may protrude in a direction toward the trap region.

The at least one side electrode is arranged at a predetermined interval in the longitudinal direction of the RF electrode, and the side wall of the insulating layer supporting the at least one electrode has a flat shape.

According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, including: depositing an insulating layer on a semiconductor substrate; Forming an insulating layer pattern for supporting the electrode by patterning the insulating layer using a first mask; And forming an electrode pattern including an RF electrode, a central DC electrode, and a lateral electrode on the insulating layer pattern by depositing a conductive layer on the semiconductor substrate and using a second mask, And the second mask has an electrode pattern formed such that at least one of the electrodes has an electrode protrusion (Overhang) protruding from the insulating layer in the width direction of the ion trap device do.

The method may further include filling a space between the insulating layer patterns with a sacrificial layer and then planarizing the upper surface of the semiconductor substrate through a polishing process after the process of forming the insulating layer pattern, And selectively floating the sacrificial layer material to float the electrode protrusions after the sacrificial layer material is formed.

As described above, according to the embodiment of the present invention, it is possible to improve the performance and stability of the trap of the charged particle by minimizing the exposure of the side wall of the insulating layer by fabricating an electrode protrusion having uniform and precise length at the time of trapping charged particles such as ions .

1 is a view for explaining the principle of a three-dimensional trap.
FIG. 2 (a) is a view for explaining the principle of a two-dimensional trap, and FIG. 2 (b) is a view showing a direction of an electric field to be generated and a motive potential corresponding to the direction.
3 is a view for explaining a structure of an electrode protrusion implemented by a wet etching process in a planar ion trap.
4 is a view showing an ion trap apparatus 10 according to an embodiment of the present invention.
5 is a view showing a cross-section taken along the line Y-Y 'in FIG. 4 in the X direction.
6 is a flowchart illustrating a method of manufacturing an ion trap chip according to an embodiment of the present invention.
7 is a view showing the cross-sectional structure of the ion trap chip 20 after deposition of the insulating film 501 and the lower conductive layer 510 and patterning of the lower electrode.
8 is a view showing the cross-sectional structure of the ion trap chip 20 after the deposition of the insulating layer 502 and the first patterning process are performed.
FIG. 9 is a view showing a cross-sectional structure of the ion trap apparatus 10 after plating and planarization are performed.
10 is a view showing the cross-sectional structure of the ion trap device 10 after the second patterning of the upper insulating layer 502 and the etching process of the rear insulating layer 803 are performed.
11 is a view showing a cross-sectional structure of the ion trap device 10 after the deposition of the upper conductive layer and the upper electrode patterning process are performed.
12 is a view showing the cross-sectional structure of the ion trap device 10 after the backside silicon etching and sacrificial layer removal processes are performed.
13 is a view showing the cross-sectional structure of the ion trap device 10 after the upper surface silicon etching process is performed.

Hereinafter, the present embodiment will be described in detail with reference to the accompanying drawings.

3 is a view for explaining a structure of an electrode protrusion of the ion trap device 300 implemented by a wet etching process in a planar ion trap.

In planar ion traps, this problem can be solved by implementing electrode overhang. The electrodes 310 and 320 supported by the insulating layer protrude from the insulating layer, thereby reducing the side wall area of the insulating layer exposed to the trapped ions and reducing the influence of ions deposited on the sidewalls on the ions.

One of the methods of implementing the electrode protrusion is a method of etching the insulating layer 330 by using a wet etching process as shown in FIG. This method is advantageous in that the process is simple, but it is difficult to precisely control the etching length because of the nature of the wet etching, so that it is difficult to precisely control the length of the protrusion. When the insulating layer 330 has a multilayer structure, There is a disadvantage that it is formed. If the length of the projecting portions of the electrodes 310 and 320 is too small, the side wall of the insulating layer 330 can not be effectively prevented from being exposed. The protruding electrodes 310 and 320 may be easily deformed if the length of the protrusions of the electrodes 310 and 320 is excessively long. Therefore, an asymmetric electric field may be formed to interfere with ion trapping, A breakdown may occur.

4 is a view showing an ion trap apparatus 10 according to an embodiment of the present invention.

4, an ion trap apparatus 10 according to an embodiment of the present invention includes a semiconductor substrate 101, one or more central DC electrodes 100 formed on a semiconductor substrate 101, RF electrodes 130 And one or more lateral DC electrodes 141, 142.

In this embodiment, the at least one central DC electrode 100 includes a first central DC electrode 110 and a second central DC electrode 120.

The first central DC electrode 110 includes a first DC connection pad 111 formed on the semiconductor substrate 101 and a first DC rail 112 connected to the first DC connection pad 111.

The second central DC electrode 120 includes a second DC connection pad 121 formed on the semiconductor substrate 101 and a second DC rail 122 connected to the second DC connection pad 121.

The first DC rail 112 and the second DC rail 122 each have an elongated shape and are spaced apart from each other by a predetermined distance between the first DC rail 112 and the second DC rail 122 And an ion trap region 150. Meanwhile, the particles trapped in the trap region 150 may include ions, and the present invention is not limited thereto, and can be applied to all charged particles.

The RF electrode 130 includes one or more RF rails and RF pads 133 on a semiconductor substrate 101. For example, the RF rail includes a first RF rail 131 and a second RF rail 132, and the first RF rail 131 and the second RF rail 132 are connected to the RF pad 133, respectively.

The first RF rail 131 and the second RF rail 132 each have an elongated shape and are wider than the first DC rail 112 and the second DC rail 122.

The one or more lateral DC electrodes 141 and 142 are disposed on the opposite side of the trap region 150 on the basis of the first RF rail 131 with a plurality of first lateral electrodes 141 and a second RF rail 132 as a reference And a plurality of second lateral electrodes 142 on the opposite side of the trap region 150.

Here, the side electrodes 141 and 142 are arranged at predetermined intervals in the longitudinal direction of the RF electrode 130, respectively. For example, the plurality of first lateral electrodes 141 and the plurality of second lateral electrodes 142 are arranged at predetermined intervals in the longitudinal direction of the first DC rail 112 and the second DC rail 122, respectively.

In this embodiment, the semiconductor substrate 101 is made of silicon (Si). The central DC electrode 100, the RF electrode 130 and the one or more lateral DC electrodes 141 and 142 are conductive layers formed on silicon (Si), and are made of metal such as tungsten, aluminum, copper, And the present invention is not limited thereto.

5 is a view showing a cross-section taken along the line Y-Y 'in FIG. 4 in the X direction.

4 and 5, an ion trap apparatus 10 according to an embodiment of the present invention includes a semiconductor substrate 101, at least one central DC electrode 110 and 120 formed on the semiconductor substrate 101, An RF electrode 130 and one or more lateral DC electrodes 141 and 142, and is symmetrical with respect to a plane indicated by Z. [

As shown in FIG. 5, the semiconductor substrate 101 and the electrode patterns 112, 122, 131, 132, 141, and 142 are electrically separated by the insulating layer 501 and the insulating layer 502.

A portion 504 of the lower conductive layer 510 formed between the insulating layer 501 and the insulating layer 502 is connected to the bonding pad portion 506 for connecting the side electrode in the ion trap device 10, A portion 504 connected to one of the first lateral electrode 141 and the second lateral electrode 142 through the second conductive layer 505 and connected to the bonding pad 506 for connecting the lateral electrode in the lower conductive layer 510 And the remaining portion 503 is connected to GND.

DC is connected to the first central DC electrode 110 and the second central DC electrode 120 in the ion trap chip 10 as shown in FIGS. 4 to 5, and a high-voltage RF power source And a voltage of an appropriate magnitude is applied to the plurality of first lateral electrodes 141 and the plurality of second lateral electrodes 142 around the position where ions are to be trapped by connecting GND to the lower conductive layer 503 Ions can be trapped.

The semiconductor substrate 101 under the trap region 150 is vertically penetrated to form a neutral atom injection port 508 to facilitate injection of neutral atoms before the ionization process.

6 is a flowchart illustrating a method of manufacturing an ion trap chip according to an embodiment of the present invention.

As shown in FIG. 6, a method of manufacturing an ion trap chip according to an embodiment of the present invention includes a process of preparing a semiconductor substrate (S610), a process of depositing a lower conductive layer and a process of patterning a lower electrode (S620) A second patterning of the upper insulating layer and a back insulating layer etching process (S650), a deposition of the upper conductive layer and an upper electrode patterning process (S660), a first patterning process (S630), a plating and planarizing process (S640) A backside silicon etching and sacrificial layer removing process (S670), and a top silicon etching process (S680).

7 is a view showing a sectional structure of the ion trap device 10 after the deposition of the insulating film 501 and the lower conductive layer 510 and the lower electrode patterning process S620 are performed after the semiconductor substrate is prepared (S610) 8 is a sectional view of the ion trap device 10 after the insulating layer 502 is deposited and the first patterning process S630 is performed. 10 shows a sectional structure of the ion trap device 10 after the second patterning of the upper insulating layer and the etching process of the rear insulating layer S650 are performed FIG. 11 is a cross-sectional view of the ion trap device 10 after depositing the upper conductive layer and performing the upper electrode patterning process (S660). FIG. 12 is a cross- S670) is performed, the cross-sectional structure of the ion trap device 10 And tanaen figure, 13 is a view showing a sectional structure of the upper surface of the silicon etching process, the ion trap device (10) after the (S680) is performed.

7, the insulating film 501 is deposited on the top and back surfaces of the semiconductor substrate 101 to insulate the semiconductor substrate 101 from the lower conductive layer 510 and to compensate for stress. In this embodiment, the insulating film 501 is composed of the silicon dioxide film 703 and the silicon nitride film 704, but the insulating film 501 is not limited to this, and various materials can be used. As the deposition method, it is possible to use CVD (Chemical Vapor Deposition) or plasma enhanced chemical vapor deposition (PECVD), but the present invention is not limited thereto.

A lower conductive layer 510 is deposited on the upper insulating layer 501. In this embodiment, the lower conductive layer 510 may be formed of aluminum. However, the lower conductive layer 510 may be formed of a conductive material such as tungsten, aluminum, gold or the like, and polysilicon. However, the present invention is not limited thereto. Meanwhile, the lower conductive layer 510 may be deposited using a method such as sputtering or evaporation.

Then, a position corresponding to the trap region 150 of the ion trap device 10 to be fabricated on the upper surface is patterned to remove the lower conductive layer 510 and the insulating film 501 of the corresponding portion. Here, as a method of removing the lower conductive layer 510 and the insulating film 501 at a position corresponding to the trap region, dry etching using plasma may be used, but the present invention is not limited thereto.

8, insulating layers 502 and 803 are deposited on the upper surface and the rear surface of the semiconductor substrate 101, respectively, and a mask for forming the upper insulating layer pattern is used in the insulating layer deposition and the first patterning process A region 805 for separating the central DC electrode 100 and the RF electrode 130 from the insulating layer 502 on the upper surface of the trap region 150, an RF electrode 130 and a plurality of lateral DC electrodes 141, And the region 807 corresponding to the bonding pad 506 are patterned and etched. The material for forming the upper and lower insulating layers 502 and 803 may be tetraethyl orthosilicate (TEOS) or silicon dioxide (SiO ₂ ) deposited by a plasma chemical vapor deposition (PECVD) method, but is not limited thereto.

As shown in FIG. 9, in the process of plating and flattening, a region 805 separating the central DC electrode and the RF electrode under the trap region 150 etched in the insulating layer 502, that is, in the insulating layer 502 A region 806 for separating the RF electrode from the plurality of side DC electrodes and a region 807 corresponding to the bonding pad portion are filled with a sacrificial layer and subjected to a chemical mechanical polishing (CMP) process The upper surface of the semiconductor substrate 101 is planarized to form a sacrificial layer 910 structure that supports the overhang of the upper electrodes 110, 120, 130, 141 and 142. The material forming the sacrificial layer 910 may be, but is not limited to, a metal such as copper, tungsten, nickel, and the like. The material forming the sacrificial layer 910 may be formed on the upper electrodes 110 and 120 so as not to damage the other structures constituting the ion trap device 10 in the process of removing the sacrificial layer 910 through the subsequent wet etching. , 130, 141, and 142) are selected as materials having wet etching characteristics different from those of other structures. The sacrificial layer 910 may be formed by a plating process, but the present invention is not limited thereto.

10, in the second patterning of the upper insulating layer 502 and the etching of the rear insulating layer 803, the upper insulating layer 502 is electrically connected to the via hole 508 for connecting to the lower conductive layer of the bonding pad 506, And the region of the rear insulating layer 803 corresponding to the neutral atom injection port 508 is patterned and removed. At this time, the region of the insulating film 501 on the rear surface corresponding to the neutral atom injection opening 508 can also be removed.

11, in the process of depositing the upper conductive layer and patterning the upper electrode, the RF electrode 130, the central DC electrode 100, and the upper electrode layer 130 are formed using a mask for depositing the upper conductive layer 1150 and forming an electrode pattern, Thereby forming an electrode pattern including the side DC electrodes 141 and 142. In the deposition process of the upper conductive layer 1150, the side DC electrodes 141 and 142 and the bonding pad 506 for connecting the side electrodes present in the lower conductive layer 510 are connected to the upper conductive layer region 503 filled in the via hole 505, (Not shown).

In the upper electrode patterning process, the pattern width of each of the electrodes 110, 120, 130, 141, and 142 is changed to the insulating layer 502 supporting the electrodes 110, 120, 130, 141, and 142 of the upper conductive layer 1150, The difference between the pattern width of the electrodes 110, 120, 130, 141, and 142 and the width of the pattern of the supporting insulating layer 502 is greater than the width of the upper electrode protrusions 1153 and 1154 ). In addition, the upper electrode protrusions 1153 and 1154 can be stably supported by the sacrificial layer structure 910, thereby achieving a uniform and accurate length of the upper electrode protrusions 1153 and 1154. The area of the sidewall of the insulating layer exposed to the ions trapped by the projections can be reduced.

Here, the width of the pattern means the length (i.e., width) of the first DC rail 112 and the second DC rail 122 in a direction perpendicular to the longitudinal direction. For example, in the mask for forming the upper insulating layer pattern, the width of the pattern of the upper surface insulating layer 502 may be set to a width of the electrode 110, 120, 130, 142 in the mask for forming the pattern of the electrodes 110, 120, 141, and 142 are longer.

Particularly, only the widths of the first DC rail 112, the second DC rail 122, the first RF rail 131, and the second RF rail 132 among the electrodes 110, 120, 130, 141, And may have an overhang in the direction of the arrow. In some cases, only the electrodes adjacent to the ion trap region 150 (e.g., the first DC rail 112 and the second DC rail 122) may have projections in the width direction. It is also possible to have protrusions 1153 formed only in the direction toward the ion trap region 150.

In this embodiment, the upper conductive layer 1150 may be formed of aluminum, but may be formed of a conductive material such as tungsten, aluminum, gold or the like and polysilicon, but the present invention is not limited thereto. Meanwhile, the upper conductive layer 1150 can be deposited using a method such as sputtering or evaporation.

12, in the rear silicon etching and sacrificial layer removing process, the region corresponding to the neutral atom injection port 508 is etched from the back surface of the semiconductor substrate 101 to remove the semiconductor substrate 101 to a predetermined depth. Here, the etching method using plasma may be used as the etching method, but the present invention is not limited thereto, and etching can be performed by various methods.

Also, in the process of removing the sacrificial layer 910, a sacrificial layer 910 may be formed by using a strong acid or strong base liquid chemical that does not damage the other materials constituting the ion trap device 10 in addition to the sacrificial layer 910 The upper electrode protrusions 1153 and 1154 are floated by selective removal.

The side walls of the upper insulating layer 502 floating over the upper electrode protrusions 1153 and 1154 are formed to be flat by selectively removing the sacrificial layer 910 material as shown in FIG. 12, thereby reducing the effective area of the insulating layer side walls, The possibility of atomic deposition can be minimized.

13, the upper surface silicon etching process removes the region of the semiconductor substrate 101 corresponding to the trap region 150 by etching the trap region 150 on the upper surface of the semiconductor substrate 101. As shown in FIG. Here, as the etching method, dry etching using plasma may be used, but the present invention is not limited thereto.

The foregoing description is merely illustrative of the technical idea of the present invention, and various changes and modifications may be made by those skilled in the art without departing from the essential characteristics of the present invention. Therefore, the embodiments disclosed in the present invention are intended to illustrate rather than limit the scope of the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments. The scope of protection of the present invention should be construed according to the following claims, and all technical ideas within the scope of equivalents should be construed as falling within the scope of the present invention.

As described above, the present invention is designed to improve the performance and stability of a charged particle, such as ions, by designing the shape of the electrode so that the sidewall of the insulating layer is not exposed to trapped ions, Height is effective and useful invention.

10: Ion trap device
101: semiconductor substrate
100: central DC electrode
110: first central DC electrode
111: first DC connection pad
112: first DC rail
120: second central DC electrode
121: second DC connection pad
122: second DC rail
130: RF electrode
131: first RF rail
132: second RF rail
133: RF pad
141, 142: Side DC electrodes
150: ion trap region
300: ion trap device
310, 320: electrode
330: insulating layer
501: insulating film
502: upper surface insulating layer
503, 504: a part of the lower conductive layer
505:
506: bonding pad
508: neutral atomizing inlet
510: lower conductive layer
703: Silicon dioxide film
704: Silicon nitride film
803: rear insulating layer
805: area separating the central DC electrode and the RF electrode
806: an area separating the RF electrode and the plurality of lateral DC electrodes
807: region corresponding to the bonding pad portion
910: sacrificial layer
1150: upper conductive layer
1152: upper conductive layer region filled in the via hole region
1153, 1154: upper electrode protrusion

Claims (10)

At least one central DC electrode comprising a DC connection pad on the semiconductor substrate and a DC rail connected to the DC connection pad;
An RF electrode including at least one RF rail positioned adjacent to the DC rail, and an RF pad coupled to the at least one RF rail;
At least one lateral electrode comprising at least one lateral electrode pad located on the opposite side of the DC electrode with respect to the RF electrode; And
And an insulating layer for supporting the electrodes between the electrodes and the semiconductor substrate,
Wherein at least one of the electrodes has an overhang protruding in the width direction from the insulating layer. The method according to claim 1,
Wherein the central DC electrode comprises a first central DC electrode and a second central DC electrode,
Wherein a first DC rail as a DC rail of the first central DC electrode and a second DC rail as a DC rail of the second central DC electrode are spaced apart from each other to have a trap region between the first DC rail and the second DC rail ,
And the semiconductor substrate portion corresponding to the trap region penetrates the ion trap device. 3. The method of claim 2,
Wherein the electrode having the protrusion is an electrode adjacent to the trap region. 3. The method of claim 2,
Wherein the protruding portion protrudes in a direction toward the trap region. 3. The method of claim 2,
Wherein the projecting portion has a uniform length in each of the electrodes. The method according to claim 1,
Wherein the at least one lateral electrode is arranged at a predetermined interval in the longitudinal direction of the RF electrode.
The method according to claim 1,
Wherein the side wall of the insulating layer supporting the at least one electrode has a flat shape. Depositing an insulating layer on a semiconductor substrate;
Forming an insulating layer pattern for supporting the electrode by patterning the insulating layer using a first mask; And
A process of depositing a conductive layer on the semiconductor substrate and forming an electrode pattern including an RF electrode, a central DC electrode, and a lateral electrode on the insulating layer pattern using a second mask
To produce an ion trap device,
Wherein the second mask has an electrode pattern formed so that at least one of the electrodes has an electrode protrusion (Overhang) protruding from the insulating layer in the width direction of the ion trap device. 9. The method of claim 8,
Further comprising the step of filling the space between the insulating layer patterns with a sacrificial layer after the process of forming the insulating layer pattern and then planarizing the upper surface of the semiconductor substrate through a polishing process. Device manufacturing method. 10. The method of claim 9,
Further comprising the step of selectively removing the sacrificial layer material to float the electrode protrusion after forming the electrode pattern.

Images