JP2005157537A - Memory access monitoring device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory access monitoring device for freely executing optimization by erasing a memory access instruction, and for generating an efficient translation code. <P>SOLUTION: This decoder 1 decodes an instruction code, and decides whether or not the instruction code is a memory access instruction to check a frame region being the specific region of a memory. When it is decided that the instruction code is a memory access instruction to check a frame region by the decoder 1, and the memory address to be accessed by the instruction code is within a frame region set by a frame region table 3, a hit signal generating circuit 2 generates and outputs a hit signal. Therefore, it is possible to guarantee that even when the memory access instruction to perform access to any unnecessary frame region is erased, the same address as the erased memory access instruction is prevented from being accessed by the other memory access instructions. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to binary translation that dynamically converts a program (object) of another instruction set architecture into its own instruction set, and in particular, for binary translation capable of efficiently deleting memory access instructions. The present invention relates to a memory access monitoring apparatus.

  In recent years, processors that have been announced in recent years have been actively moving toward a significant performance improvement by adopting a novel architecture. One example is binary translation, which is a dynamic code conversion technique. This binary translation increases the degree of freedom between the executable code output by the compiler and the instructions executed by the microcomputer, and provides a means to free from the legacy of the legacy of code compatibility from the microcontroller's point of view. To do.

  In such a binary translation technique, if the scheduler can freely move the order of instructions, a better instruction code can be generated. The biggest constraint on moving this instruction arises from potential dependencies between memory operations. In other words, even if there is actually no dependency between memory operations, the address accessed by the microcomputer is known only at the time of execution, so the order of memory access instructions can be changed or deleted for safety. I can't do it.

  For example, if the load instruction can be moved before the store instruction, good results are obtained in many cases, such as pipeline processing. However, if the load instruction happens to read the data written by the preceding store instruction, it becomes illegal by changing the order of the instructions. Since it is difficult to detect this except during instruction execution, the translator can only perform an excessively conservative conversion.

  However, this problem can be solved by adding simple hardware. When the translator moves the load instruction before the store instruction, the translator converts the load instruction into a protect load instruction. In addition to loading the data, the address, the size of the loaded data, and the like are stored in the load protect table.

  Then, the store instruction is converted into a store instruction for checking the load protect table. In addition to storing data, the store instruction checks the load protect table. As a result of checking, if a situation occurs in which previously loaded data is overwritten, an exception is generated, and by executing the instruction again from a certain point, accurate program execution can be continued. This will be briefly described.

  If no exception occurs during the execution of the instruction and the instruction reaches the point where the order of the instructions is the same as the original instruction, the work up to that point is determined by a special instruction. This special command is called commit, and the time when the work is confirmed is called the commit time. If an exception occurs after committing, execution is guaranteed by returning to the point of last commit. For re-execution, a mechanism (store buffer) that holds the register value at the time of commit in the shadow register or delays writing to the memory after commit is required.

As a technology related to this, there is an invention disclosed in Japanese Patent Laid-Open No. 2002-312180. In this processor system, the original instruction sequence interpretation execution process flow, the instruction conversion / optimization process flow, and the original instruction sequence prefetching process flow are made independent, and a plurality of processes can be performed simultaneously in a chip multiprocessor format or by one instruction execution control unit. The processor is configured in a format that executes a flow, and a plurality of processing flows are processed in parallel. Furthermore, the instruction conversion / optimization process flow forms the converted instruction sequence in a form that generates multiple processing flows, and the original instruction sequence interpretation execution process flow is generated as an instruction conversion / optimization process flow at the time of each instruction interpretation execution. This is executed when there is a post-conversion instruction sequence corresponding to the received instruction.
Japanese Patent Laid-Open No. 2002-312180

  In the hardware using the load protection table described above, all the instructions to be protected are described, and the processing proceeds with invalid information stored by the instructions explicitly. Since microcomputers place emphasis on performance, even if the number of protected instructions stored (number of entries) is large, there is often no problem with a slight increase in hardware scale. However, an increase in hardware scale directly leads to an increase in power consumption and production costs. In the microcontroller, there is a problem that performance must be sacrificed in order to avoid an increase in hardware as much as possible.

  In an assembler obtained by compiling a high-level language, etc., the frame area (stack area) is generally used to temporarily hold data and is separated from the area that holds global variables. There are many. Most of the reason for using the frame area is due to the lack of general purpose registers. On the other hand, when the translation code is executed by a microprocessor having a large number of general-purpose registers, data can be held in the registers, so that memory access is often unnecessary.

  If there is only a load protect table, it is not possible to delete a memory access instruction when performing the optimization described above. For example, consider a case where the original code holds a temporary value in the frame area and reads it from the frame area each time that value is needed. If the value can be held in the register, writing to the memory and reading from the memory are not necessary, and these memory access instructions can be deleted. However, there is no guarantee that other memory access instructions do not reference the value. Even when the load protect function is provided, if the memory access instruction is deleted, it is not registered in the load protect table, so at least the store instruction cannot be deleted.

  Further, not only an unnecessary memory access instruction remains for the guarantee, but also the entry of the load protection table must be used by leaving the instruction, and a large table is required. Therefore, although the scale of hardware increases, there is a problem that memory access can be optimized only to some extent.

  The present invention has been made in order to solve the above-described problems, and an object of the present invention is to provide a memory access that can be optimized by deleting a memory access instruction and can generate an efficient translation code. It is to provide a monitoring device.

  According to one aspect of the present invention, a memory access monitoring device in a microcontroller capable of executing binary translation is a memory access instruction that decodes an instruction code and checks a frame area that is a specific area of the memory. Decoding means for determining whether or not, a table for setting a frame area, and a memory address that is determined by the decoding means to be a memory access instruction for checking the frame area by the instruction code and accessed by the instruction code And generating means for generating and outputting a hit signal.

  According to another aspect of the present invention, there is provided a memory access monitoring device in a microcontroller capable of executing binary translation, which decodes an instruction code and determines whether it is a register relative indirect memory access instruction. And a table for setting a frame area, which is a specific area of the memory, a register for storing a base register number, and a decoding unit that determines that the instruction code is not a register relative indirect memory access instruction, or When the instruction means determines that the instruction code is a register relative indirect memory access instruction and the base register number of the instruction code does not match the base register number stored in the register, the instruction code accesses the instruction code. Memo If the frame area in which the address is set in the table, and a generating means for generating and outputting a hit signal.

  According to an aspect of the present invention, the generation unit determines that the instruction code is a memory access instruction for checking the frame area by the decoding unit, and sets a memory address accessed by the instruction code in the table. If it is within the frame area, a hit signal is generated and output, so even if a memory access instruction that accesses a frame area that is no longer needed is deleted, the other memory access instruction has the same address as the deleted memory access instruction. You can now guarantee that you will never have access.

  According to another aspect of the present invention, when the generation unit determines that the instruction code is not a register relative indirect memory access instruction by the decoding unit, or the instruction unit stores the instruction code in register relative indirect memory access by the decoding unit. If the instruction register is determined to be an instruction and the base register number of the instruction code does not match the base register number stored in the register, the memory address accessed by the instruction code is within the frame area set in the table. If so, a hit signal is generated and output, so it is possible to determine whether or not to refer to the frame area table without preparing a specific memory access instruction to be compared with the value of the frame area table. .

(First embodiment)
FIG. 1 is a block diagram showing a schematic configuration of a memory access monitoring apparatus according to the first embodiment of the present invention. The memory access monitoring device includes a decoder 1 that decodes an instruction code, a hit signal generation circuit 2 that determines whether the instruction code hits a predetermined condition, generates a hit signal that is the determination result, and outputs the hit signal. And a frame area table 3 used to determine whether the memory access address is in the frame area. In the present embodiment, the case where the microcontroller and the memory access monitoring device are configured by one chip will be described, but the present invention is not limited to this.

  Information on whether or not to check the frame area is specified in the instruction code. The decoder 1 decodes the information to generate a frame area check signal and outputs it to the hit signal generation circuit 2. The decoder 1 also outputs the operand decoding result to the hit signal generation circuit 2.

  The frame area table 3 includes a maximum value register 31 that holds the maximum value of the address of the frame area, a minimum value register 32 that holds the minimum value of the address of the frame area, and the maximum value and address held in the maximum value register 31. A comparator 33 that compares the memory access address output to the bus 5 and a comparator 34 that compares the minimum value held in the minimum value register 32 and the memory access address output to the address bus 5 are included.

  The comparator 33 outputs a first comparison condition match signal when the memory access address output to the address bus 5 is equal to or less than the maximum value held in the maximum value register 31. In the example of FIG. 1, when the logic level of the comparison match signal is set to a high level (hereinafter abbreviated as H level) and the memory access address is less than or equal to the maximum value held in the maximum value register 31, the comparator 33 The H level is output, and if it is greater than the maximum value, the low level (hereinafter abbreviated as L level) is output. If the memory access address output to the address bus 5 is equal to or greater than the minimum value held in the minimum value register 32, the comparator 34 outputs a second comparison condition match signal. In the example of FIG. 1, if the logic level of the comparison match signal is H level, the comparator 34 outputs H level when the memory access address is not less than the minimum value held in the maximum value register 32, and the minimum value If it is smaller than that, L level is output.

  The hit signal generation circuit 2 generates a check signal indicating whether or not to check the frame area based on the operand output from the decoder 1 and the frame area check signal, and outputs the check signal. The hit signal output circuit 22.

  The control circuit 21 outputs a signal of a predetermined logic level as a check signal when the operand indicates a memory access instruction and the frame area check signal indicates that the frame area is to be checked. In the example of FIG. 1, when the frame area check signal indicates that the frame area is to be checked, an H level is output to the check signal. The hit signal output circuit 22 is composed of an AND circuit. When the check signal output from the control signal 21 is at the H level and the signals output from the comparators 33 and 34 are at the H level, the hit signal is output. H level is output to the other end, otherwise L level is output to the hit signal.

  In the above configuration, when the first and second comparison coincidence signals from the comparators 33 and 34 are at the H level and the check signal from the control circuit 21 is at the H level when the frame region check is performed, the AND circuit Although an example in which an H level hit signal is output from the hit signal output circuit 22 configured as described above is shown, it is possible to arbitrarily change the logic level of the input or output, for example, the first and second comparison matches The hit signal output circuit 22 is replaced with a logic circuit such as an OR circuit, a NAND circuit or a NOR circuit in accordance with the logic level of the check signal output when performing the signal and frame region check, and the logic level of a part of the input Can be used as appropriate.

  In the example of FIG. 1, the first comparison match signal and the second comparison match signal are respectively input to the hit signal output circuit 22, but an AND circuit is further provided in the frame table region 3 to provide the first comparison match signal. It is also possible to input the comparison match signal and the second comparison match signal to the AND circuit and supply the output to the input of the hit signal output circuit 22. At that time, the number of input terminals of the hit signal output circuit can be reduced by one.

  The hit signal is communicated to a mechanism that generates an exception in the microprocessor. An exception occurs when the hit signal is at the H level, and the instruction is re-executed from a certain point. The re-execution of this instruction is the same as the operation when an exception occurs in the load protection table described in the prior art.

  FIG. 2 is a diagram illustrating an example of a frame area table operation command according to the first embodiment of this invention. The SET_FPMIN instruction is an instruction for setting the minimum value of the address of the frame area in the minimum value register 32. The SET_FPMAX instruction is an instruction for setting the maximum value of the address of the frame area in the maximum value register 31. The value set in the register is described after SET_FPMIN or SET_FPMAX. The RESET_FPMIN instruction is an instruction for resetting the minimum value register 32, and “1” is set to all the bits of the minimum value register 32 by executing this instruction. The RESET_FPMAX instruction is an instruction for resetting the maximum value register 31. By executing this instruction, “0” is set to all the bits of the maximum value register 31.

  These instructions are executed (described in the translation code) when translation starts or when the frame area is changed, so that the maximum or minimum value of the frame area table is set or reset. It is.

  If the instruction code is a frame area table operation instruction, the decoder 1 sets or resets the maximum value register 31 or the minimum value register 32 via the bus 4.

  FIG. 3 is a diagram showing an example of a method for clearly indicating whether or not to check the frame area in the first embodiment of the present invention. FIG. 3A shows a word load instruction, which is explicitly described by adding a frame region check extension “.F” as shown in the left mnemonic. Further, as shown in the configuration of the instruction code on the right side, the frame region check extension is stored in bits 30 and 31. The load instruction shown in FIG. 3A is an instruction for reading data from an address obtained by adding the value stored in Rc to the base address stored in register Rb and storing the data in register Ra. The load instruction shown in FIG. 3B is an instruction for reading data from an address obtained by adding an immediate value imm to the base address stored in the register Rb and storing the data in the register Ra.

  As described above, according to the memory access monitoring apparatus of the present embodiment, when a memory access instruction accesses a frame area, an exception is generated and the instruction is re-executed from a certain point in time. Even if a memory access instruction that accesses a frame area that is no longer needed is deleted, it can be assured that no other memory access instruction accesses the same address as the deleted memory access instruction. Therefore, optimization by deleting the memory access instruction can be performed freely, and an efficient translation code can be generated.

  In addition, it is no longer necessary to individually manage the instruction for accessing the deleted frame area using the load protect table, and the load protect table can be configured with a minimum amount of hardware.

(Second Embodiment)
FIG. 4 is a block diagram showing a schematic configuration of a memory access monitoring apparatus according to the second embodiment of the present invention. The memory access monitoring device includes a decoder 11 that decodes an instruction code, a control circuit 23 that generates and outputs a frame area access signal based on a register relative indirect signal output from the decoder 11, a hit signal output circuit 24, A maximum value register 31, a minimum value register 32, comparators 33 and 34, and a base register 35 for holding a base register number. Note that components having the same functions as those in the first embodiment are denoted by the same reference numerals, and detailed description of the components will not be repeated.

  In general, a memory access instruction for accessing a frame area uses (base register value + immediate value) as an address. Therefore, whether to access the same address can be determined at the time of translation as long as the value of the base register does not change. In addition, all memory access instructions that do not use (base register value + immediate value) as an address can be guaranteed to be correctly executed even if the instruction that accesses the frame area is deleted by comparing it with the value in the frame area table. it can.

  The decoder 11 decodes the instruction code, and if the instruction code is a register relative indirect memory access instruction whose address is (base register value + immediate value), for example, outputs an H level to the register relative indirect signal. In this case, L level is output to the register relative indirect signal.

  When the register relative indirect signal output from the decoder 11 is at the H level, the control circuit 23 compares the register number of the memory access instruction with the base register number held in the base register 35. If they match, it is determined that this memory access instruction accesses the frame area, and an H level, for example, is output to the frame area access signal.

  In addition, when the register relative indirect signal output from the decoder 11 is at the L level, or even when the register relative indirect signal is at the H level, the register number of the memory access instruction and the number of the base register held in the base register 35 Is not equal to the frame area, for example, L level is output to the frame area access signal in order to determine whether or not this memory access instruction accesses the frame area.

  In the example of FIG. 4, the hit signal output circuit 24 is an AND circuit having an input that receives the frame area access signal as an inverting input (that is, only when the signal at the inverting input terminal is at L level and the input signal at the other terminal is at H level). When the frame area access signal is at the H level, the comparison result is invalidated and the L level is output as the hit signal. The hit signal output circuit 24 outputs an H level to the hit signal to generate an exception when the frame area access signal is at the L level and the comparators 33 and 34 output the H level. The instruction is re-executed from a certain point.

  FIG. 5 is a diagram illustrating an example of a frame area table operation command according to the first embodiment of this invention. The SET_FPMIN instruction, the SET_FPMAX instruction, the RESET_FPMIN instruction, and the RESET_FPMAX instruction are the same as those shown in FIG. The SET_FP instruction is an instruction for setting a register number in the base register 35. The CLR_FP instruction is an instruction for clearing the value of the base register 35. By executing this instruction, (the number of registers + 1) is set in the base register 35.

  As described above, according to the memory access monitoring apparatus of the present embodiment, in addition to the effects described in the first embodiment, a specific memory access instruction to be compared with the value of the frame area table is prepared. It is possible to determine whether or not to refer to the frame area table. Therefore, it is possible to determine whether to refer to the frame area without changing the instruction field or adding a new instruction.

(Third embodiment)
In the first and second embodiments of the present invention, the frame area table is set and reset using a dedicated instruction. However, in the third embodiment of the present invention, a memory access instruction By adding a frame area operation extension to the frame area, the contents of the frame area table can be changed simultaneously with memory access.

  FIG. 6 is a block diagram showing a schematic configuration of a memory access monitoring apparatus according to the third embodiment of the present invention. The memory access monitoring device includes a decoder 12 that decodes an instruction code, a control circuit 23 that generates and outputs a frame area access signal based on a register relative indirect signal output from the decoder 12, a hit signal output circuit 24, A maximum value register 31, a minimum value register 32, comparators 33 and 34, and a base register 35 for holding a base register number. Note that components having the same functions as those in the second embodiment are denoted by the same reference numerals, and detailed description of the components will not be repeated.

  The decoder 12 decodes the instruction code. If the instruction code is a memory access instruction whose address is (base register value + immediate value), the decoder 12 outputs an H level to the register relative indirect signal. L level is output to the register relative indirect signal. If the instruction code is a memory access instruction with a frame region operation extension, the decoder 12 decodes the frame region operation extension, and the base register 35 and the maximum value register 31 according to the decoding result. Alternatively, a set signal is output to the minimum value register 32 and a register number or a memory address is output to the bus 4.

  FIG. 7 is a diagram illustrating an example of an extension for manipulating a frame area according to the third embodiment of the present invention. If the extension “.FMIN” is attached to the instruction, the minimum value of the address of the frame area is set in the minimum value register 32. If the extension “.FMAX” is added to the instruction, the maximum value of the address of the frame area is set in the maximum value register 31. If the extension “.b” is attached to the instruction, the base register number is set in the base register 35.

  FIG. 8 is a diagram illustrating an example of an instruction with a frame region operation extension according to the third embodiment of the present invention. FIGS. 8A and 8B show a word load instruction, which is explicitly described by adding a frame region operation extension as shown in the left mnemonic. In the extension “.F”, any one of the frame region operation extensions shown in FIG. 7 is described. Further, as shown in the configuration of the instruction code on the right side, the extension for operating the frame area is stored in bits 30 and 31. The value set in the register is described after the instruction code including the extension for operating the frame area, and constitutes, for example, an 8-byte instruction as a whole.

  For example, if the load instruction shown in FIG. 8A is appended with the extension “.FMIN” for frame region operation, the decoder 12 outputs the value set in the minimum value register 32 to the bus 4 and sets the minimum A set signal to the value register 32 is output. The decoder 12 outputs the value set in the maximum value register 31 to the bus 4 and outputs the maximum value if the extension “.FMAX” is attached to the load instruction shown in FIG. A set signal to the value register 31 is output. Further, the decoder 12 outputs a value to be set in the base register 35 to the bus 4 if the extension “.b” for the frame area operation is added to the load instruction shown in FIG. A set signal to 35 is output.

  As described above, according to the memory access monitoring device in the present embodiment, in addition to the effects described in the first and second embodiments, an execution cycle due to execution of a dedicated instruction is not added. Values can be set in the frame area table. Therefore, it is possible to generate an instruction code with a reduced execution cycle.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

It is a block diagram which shows schematic structure of the memory access monitoring apparatus in the 1st Embodiment of this invention. It is a figure which shows an example of the frame area | region table operation command in the 1st Embodiment of this invention. It is a figure which shows an example of the method of specifying whether the frame area | region is checked in the 1st Embodiment of this invention. It is a block diagram which shows schematic structure of the memory access monitoring apparatus in the 2nd Embodiment of this invention. It is a figure which shows an example of the frame area | region table operation command in the 1st Embodiment of this invention. It is a block diagram which shows schematic structure of the memory access monitoring apparatus in the 3rd Embodiment of this invention. It is a figure which shows an example of the extension for frame area operation in the 3rd Embodiment of this invention. It is a figure which shows an example of the instruction | command with which the extension for the frame area | region operation in the 3rd Embodiment of this invention was attached | subjected.

Explanation of symbols

  1, 11, 12 decoder, 2 hit signal generation circuit, 3 frame area table, 4 bus, 5 address bus, 21, 23 control circuit, 22, 24 AND circuit, 31 maximum value register, 32 minimum value register, 33, 34 Comparator, 35 base register.

Claims (7)

A memory access monitoring device in a microcontroller capable of executing binary translation,
Decoding means for decoding the instruction code and determining whether the instruction is a memory access instruction for checking a frame area which is a specific area of the memory;
A table for setting the frame area;
If the instruction means determines that the instruction code is a memory access instruction for checking the frame area, and the memory address accessed by the instruction code is within the frame area set in the table, a hit signal is generated. And a memory access monitoring device. The instruction code includes an identifier indicating whether to check the frame area,
The memory access monitoring apparatus according to claim 1, wherein the decoding unit determines whether or not the instruction code is a memory access instruction for checking a frame area with reference to the identifier. A memory access monitoring device in a microcontroller capable of executing binary translation,
Decoding means for decoding an instruction code and determining whether or not it is a register relative indirect memory access instruction;
A table for setting a frame area which is a specific area of the memory;
A register to store the base register number;
When the decoding means determines that the instruction code is a memory access instruction that is not a register relative indirect memory access instruction, or the decoding means determines that the instruction code is a register relative indirect memory access instruction and the base of the instruction code If the register number does not match the base register number stored in the register and the memory address accessed by the instruction code is within the frame area set in the table, a hit signal is generated and output. And a memory access monitoring device including a generation unit. The table includes a first register for storing a minimum value of an address of the frame region;
A second register for storing a maximum value of the address of the frame area;
First comparing means for determining whether the memory address is greater than or equal to a minimum value stored in the first register;
4. The memory access monitoring apparatus according to claim 1, further comprising: a second comparison unit that determines whether or not the memory address is equal to or less than a maximum value stored in the second register.   The memory access monitoring apparatus according to claim 1, wherein an exception is generated by a hit signal generated by the generation unit. The instruction includes a dedicated instruction for setting a frame area in the table or the register,
The memory access monitoring apparatus according to claim 1, wherein if the instruction code is the dedicated instruction, the decoding unit sets a value in the table or the register. The instruction code includes an extension indicating that the frame area is operated,
A value set in the table or the register simultaneously with the memory access,
The memory access monitoring apparatus according to claim 1, wherein the decoding unit sets a value in the table or the register simultaneously with a memory access if the extension is added to the instruction code.

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