JP3872809B2 - Method and apparatus for enhancing scheduling in advanced microprocessors - Google Patents

Abstract

Apparatus and a method for causing scheduler software to produce code which executes more rapidly by ignoring some of the normal constraints placed on its scheduling operations and simply scheduling certain instructions to run as fast as possible, raising an exception if the scheduling violates a scheduling constraint, and determining steps to be taken for correctly executing each set of instructions about which an exception is raised.

Description

  The present invention relates to computer systems and, more particularly, to a method and apparatus for accelerating instruction reordering in an improved microprocessor.

  In recent years, a simple but very fast host processor (referred to as “morph morph”) and software (referred to as “code morphing software”) have been combined, New microprocessors have been developed that execute application programs designed for a processor different from the processor at a speed that cannot be achieved by the processor (target processor) for which the program is designed. The morph host processor executes code morphing software to convert the application program into morph host processor instructions to achieve the original target software objectives. As the target instructions are converted, they can be executed and stored in the conversion buffer at the same time and accessed without further conversion. Initial conversion and execution of the program is slow, but once converted, many of the steps normally required when executing the program in hardware are not required.

  In order to be able to execute programs designed for other processors at a rapid rate, the morph processor includes a number of hardware enhancements. One of these enhancements is a gated store buffer that exists between the host processor and the translation buffer. The second enhancement is a set of host registers that store the state of the target machine at the start of any sequence of target instructions to be translated. A sequence of target instructions in a range where the state of the target processor is known is converted to a morph host instruction, placed in a conversion buffer, and awaiting execution. If the converted instruction is executed without an exception occurring, the target state at the start of the instruction sequence is updated to the target state at the time when the sequence is completed.

  If an exception occurs during the execution of the translated host instruction sequence, the process stops and the entire operation can be returned to the beginning of the target instruction sequence where a known state of the target machine exists, i.e., can be rolled back. This allows for very rapid and precise exception handling while dynamically translating and executing instructions, resulting in results never achieved by the prior art.

  Further speedup is achieved when running a new microprocessor with a scheduler that is part of the code morphing software. As the instructions are converted, the scheduler rearranges and reschedules the instructions from the raw order generated by the raw conversion into an order that provides the same result but allows for faster execution. The scheduler attempts to reduce the time it takes to execute the rescheduled software by placing certain instructions in front of other instructions or running the instructions together. The scheduler function is associated with a number of constraints, and the most basic constraint is that the rescheduled program must still produce the same final result as the original program.

  As an example, some programs have a sequence of instructions that must be executed without interruption in order to obtain correct results. The scheduler cannot interfere with such sequences without interfering with the results obtained. Many processors have hardware interlocks to ensure that such sequences actually run without interruption. Because of the need to protect such instruction sequences, special constraints are placed on processors without hardware interlocks, such as the advanced morph host processors discussed herein. The software must in some way know these sequences and ensure that they run without interruption.

  Control dependency is another traditional constraint on reordering that the scheduler faces. Control dependency is related to branch instructions. The scheduler must ensure that the program executes correctly even if it reorders the instructions that appear before and after the branch.

  There is another dependency on storage that affects load reordering. For example, when the updated data is stored at a certain memory address and then operated in a register operation, the data at that address must not be held in the register at the time of storage. Otherwise, the data in the register may be out of date.

All of these constraints make typical scheduler functionality very conservative, resulting in slower code generation.
Conventional schedulers do their best in determining instructions that depend on each other to perform reordering. A normal scheduler can determine that some operations depend in some way on other operations, and some operations do not depend on other operations at all, but cannot determine anything about other operations. Such schedulers treat them conservatively in the case of operations that depend on other operations, by arranging them in the normal native order in which they occurred. Such a scheduler reorders operations that are completely independent of other operations as it desires. Eventually, the scheduler treats all operations that cannot be determined with respect to dependencies as if they depend on each other, thus making these treatments conservative and slow.

  It would be desirable to provide circuitry and software that allows advanced processor schedulers to generate code that executes at an accelerated rate.

  The present invention ignores some of the normal constraints defined for scheduling operations, simply schedules certain instructions to execute as fast as possible, raises an exception if this scheduling violates the scheduling constraints, This is accomplished by an apparatus and method that causes the scheduler software to generate code to be executed more quickly by determining the actions to be taken to correctly execute each instruction set that has generated.

  These and other objects and features of the invention will be better understood by reference to the following detailed description taken in conjunction with the drawings. In the drawings, like elements are referred to with like numerals throughout the several views.

  FIG. 1 is a much simpler hardware processor (referred to as “morph host”) and emulated software (referred to as “code morphing software”) that is much simpler than the state of the art microprocessor. ) Shows a new microprocessor 10 combined. The two parts work together to perform operations in an advanced microprocessor that would normally be performed only in hardware. The new microprocessor 10 is faster than prior art microprocessors, can run any software for any operating system that can be run by a number of prior art microprocessor families, and is conventional. Less expensive than technical microprocessors.

  The microprocessor 10 includes a morph host processor 11 designed to execute code morphing software 12 to execute application programs designed for different target processors. The morph host 11 includes specially adapted hardware enhancements to allow efficient use of the acceleration techniques provided by the code morphing software 12. The morph host processor includes hardware enhancements that help speed up operations and provide the state of the target computer immediately when an exception or error occurs. Code morphing software, among other things, translates target program instructions into morph host instructions, schedules and optimizes host instructions, and executes correctly in response to exceptions and errors when necessary. It includes software that rolls back execution to the last known time and replaces the correct target state and working state at that time so that the correct target code retranslation occurs. The code morphing software also includes various processes that increase processing speed. The block diagram of FIG. 2 details the example hardware of the morph host 11 that implements the features discussed herein.

  As shown in the diagram of FIG. 3 (showing the main loop operation of the code morphing software 12), the code morphing software, in combination with the enhanced morph host, morphs the target instruction during execution. Converts to host instructions and caches these host instructions in a memory data structure (referred to as a “translation buffer”). Once the target instruction has been converted, it can be recalled from the conversion buffer and executed. In doing so, determine which primitive instructions are required to implement each target instruction, address each primitive instruction, fetch each primitive instruction, optimize the sequence of primitive instructions, and assign assets to each primitive instruction Many steps required in prior art hardware microprocessors, such as assigning, reordering primitive instructions, and executing each step of each sequence of related primitive instructions each time a target instruction is executed None of them are required.

  One of the main problems with prior art emulation techniques has been the inability to skillfully handle exceptions that occur during execution of the target program. Some exceptions that occur during the execution of the target application are thrown to the target operating system, and at the time of any such exceptions for proper execution of the exception and subsequent instructions. Even the correct target state must be obtained. In addition, the emulator may generate an exception in order to detect a specific target operation that has been replaced by a specific host function. Furthermore, the host processor may also generate an exception when executing a host instruction derived from the target instruction. All of these exceptions can occur during an attempt to change the target instruction to a host instruction by the emulator, or when an emulated host instruction is executed by the host processor. Exceptions thrown to the target operating system are particularly difficult because knowledge of the state of the target processor is always required.

  In order to efficiently recover from these exceptions, the enhanced morph host includes a number of hardware improvements. These improvements include a gate storage buffer (see FIG. 5). The gate storage buffer is responsible for changing the working memory state on the “uncommited” side of the hardware “gate” and changing the official memory state on the “commited” side of the hardware gate. Store. At the hardware gate, these committed memories "flow out" to main memory. A “commit” operation transfers memory storage from the uncommitted side of the gate to the commit side of the gate. When an exception occurs, the “rollback” operation discards the uncommitted storage in the gate storage buffer.

  The hardware enhancement also includes a number of additional processor registers (see FIG. 4). The additional registers provide a set of host or working groups for processing host instructions, in addition to enabling register renaming to mitigate problems for instructions that attempt to utilize the same hardware resources. It is possible to maintain registers and also to maintain a set of target registers that hold the official state of the target processor that originally created the target application. Target registers are connected to their working register equivalents via a dedicated interface, which allows the commit operation to quickly transfer the contents of all working registers to the official target register. And allows the transfer of the contents of all official target registers to their working register equivalents quickly by an action called “rollback”.

  Once one or a group of target instructions has been converted and executed without error, the state of the memory and the state of the target register can be updated with additional official registers and gate storage buffers. Updates are selected by code morphing software so that they occur at the boundaries of a single target instruction. If the source host instruction generated by a series of target instruction conversions is run without exception by the host processor, the working memory store and working register states generated by these instructions are in official memory. And transferred to the official target register.

  On the other hand, if an exception occurs when processing a host instruction at a time that is not at the target instruction boundary, the original state in the target register at the time of the last update (or commit) is recalled to the working register. The uncommitted memory storage in the gate storage buffer can be discarded. If the exception that occurred is a target exception, the target instructions that caused the target exception are reconverted one at a time, in a sequential sequence as if executed by the target microprocessor. Can be executed. As each target instruction is executed correctly without error, the state of the target register can be updated and the data in the storage buffer can be passed to memory. If an exception occurs again while running the host instruction, the correct state of the target processor is held by the morph host and the memory target register, and the operation can be processed correctly without delay. Each new conversion performed by this coordinated conversion can be cached for future use each time it is converted, or if it happens only once or rarely, such as a page fault You may discard it. Combining these features, the microprocessor created by the combination of code morphing software and morph host helps to execute instructions more quickly than the processor for which the software was originally written.

  In addition to simply translating instructions, caching the translated instructions, and performing each transformation whenever the instruction set needs to be executed, the code morphing software reorders the different transformations, It also performs optimization and rescheduling. One of the optimization processes links the various sequences of translated host instructions together when the possibility of taking a branch during execution becomes apparent. Finally, it becomes almost completely unnecessary for the main loop to refer to the branch instruction of the host instruction. When this condition is reached, before running any host instruction, fetch the target instruction, decode the target instruction, fetch the source instructions that make up the target instruction, optimize these primitive operations, The time required for re-scheduling and rescheduling these primitive operations is not required. Thus, the work required to execute any target instruction set using the improved microprocessor is dramatically reduced.

  As pointed out above, if the order of instructions is correct but remains the same, the reordering operation uses the scheduler to try to select a better instruction execution order. One of the problems with the scheduler is that these functions are limited. The most basic constraint is that when the program is executed, it still must produce the same final result that is obtained with the original sequence of instructions. All of these constraints force a typical scheduler to function very conservatively, resulting in slower execution of the resulting code.

  For example, to ensure that correct results are produced, typical schedulers operate on determinism, instructions that do not have dependencies, instructions that have dependencies, and the existence of dependencies is unknown Select the instruction. All instructions with dependencies and instructions whose dependencies do not exist are treated as if they exist and are not reordered. Only reorder instructions that are known to have no dependencies. Following these guidelines, the scheduler generates code, which slows its execution.

  Another limitation is related to the specific embodiment of the morph host processor. One embodiment of a morph host processor is a processor designed to speed up functions by eliminating special circuitry that slows down operation. This embodiment of the morph host processor is designed without any hardware locking mechanism. A hardware locking mechanism is a circuit whose purpose is to ensure that all steps in a particular instruction sequence are executed without interruption. In the absence of a locking mechanism, the scheduler functions strictly to process all the steps in such a sequence, without reordering, in the original transformed order and to ensure that the processor produces the correct result from the sequence. It is required to do.

  The scheduler of the present invention is a software part of code morphing software. Unlike prior art hardware schedulers, software schedulers use speculative techniques when reordering instructions. The scheduler assumes that the fastest possible operation is desired for a given operation and reorders the instructions to achieve this result. The morph host is equipped with hardware that raises an exception if the selected guess is incorrect. In most cases, the guess is correct and the overall result is much faster. However, if the guess is not correct, an exception typically causes the software to utilize the gate store buffer and target register and roll back the operation to the beginning of the speculative sequence where the correct state is known.

  In contrast to the deterministic strategy used by prior art schedulers, the scheduler of the present invention utilizes probabilistic guidance when selecting a category of instructions for reordering. The improved scheduler selects four categories of instruction sequences from the sequence of instructions generated from the target instruction set by the transformation (see FIG. 6). These categories include instruction sequences that have no dependencies, instruction sequences that have known dependencies, instruction sequences that have a high probability of having no dependencies, and instruction sequences that have a high probability of having dependencies. As in the case of the prior art, an instruction sequence known to have no dependency can be arbitrarily rearranged by the scheduler. Instruction sequences with known dependencies are processed in the sequential order given by the converter.

  However, instructions with a high probability of having no dependency are treated as actually having no dependency, and are rearranged so as to speed up execution as much as possible. The morph host is provided with hardware means for detecting an incorrect reordering and generating an exception if a dependency actually exists. The scheduler performs a check in cooperation with the hardware means, finds a case where each rearranged instruction cannot be executed correctly, and can generate an exception when the operation sequence does not execute correctly. Such an exception allows the scheduler to handle the sequence conservatively or in some other more appropriate manner, ignoring the reordering it has previously made that caused the exception.

  On the other hand, an instruction with a high probability of having dependency can be processed either aggressively or conservatively. When actively processing, these are treated as instructions having a high probability of having no dependency. These are rearranged, the execution is speeded up as much as possible, and the hardware means provided in the morph host is used to detect the case where the incorrect rearrangement is performed and generate an exception. When processing conservatively, they are processed in the sequential order given by the converter. Normally, conservative handling is faster. This is because generating a large number of exceptions significantly reduces execution speed.

  In one embodiment of the invention, a circuit such as that shown in FIG. 7 is added to the host processor. This circuit is used to store memory addresses that are accessed by instructions reordered by the scheduler using a special “load and protect” or “store and protect” operation. Such “load and protect” or “store and protect” operations can be used whenever an instruction is reordered, and the memory address accessed by the reordered instruction is used as a protection register. It has the effect of being placed in one of a plurality of morph host registers 71 designed for use. In one embodiment, eight protection registers 71 are provided. The “load and protect” or “store and protect” instruction points to the specific protection register used for the operation.

  Throughout this specification, the term “memory address” is used in describing load and protect instructions as well as store and protect instructions, but this term is possible to determine the memory area to be protected. It is used as a reference for many configurations. The term memory address is used to mean a descriptor of the memory address to be protected. For example, in a system where the memory is byte addressable, one embodiment of the present invention uses the starting memory address and a number of bits equal to the number of bytes in the address area to set the protection state of each of these bytes. Show. Another embodiment that provides similar addressing utilizes the starting memory address and length, while the third embodiment utilizes individual byte addresses and individual comparators per byte address.

  In one example of operation, the instruction sequence includes a first store instruction STORE1, a second store instruction STORE2, and a load instruction LOAD1 in order. The scheduler reorders these instructions, assuming that there is a low probability of incorrect operation due to reordering. In the reordered sequence, the load instruction first, the second store instruction second, and the second Place one store instruction third. To do this, the scheduler places the load data in one of the general purpose registers 72 and “load” to place the address of the memory location from which the load data was obtained in the protection register 71 specified by the instruction. Use “and protect” operation. The software scheduler knows which instruction to check to determine if an error has occurred due to the reordering, so the scheduler can determine the next instruction that might be affected by the reordering (in this case , STORE1 and STORE2 instructions, preceded by the load), indicate an instruction (eg, a bit in the bitmask) to indicate the particular protection register that holds the protected memory address. By having this indication in a specific location (one of 8 bits if 8 protection registers are used for the trapping function), the address where each store is placed by the store instruction is indicated in the indicated protection register 71. Indicates that execution of an instruction depends on whether it overlaps with a memory address held in the memory.

  Similarly, the scheduler stores the data of the STORE2 instruction in the memory using the “store and protect” operation, and the address of the memory location where the data is stored is in the protection register 71 specified by the store and protect instruction. Put. In addition, the scheduler places an instruction in each bit mask of instructions that may be affected by the reordering (in this case, only the STORE1 instruction) and indicates a specific protection register that holds this protected memory address. . Finally, the scheduler uses a normal store instruction for the last STORE1 instruction.

  When the instruction sequence is executed, the host hardware uses the comparison circuit 73 to, for each of these three instructions, the memory address of the instruction stored in one of the protection registers 71. It is determined whether there is no duplication with any part of the data in, and if there is any duplication, an exception is generated. Thus, the LOAD1 operation (load and protect) writes its memory into the protection register 71, but does not check any protection registers. This is because the set indicator does not specify any protection register. The STORE2 operation (store and protect) writes its memory location to a different protection register 71 and checks the protection register 71 used for the LOAD1 instruction to determine overlap between those memory locations To do. Finally, the STORE1 operation (increased by the protection register indicator but remains as a store) checks the protection register for each of the LOAD1 and STORE2 instructions, and its memory address and the memory address of the LOAD1 and STORE2 instructions Examine the overlap between and. In the case of the first and third embodiments described above, the comparison makes it possible to apply protection exactly at the byte level.

  Any exception causes the code morphing software to decide what action to take in response to the exception. Typically, code morphing software can conservatively reprocess instruction sequences by interrupting execution of the reordered instruction sequence and causing the host to return to the state of the target processor at the beginning of the instruction sequence. Like that. If the addresses are not identical (in this example, indicates that the store instruction does not access the protected memory address), execution of the rearranged instruction sequence proceeds at the accelerated pace obtained by the rearrangement.

  Modify load and store instructions utilized by the morph host to achieve communication between the host processor and the scheduler. In one embodiment, these instructions are completely replaced with “load and protect” and “store and protect” instructions. Each “Load and Protect” as well as each “Store and Protect” instruction includes a bit mask (eg, 8 bits corresponding to 8 protection registers) and reorders using these bits as flags Indicates a specific protection register that looks for the memory address of a specific instruction or aliased instruction. Each of these bits specifies one of the available protection registers that stores the memory address for the hardware to be checked. After checking the specific protection register designated to store the memory address when the instruction is rearranged by this bit mask, subsequent instructions that may be affected by the rearrangement are executed. "Load and protect" and "store and protect" instructions can also be used in place of normal load and store instructions, respectively. This is because if no bit in the bit mask is set, no check is made. In such cases, the “load and protect” and “store and protect” instructions are identical to the load and store operations. It should also be noted that a protection register can be associated with a specific general purpose register that holds memory data, thus allowing efficient use of a small number of protection registers.

  The host processor of the present invention also includes an additional register called an “enable protection register” 74 that stores the location of the protection register that contains the valid memory address associated with the reordered instruction. The instruction given by the “load and protect” or “store and protect” instruction is used to set a bit indicating a particular protection register to indicate that protection register. In one embodiment, the enable protection register bit is cleared whenever a commit operation is performed indicating that the translated and reordered instruction sequence has been executed without a reordering exception. Since the reordering is performed only in the sequence of instructions appearing between two commit points, the reordering operation can use all of the protection registers allocated for reordering for each newly converted instruction sequence. .

  An additional advantage of this new invention is that the store can be reordered with respect to each other by a “store and protect” operation. In the present invention, this can be accomplished by storing data in a memory location and protecting the address of this memory location in a protection register. When subsequent stores appear that can be affected by reordering, the bit mask indicates which protection registers the hardware should check against the memory address, whether an exception should be raised, or the reordering of the store It is determined whether or not is correctly performed.

  In one embodiment of the new microprocessor, memory data that is frequently used in performing operations is replicated (or “aliased”) into execution unit registers, and the time or data required to fetch the data from memory is A circuit configuration is provided that makes it possible to eliminate the time required for storage in the memory. For example, if data in memory is frequently reused during execution of one or more code sequences, each time the data is used, this data must be read from memory and loaded into a register in the execution unit It is customary. To reduce the time required by such frequent memory accesses, instead, the data is temporarily loaded from the memory into the execution unit register at the beginning of the code sequence, and the memory space is used for the duration of the code sequence. Specifies this register to act as a replacement for. Once this is done, each of the load operations normally involved in loading data from a specified memory address into a register instead is simply a register-to-register copy operation that proceeds at a much faster pace, and these In many cases, even the copying operation can be eliminated by further optimization.

  Similarly, execution of a code sequence often requires that data being executed in that code sequence be frequently written to one memory address. In order to reduce the time required to store memory for such frequent identical addresses, each time data is written to a memory address, it is designated to serve as a replacement for memory space for the duration of the code sequence. This can be transferred to the execution unit register. Once an execution unit register has been specified, every time data is changed, only a simple register-to-register transfer operation is required, which proceeds much faster than a store to memory address.

The operation of the aliasing circuit was filed on Sep. 26, 1996 and is described in M.S. entitled Method and Apparatus for Aliasing Memory Data in an Advanced Microprocessor . U.S. patent application Ser. No. 08 / 721,698 to Wing et al. This patent application is assigned to the assignee of the present invention.

  The second embodiment of the present invention for accelerating the reordering operation utilizes some additional hardware and, as described in the aforementioned patent application, the same hardware for both reordering and memory address aliasing. Is to be able to use. Note that reordered instructions typically appear between adjacent committed operations, whereas memory data aliased in execution unit registers actually lasts much longer. Is customary. Note that in this second embodiment, a second “persistent” register 76 is added to enable long-term or permanent protection, along with short-term protection provided for reordering by the enable protection register 74. Keep it. The second persistent register 76 is used in the same manner as the register 74, but records only the protection register that should maintain the memory address for a longer period than between adjacent commit operations.

  For example, if it is desired to alias the memory address and store the data in a host register for use for a long period of time (eg during a loop), which protection register holds the address of the long-term aliasing operation Is copied from the instruction and placed in both the enable protection register 74 and the second persistent register 76. Assuming that the first commit operation can be performed by executing the rearranged instruction sequence without causing an exception, the enable protection register is cleared. In this way, the short-term flag indicating the protection register that holds the address of the rearranged instruction to be checked is deleted every commit. After clearing the enable protection register at the time of commit, the contents of the second permanent register are written into the enable protection register. Since the data in the permanent register indicating which protection register is used for long-term aliasing is written to the enable protection register, the indication of the protection register used for long-term aliasing is not affected by the commit operation. By writing the contents of the persistent register to the enable protection register at each commit, the data is no longer needed for the next instruction sequence, and ultimately for the aliasing operation, and the second register is finally cleared. Until you do so, continue to protect effectively.

  In addition to the second permanent register 76, a shadow register 78 is held, and information held in the permanent register is also stored. The shadow register is used during commit and rollback operations. When a commit occurs, the data in persistent register 76 is copied to enable protection register 74 as described above. Further, since the same data is copied to the register 78 that shadows (protects) the permanent register at the time of commit, the setting of the permanent register is accommodated in the shadow register at the start of the next instruction sequence to be rearranged. If an exception occurs during execution of the next instruction sequence and a rollback operation is required, the contents of the shadow register are copied to both the enable protection register and the permanent register. This will place in these registers the same instructions that were in the enable protection register and the permanent register before the execution of the instruction sequence started, thereby ensuring the correct state to continue execution more conservatively. .

  Additional advantages are provided by the arrangement of the present invention. With the addition of a persistent register 76, the same hardware can be used to enhance both the ability to reorder in the short term (between commits) and to retain alias memory data for long periods in the execution unit registers. This eliminates memory access redundancy, and can also be used to eliminate other types of redundancy that occur during commit operations. For example, two loads can occur from the same memory address within an instruction sequence. If this happens and the store for this memory address does not occur in the middle, the second load can simply be ignored, and the data placed in the register by the first memory access will be substituted for the second load operation. In addition, it may be used without change. However, if a store enters between these loads, it is necessary to determine whether this store has been performed on the memory address performing the second access. In other words, in the conventional optimization technique, when a store enters between loads, the second load cannot be deleted.

  The present invention can be effectively used to shorten the operation. If the first load is changed to a “load and protect” operation, the memory address is stored in a protection register and the store instruction receives a flag indicating the specific protection register to check, the second load The data stored by the “load and protect” operation can be used for the second load. When a store instruction attempts to access a protected memory address, a flag indicating the protection register to be checked performs a comparison before the store is accessed. This raises an exception and rolls back to the last commit point where the correct target state exists. Thus, the scheduler can provide an appropriate instruction sequence including a second load operation and can execute the sequence again.

  Similarly, if an instruction sequence between two commit operations includes two stores to the same memory address, delete the first store if there is no load from this memory address between the stores. Can do. However, if the data from this memory address is used for an intermediate load, the first store cannot be deleted. Using the present invention, the first store for this memory address can be deleted by making the load instruction "load and protect". The second store then receives the protection register indication from “Load and Protect” and checks the memory address of the access. If the load is from a different address, the second store can continue correctly. If the load is from the same address, attempting to access memory for the second store will raise an exception and roll back the operation to the last commit point. From this point, the scheduler may re-schedule the instruction to include both store operations and re-execute the sequence.

  While the invention has been described with reference to the preferred embodiment, it will be appreciated that various changes and modifications can be made by those skilled in the art without departing from the spirit and scope of the invention. For example, although the invention has been described with respect to embodiments designed to work with a particular processor family, the invention applies equally to programs and programs designed for other processor architectures. It is natural to understand that. Accordingly, the invention should be construed based on the claims that follow.

FIG. 1 is a diagram illustrating a novel microprocessor that can utilize the present invention. FIG. 2 is a block diagram of hardware that implements the novel microprocessor of FIG. FIG. 3 is a flowchart showing the main processing loop of the new processor of FIG. FIG. 4 is a block diagram showing a part of the new processor. FIG. 5 is a block diagram showing another part of the new processor. FIG. 6 is a flow chart showing the operation of scheduler software designed in accordance with the present invention. FIG. 7 is a block diagram illustrating one embodiment of a circuit implementing the present invention.

Claims (19)

Instruction scheduling and execution method comprising:
a) a first memory operation including a first address range; a second memory operation including at least a portion of the first address range; and a third intervening in the first and second memory operations. Accessing a sequence of instructions consisting of memory operations,
It is not known whether the third memory operation includes an address within the first address range, and at least one of the first to third memory operations includes a store operation;
An access step;
b) removing the second memory operation from the sequence of instructions;
c) adding information to the third memory operation to determine the first address range,
The information comprises a mask to determine which of the plurality of registers holds the protected address;
Additional steps;
d) removing the second memory operation and executing the sequence of instructions;
e) During the execution, it is determined whether the third memory operation affects an address in the first address range, and if so, an exception is generated and the second memory is Re-executing the sequence of instructions including the operation;
A method consisting of: The method of claim 1, wherein step e) further determines whether during the execution, the third memory operation affected an address within the range of any protected address. A method comprising steps. The method of claim 1, further comprising the step of storing a memory address associated with the first address range in one of the plurality of registers prior to execution of the instruction sequence. how to. The method of claim 1, further comprising the step of storing a memory address associated with the first address range in a register prior to execution of the instruction sequence. 5. The method of claim 4, wherein the sequence of instructions includes a fourth memory operation in the sequence of instructions after the first instruction sequence;
Further, even if the fourth memory operation affects the first address range, second information that allows the fourth memory operation to be executed without occurrence of an exception is obtained. Including the step of appending to
A method characterized by that. 2. The method of claim 1, wherein the first and second memory operations can be safely reduced to a single memory operation if the third memory operation is not intervening. Instruction scheduling and execution method comprising:
a) a first load instruction that loads from a first address range, a second load instruction that loads from the first address range, and a store instruction that intervenes in the first and second load instructions. Accessing a sequence of instructions comprising:
It is not known whether the store instruction stores to an address in the first address range;
An access step;
b) removing the second load instruction from the sequence of instructions;
c) executing the sequence of instructions without the second load instruction, including storing a memory address for the first address range in a protection register;
d) During the execution, determine whether the store instruction stores to an address in the first address range, and if so, generate an exception and include the second load instruction Re-executing the sequence;
A method consisting of: The method of claim 7, wherein step b) further comprises adding a flag to the store instruction to indicate the protection register. 8. The method of claim 7, wherein step b) further comprises changing the first load instruction to a load and protect instruction. Instruction scheduling and execution method comprising:
a) an instruction comprising a first store instruction to a first address range, a second store instruction to the first address range, and a load instruction intervening in the first and second store instructions A step of accessing a sequence of
It is not known whether the load instruction affects the first address range;
An access step;
b) removing the first store instruction from the sequence of instructions, comprising storing a memory address associated with the load instruction in a protection register;
c) executing the sequence of instructions without the first store instruction;
d) during the execution, determine whether the load instruction has affected an address in the first address range, and if so, generate an exception and include the first store instruction Re-executing the sequence of
A method consisting of: 11. The method of claim 10, wherein step b) further comprises adding a flag to the second store instruction to indicate the protection register. 11. The method of claim 10, wherein step b) further comprises changing the load instruction to a load and protect instruction. Instruction scheduling and execution method comprising:
a) a first store instruction for storing in a first address range; a load instruction for loading from the first address range; a second store instruction for intervening in the first store instruction and the load instruction; Accessing a sequence of instructions comprising:
It is not known whether the second store instruction stores to an address in the first address range;
An access step;
b) removing the load instruction from the sequence of instructions, comprising storing a memory address associated with the first address range in a protection register;
c) executing the sequence of instructions without the load instruction;
d) During the execution, it is determined whether the second store instruction stores to an address in the first address range, and if so, an exception is generated and the instruction including the load instruction Re-executing the sequence;
A method consisting of: 14. The method of claim 13, wherein step b) further comprises adding a flag to the second store instruction to indicate the protection register. 14. The method of claim 13, wherein step b) further comprises changing the first store instruction to a store and protect instruction. Instruction scheduling and execution method comprising:
a) a load instruction that loads from a first address range, a first store instruction that is not known to store to an address within the first address range, and a first instruction that stores to the first address range Accessing a sequence of instructions consisting of two store instructions,
The first store instruction intervenes in the load instruction and the second store instruction;
An access step;
b) removing the second store instruction from the sequence of instructions, comprising storing a memory address associated with the first address range in a protection register;
c) executing the sequence of instructions without the second store instruction;
d) During the execution, it is determined whether the first store instruction stores to an address in the first address range, and if so, an exception is generated and the second store instruction is Re-executing the sequence of instructions comprising:
A method consisting of: 17. The method of claim 16, wherein step b) further comprises adding a flag to the first store instruction to indicate the protection register. 17. The method of claim 16, wherein step b) further comprises changing the load instruction to a load and protect instruction. 17. The method of claim 16, wherein the second store instruction stores back to the first address range the same value that the load instruction loaded from the first address range. how to.

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