JP2005151411A - Distortion suppressing circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a distortion suppressing circuit capable of optimizing the bias control of distortion suppression. <P>SOLUTION: The distortion suppressing circuit of a high frequency power amplifier, which uses an LDMOS transistor, includes: distortion component detection means 36-48 for detecting a distortion component that occurs in the high frequency power amplifier, by partially extracting and composing an input signal and an output signal of the high frequency power amplifier 30; and a gate bias control means 50 that varies a gate bias voltage of the LDMOS transistor and controls the distortion component to a minimum. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a distortion suppression circuit, and more particularly to a distortion suppression circuit that optimizes the distortion of a high-frequency amplifier using an LDMOS (Laterally Diffused Metal Oxide Semiconductor) transistor.

  In recent years, transmission power in mobile communication tends to increase, but improvement in communication quality is also required. For this reason, high frequency amplifiers used for mobile communication are required to reduce as much as possible the increase in distortion associated with an increase in power.

  As a conventional distortion suppression circuit, for example, there is one disclosed in Patent Document 1. FIG. 1 shows a circuit configuration diagram of an example of a conventional distortion suppression circuit. In the figure, a power amplifier 10 amplifies a high frequency signal supplied from an input terminal 12 and outputs it from an output terminal 14. A directional coupler 16 is provided between the power amplifier 10 and the output terminal 14, and a part of the output high-frequency signal is branched by the directional coupler 16 and supplied to the detector 18.

  The detector 18 detects a high frequency signal and supplies the detection output to the bias control circuit 20. The bias control circuit 20 varies the bias voltage applied to the gate of the GaAs • FET in the power amplifier 10 according to the detection output to optimize the distortion included in the high frequency signal output from the power amplifier 10.

Furthermore, there is a circuit described in Patent Document 2 as a power consumption control circuit for a high-frequency linear amplifier. The power consumption control circuit of Patent Document 2 branches an input / output signal of a high-frequency linear amplifier using GaAs / FET by a coupler, detects intermodulation distortion using a delay line, a synthesizer, and a detector, A control signal based on the state of intermodulation distortion is generated to control the magnitude of the drain current of the GaAs • FET as the amplifying element of the high-frequency linear amplifier.
JP-A-5-235646 JP-A-8-256018

  In the conventional distortion suppression circuit shown in FIG. 1, an output high-frequency signal output from a directional coupler connected to the output terminal of the power amplifier 10 is detected by a detector, and an amplifier element 10a is detected by a bias control circuit 20. Since the bias control circuit 20 detects the high-frequency signal and the distortion signal, which are the main signals, the bias control circuit 20 cannot control the distortion-suppressing bias control.

  In addition, the power consumption control circuit of the high frequency linear amplifier of Patent Document 2 uses GaAs / FET to perform high frequency amplification, and the power control using LDMOS instead of GaAs / FET optimizes the distortion suppression bias control. There was a problem that I could not.

  The present invention has been made in view of the above points, and an object thereof is to provide a distortion suppression circuit capable of optimizing bias control for distortion suppression.

The invention according to claim 1 is a distortion component detecting means for detecting a distortion component generated in the high frequency power amplifier by extracting and synthesizing a part of each of the input signal and the output signal of the high frequency power amplifier,
By having gate bias control means for controlling the gate bias voltage of the LDMOS transistor so as to minimize the distortion component,
The gate bias voltage of the LDMOS transistor can be controlled so that the distortion component is minimized, and the bias control for suppressing distortion can be optimized.

The invention according to claim 2 includes drain bias control means for controlling the distortion component to increase by increasing the drain bias voltage of the LDMOS transistor when the distortion component exceeds the first threshold,
It is possible to optimize bias control for distortion suppression.

In the invention according to claim 3, the drain bias control means reduces the drain bias voltage of the LDMOS transistor and performs power consumption reduction control when the distortion component becomes less than a second threshold value.
The power consumption of the high frequency power amplifier can be reduced.

  According to the first aspect of the present invention, the gate bias voltage of the LDMOS transistor can be controlled to minimize the distortion component, and the bias control for suppressing the distortion can be optimized.

  According to the second aspect of the invention, it is possible to optimize the bias control for distortion suppression.

  According to the third aspect of the present invention, the power consumption of the high frequency power amplifier can be reduced.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 2 shows a circuit configuration diagram of the first embodiment of the distortion suppression circuit of the present invention. In the figure, the power amplifier 30 amplifies the high frequency signal supplied from the input terminal 32 and outputs it from the output terminal 34. The power amplifier 30 performs power amplification using an LDMOS transistor 30a which is a field effect semiconductor element. The LDMOS transistor 30a is supplied with an input high-frequency signal at the gate and outputs an output high-frequency signal from the drain. The LDMOS transistor 30a is configured to have a variable gate bias voltage and a fixed drain bias voltage.

  Directional couplers 36 and 38 are provided between the power amplifier 30 and the input terminal 32 and output terminal 34, and a part of the input high-frequency signal is branched by the directional coupler 36. A part of the output high-frequency signal is branched. A part of the input high-frequency signal branched by the directional coupler 36 is delayed by a predetermined delay amount by the delay unit 40 and supplied to the combiner 46.

  A part of the output high-frequency signal branched by the directional coupler 38 is phase-shifted by the phase shifter 42, attenuated by the attenuator 44, and supplied to the combiner 46. The delay amount of the delay device 40 corresponds to the delay amounts of the power amplifier 30, the phase shifter 42, and the attenuator 44. The phase shifter 42 inverts the phase of the output high frequency signal with respect to the phase of the input high frequency signal in the synthesizer 46. The attenuator 44 makes the input high-frequency signal level and the output high-frequency signal level in the synthesizer 46 the same. Therefore, the distortion component excluding the high-frequency signal component is extracted from the synthesizer 46. This distortion component is detected by the detector 48, and a distortion component voltage that is a detection output is supplied to the bias controller 50.

  The bias control unit 50 varies the resistance value of the variable resistor 52 in accordance with the distortion component voltage and varies the gate bias voltage applied to the gate of the LDMOS transistor 30a in the power amplifier 30 to thereby output the high frequency signal output from the power amplifier 30. Optimize distortion contained in.

  Here, the LDMOS transistor 30a has an idle current / distortion characteristic as shown by a solid line in FIG. 3, and the distortion at a specific idle current Idq1 is a minimum value. On the other hand, the distortion of the GaAs • FET decreases as the idle current increases as shown by the broken line. The idle current is the drain current of the LDMOS transistor 30a when the input high frequency signal is zero.

  The bias controller 50 varies the gate bias voltage of the LDMOS transistor 30a according to the flowchart shown in FIG. In FIG. 4, an initial value Vgs preset as a gate bias voltage is applied to the gate of the LDMOS transistor 30a in step S1. When the gate high frequency signal of the LDMOS transistor 30a is input, distortion occurs, and the distortion component voltage supplied from the detector 48 is read in step S3. Next, the distortion component voltage read in step S4 is stored in a register to obtain a stored value X1, and in step S5, it is determined whether or not the stored value X1 exceeds a preset initial value X0.

  As a result, when X0 ≧ X1, since the distortion is sufficiently small, the process proceeds to step S6, the initial value Vgs of the gate bias voltage at that time is held and applied to the gate of the LDMOS transistor 30a, and the process proceeds to step S3. On the other hand, if X0 <X1, the process proceeds to step S7, and the gate bias voltage is increased (or decreased) by a predetermined amount. The predetermined amount is one bit when the gate bias voltage is indicated by n bits.

  Thereafter, the gate bias voltage increased (or decreased) by a predetermined amount in step S8 is applied to the gate of the LDMOS transistor 30a, and the distortion component voltage Dn supplied from the detector 48 is read in step S9. Then, the distortion component voltage Dn read in step S10 is stored in a register to be a stored value Xn, and in step S11, it is determined whether or not the stored value Xn exceeds the stored value X1.

  As a result, when X1 ≧ Xn, since the distortion is reduced, the process proceeds to step S12, the gate bias voltage is increased (or decreased) by a predetermined amount, and the gate bias voltage is shifted in the same direction as step S7, and the process proceeds to step S8. move on.

  On the other hand, if X1 <Xn, since the distortion has increased, the process proceeds to step S13, the gate bias voltage is decreased (or increased) by a predetermined amount, the gate bias voltage is shifted in the opposite direction to step S7, and the process proceeds to step S8. .

  In this way, by repeating steps S8 to S13, a gate bias voltage for obtaining a specific idle current Idq1 at which the distortion becomes a minimum value is applied to the gate of the LDMOS transistor 30a. Further, since the detector 48 detects the distortion component voltage from which the high frequency signal is removed, the gate bias voltage can be optimized.

  FIG. 5 shows a circuit configuration diagram of a second embodiment of the distortion suppression circuit of the present invention. In the figure, the same parts as those in FIG. In FIG. 5, the power amplifier 30 amplifies the high frequency signal supplied from the input terminal 32 and outputs it from the output terminal 34. The power amplifier 30 performs power amplification using an LDMOS transistor 30a which is a field effect semiconductor element. The LDMOS transistor 30a is supplied with an input high-frequency signal at the gate and outputs an output high-frequency signal from the drain, and is configured to vary the gate bias voltage and the drain bias voltage.

  Directional couplers 36 and 38 are provided between the power amplifier 30 and the input terminal 32 and output terminal 34, and a part of the input high-frequency signal is branched by the directional coupler 36. A part of the output high-frequency signal is branched. A part of the input high-frequency signal branched by the directional coupler 36 is delayed by a predetermined delay amount by the delay unit 40 and supplied to the combiner 46.

  A part of the output high-frequency signal branched by the directional coupler 38 is phase-shifted by the phase shifter 42, attenuated by the attenuator 44, and supplied to the combiner 46. The delay amount of the delay device 40 corresponds to the delay amounts of the power amplifier 30, the phase shifter 42, and the attenuator 44. The phase shifter 42 inverts the phase of the output high frequency signal with respect to the phase of the input high frequency signal in the synthesizer 46. The attenuator 44 makes the input high-frequency signal level and the output high-frequency signal level in the synthesizer 46 the same. Therefore, the distortion component excluding the high-frequency signal component is extracted from the synthesizer 46. This distortion component is detected by the detector 48, and a distortion component voltage that is a detection output is supplied to the bias controller 60.

  The bias control unit 60 varies the resistance value of the variable resistor 52 according to the distortion component voltage to vary the gate bias voltage applied to the gate of the LDMOS transistor 30a in the power amplifier 30, and varies according to the distortion component voltage. By varying the resistance value of the resistor 62 and varying the drain bias voltage applied to the drain of the LDMOS transistor 30a, the distortion included in the output high frequency signal of the power amplifier 30 is optimized.

  Here, the LDMOS transistor 30a has input / output characteristics as shown in FIG. In FIG. 6, the solid line shows the input / output characteristics when the drain bias voltage is high, the broken line shows the input / output characteristics when the drain bias voltage is about the middle, and the alternate long and short dash line shows the input / output characteristics when the drain bias voltage is low. Is shown. That is, as the drain bias voltage is increased, the saturation power characteristic is improved and the linearity is improved. However, the power consumption increases as the drain bias voltage increases.

  The bias controller 60 varies the gate bias voltage of the LDMOS transistor 30a according to the flowchart shown in FIG. In FIG. 7, the initial value Vds preset as the drain bias voltage in step S20 is applied to the drain of the LDMOS transistor 30a, and the initial value Vgs preset as the gate bias voltage in step S21 is applied to the gate of the LDMOS transistor 30a. Apply to. When the gate high frequency signal of the LDMOS transistor 30a is inputted, distortion occurs, and the distortion component voltage D1 supplied from the detector 48 is read in step S22 and compared with the preset A value and B value. The A value is the minimum expected distortion component voltage value, and the value is the maximum expected distortion component voltage value (A <B).

  As a result, if D1> B, the initial value Vds of the drain bias is increased by a predetermined value F in step S24 and the process proceeds to step S22. If D1 <A, the initial value Vds of the drain bias is predetermined in step S25. The value F is decreased and the process proceeds to step S22.

  If A <D1 <B, the distortion component voltage D1 read in step S25 is stored in the register as the stored value X1, and whether the stored value X1 exceeds the preset initial value X0 in step S26. Determine whether or not.

  As a result, when X0 ≧ X1, since the distortion is sufficiently small, the process proceeds to step S27. The initial value Vgs of the gate bias voltage at that time is held and applied to the gate of the LDMOS transistor 30a, and the process proceeds to step S22. On the other hand, if X0 <X1, the process proceeds to step S28, and the gate bias voltage is increased (or decreased) by a predetermined amount. The predetermined amount is one bit when the gate bias voltage is indicated by n bits.

  Thereafter, the gate bias voltage increased (or decreased) by a predetermined amount in step S29 is applied to the gate of the LDMOS transistor 30a, and the distortion component voltage Dn supplied from the detector 48 is read in step S30 to obtain an A value, B Compare with each value.

  As a result, if D1> B, the initial value Vds of the drain bias is increased by a predetermined value F in step S31 and the process proceeds to step S29. If D1 <A, the initial value Vds of the drain bias is predetermined in step S32. The value F is decreased and the process proceeds to step S29.

  If A <D1 <B, the distortion component voltage D1 read in step S33 is stored in the register as the stored value X1, and in step S34, the stored value X1 exceeds the preset initial value X0. Determine whether or not.

  As a result, when X1 ≧ Xn, since the distortion is reduced, the process proceeds to step S35, the gate bias voltage is increased (or decreased) by a predetermined amount, and the gate bias voltage is shifted in the same direction as step S28, and the process proceeds to step S29. move on.

  On the other hand, if X1 <Xn, since the distortion has increased, the process proceeds to step S36, the gate bias voltage is decreased (or increased) by a predetermined amount, the gate bias voltage is shifted in the opposite direction to step S28, and the process proceeds to step S29. .

  In this way, by repeating steps S29 to S36, a gate bias voltage for obtaining a specific idle current Idq1 at which the distortion becomes a minimum value is applied to the gate of the LDMOS transistor 30a. Since the distortion component voltage from which the high-frequency signal is removed is detected, the gate bias voltage can be optimized.

  Further, when the input high-frequency signal level is low and the distortion component voltage value is lower than the minimum value A, the drain bias voltage can be decreased by a predetermined value F to reduce the power consumption of the LDMOS transistor 30a. When the level is high and the distortion component voltage value is higher than the maximum B value, the drain bias voltage can be increased by a predetermined value F to improve the saturation power characteristic of the LDMOS transistor 30a.

The directional couplers 36 and 38, the delay device 40, the phase shifter 42, the attenuator 44, the synthesizer 46, and the detector 48 correspond to the distortion component detecting means described in the claims, and the bias controllers 50 and 60 are provided. Corresponding to the gate bias control means, the bias control unit 60 corresponds to the drain bias control means, the B value corresponds to the first threshold value, and the A value corresponds to the second threshold value.
(Appendix 1)
In the distortion suppression circuit of the high frequency power amplifier using the LDMOS transistor,
Distortion component detection means for detecting distortion components generated in the high-frequency power amplifier by extracting and synthesizing a part of each of the input signal and output signal of the high-frequency power amplifier;
A distortion suppression circuit comprising gate bias control means for controlling the bias component of the LDMOS transistor to vary so as to minimize the distortion component.
(Appendix 2)
In the distortion suppression circuit according to attachment 1,
A distortion suppression circuit comprising drain bias control means for controlling the distortion component to increase by increasing a drain bias voltage of the LDMOS transistor when the distortion component exceeds a first threshold.
(Appendix 3)
In the distortion suppression circuit according to attachment 2,
The distortion suppression circuit according to claim 1, wherein the drain bias control means reduces the drain bias voltage of the LDMOS transistor to control power consumption when the distortion component becomes less than a second threshold value.
(Appendix 4)
In the distortion suppression circuit according to attachment 1,
The distortion component detection means includes a first directional coupler that branches a part of an input signal of the high-frequency power amplifier,
A delayer for delaying the signal branched by the first directional coupler;
A second directional coupler for branching a part of the output signal of the high-frequency power amplifier;
A phase shifter that shifts the phase of the signal branched by the second directional coupler;
An attenuator for attenuating the signal phase-shifted by the phase shifter;
A combiner that combines the signal delayed by the delay unit and the signal attenuated by the attenuator;
A distortion suppression circuit comprising a detector for detecting a signal synthesized by the synthesizer.

It is a circuit block diagram of an example of the conventional distortion suppression circuit. It is a circuit block diagram of 1st Embodiment of the distortion suppression circuit of this invention. It is an idle current and a distortion characteristic figure of a LDMOS transistor. 5 is a flowchart of variation processing executed by a bias control unit 50. It is a circuit block diagram of 2nd Embodiment of the distortion suppression circuit of this invention. It is an input / output characteristic diagram of an LDMOS transistor. 5 is a flowchart of a variation process executed by a bias control unit 60.

Explanation of symbols

DESCRIPTION OF SYMBOLS 30 Power amplifier 32 Input terminal 34 Output terminal 36,38 Directional coupler 40 Delay device 42 Phase shifter 44 Attenuator 46 Synthesizer 48 Detector 50, 60 Bias control part 52, 62 Variable resistance

Claims (3)

In the distortion suppression circuit of the high frequency power amplifier using the LDMOS transistor,
Distortion component detection means for detecting distortion components generated in the high-frequency power amplifier by extracting and synthesizing a part of each of the input signal and output signal of the high-frequency power amplifier;
A distortion suppression circuit comprising gate bias control means for controlling the bias component of the LDMOS transistor to vary so as to minimize the distortion component. The distortion suppression circuit according to claim 1,
A distortion suppression circuit comprising drain bias control means for controlling the distortion component to increase by increasing a drain bias voltage of the LDMOS transistor when the distortion component exceeds a first threshold. The distortion suppression circuit according to claim 2,
The distortion suppression circuit according to claim 1, wherein the drain bias control means reduces the drain bias voltage of the LDMOS transistor to control power consumption when the distortion component becomes less than a second threshold value.

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