JP2005151203A - Delay circuit designing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a delay circuit designing method which designs a delay circuit having desired design values of the rise propagation delay time and the fall propagation delay time, and those of the rise waveform deformation and the fall waveform deformation of output signals. <P>SOLUTION: Inverter gates 1, 2, 3, 4 on even-number stages are cascade-connected to form a delay circuit. The transient analysis simulation is executed with parameters using the gate lengths LP2, LN2, LP3, LN3 and the gate widths WP2, WN2, WP3, WN3 of p-channel MOS transistors 2a, 3a and n-channel MOS transistors 2b, 3b in the inverter gates 2, 3 other than the inverter gate 1 on the first stage nearest to an input terminal and the inverter gate 4 on the last stage to determine the values of their gate lengths and gate widths, thereby obtaining desired design rise propagation delay time, fall propagation delay time, rise waveform deformation, and fall waveform deformation. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method for designing a semiconductor integrated circuit, and more particularly to a delay circuit design method for designing a delay circuit formed in an integrated circuit having a MOS structure.

  FIG. 1 is a gate level circuit diagram showing a typical delay circuit used in a semiconductor integrated circuit. As shown in FIG. 1, the delay circuit is formed by cascading even-numbered inverter gates 10 and 11 along the signal propagation direction.

  FIG. 2 is a diagram illustrating the operation of the typical delay circuit of FIG. The gate length and gate width of the MOS transistors of the inverter gates 10 and 11 are configured with the utmost importance on minimizing the layout area. In addition, the propagation delay time and waveform rounding of the inverter gate are designed to be within the allowable range of the design specification, for example, the propagation delay time is 3 ns or less and the waveform rounding is 5 ns or less. No adjustment has been made to make them equal. Therefore, as shown in FIG. 2, in the signal propagation from the input signal Sin to the output signal Sout, the rising propagation delay time tpdLH and the falling propagation delay time tpdHL of the output signal Sout are not equal, and the rising of the output signal Sout The waveform round tr and the falling waveform round tf are not equal. That is, the delay circuit is tpdLH ≠ tpdHL and tr ≠ tf.

  Here, the rising propagation delay time tpdLH and the falling propagation delay time tpdHL are respectively the signal amplitude at the time of signal transition of the output signal Sout from the time point of the signal amplitude 50% at the time of signal transition (rising and falling) of the input signal Sin. This is the elapsed time up to 50%. The rising waveform round tr and the falling waveform round tf are times from the signal amplitude 20% of the output signal Sout to the signal amplitude 80%. When the delay circuit is configured with a normal CMOS circuit, the signal amplitude is equal to the power supply voltage.

  Further, as a conventional technique, a method described in the following Patent Document 1 (Japanese Patent Laid-Open No. 2000-22510) is known as a method for suppressing variations in propagation delay time of a delay circuit.

  FIG. 6 shows an RC delay circuit described in Patent Document 1. This RC delay circuit is configured by providing at least one set of delay circuits in which the first delay circuit 1011 and the second delay circuit 1012 are inserted in the column direction along the signal propagation direction. The first delay circuit includes a first RC circuit 1110 and a first inverter gate IV2 connected to an output side thereof, and a second delay circuit is connected to the second RC circuit 1120 and an output side thereof. A second inverter gate IV2. Here, the transition direction of the input potential of the first inverter gate accompanying the transition of the logic level of the input signal of the first delay circuit is opposite to the transition direction of the input potential of the second inverter gate. The first delay circuit 1011 and the second delay circuit 1012 are connected in cascade through a single-stage inverter gate.

  Thus, when the absolute value of the threshold value of the P-channel MOS transistor and the absolute value of the threshold value of the N-channel MOS transistor included in the RC delay circuit vary in the opposite directions, the first delay circuit 1011 and the second delay circuit By canceling the delay time variation with the delay circuit 1012, the overall delay time variation can be suppressed. In addition, the rising propagation delay time when the input signal changes from “L” level (low level) to “H” level (high level), and when the input signal changes from “H” level to “L” level. The delay time is substantially equal to the falling propagation delay time. This RC delay circuit is mainly intended to suppress delay time variation, and it is described that rising propagation delay time≈falling propagation delay time and propagation delay time can be made approximately equal. In other words, the RC delay circuit has a problem that the rising propagation delay time and the falling propagation delay time can only be approximately equal.

Further, it is impossible to obtain the relationship between the rising propagation delay time and the falling propagation delay time of the desired output signal, for example, the relationship of the rising propagation delay time> the falling propagation delay time, and the desired rising waveform rounding and falling waveform rounding. There's a problem.
JP 2000-22510 A

  As described above, the conventional delay circuit has a problem that the rising propagation delay time and the falling propagation delay time of the output signal of the delay circuit are not equal, and the rising waveform rounding and the falling waveform rounding are not equal.

  The delay circuit is intended to be used for controlling the signal propagation time of a certain signal line in the design process of the semiconductor integrated circuit, and the rise propagation delay time and the fall propagation delay time of the non-uniform output signal Uneven output signal rounding and falling waveform rounding are undesirable for the following reasons.

  Next, the reason for the above undesirable will be described. FIG. 7 shows signal waveforms for explaining an undesired operation using the delay circuit. In a circuit that holds data, such as a flip-flop circuit or a latch circuit, when the value of the data input signal (DATA) at that time is held by the rising waveform of the clock signal (CLOCK), a certain constant is obtained after the clock signal rises. There is a data holding time 20 in which the data input signal must be maintained at a constant value for a period of time (see FIG. 5B). If the data holding time 20 becomes shorter than the minimum value required for normal operation, a data holding time error occurs and the value of the data input signal cannot be held. Further, there is a data setting time 21 in which the data input signal must be held at a certain value for a certain period of time before the clock signal rises (see FIG. 5B). If the data setting time 21 becomes shorter than the minimum value required for normal operation, a data setting time error occurs and the value of the data input signal cannot be held.

  In the data input signal waveform shown in FIG. 7B, in the operation of holding the “H” level at the first rise of the clock signal, the data holding time 20 of the data input signal is smaller than the minimum value necessary for normal operation. Since the data holding time error has occurred, a delay circuit is inserted in the data input signal line to delay the data input signal as shown in the data input signal waveform of FIG. It is assumed that 22 is equal to or greater than the minimum value and the data retention time error is eliminated. However, in FIG. 7C, the data holding time error and the data setting time error do not occur at the first rise of the clock signal, but the rise propagation delay time of the non-uniform output signal in the delay circuit rises. Due to the falling propagation delay time and uneven rising and falling waveform rounding of the output signal, a delay circuit for delaying the falling timing of the data input signal is inserted to further delay the rising timing of the data input signal. As a result, at the second rise of the clock signal, the data setting time 23 becomes shorter than the minimum value necessary for its normal operation, a data setting time error occurs, and the value of the data input signal may be held. It becomes impossible (refer to (c) in the figure). As described above, in the conventional technique, the above-described problems may occur, and it is necessary to set the rising propagation delay time and the falling propagation delay time to be equal to each other, or to be able to individually set to appropriate values. Arise.

  The present invention has been made in view of the above problems, and each value of rising propagation delay time and falling propagation delay time from the input signal to the output signal of the delay circuit, rising waveform rounding and falling waveform rounding of the output signal. However, an object of the present invention is to provide a delay circuit design method capable of designing, for example, the rising propagation delay time and the falling propagation delay time to be equal, and the rising waveform round and the falling waveform round can be designed to be equal. .

  In order to achieve the above object, a delay circuit design method according to the present invention comprises connecting a plurality of inverter gates in cascade, connecting an input and an input terminal of a first-stage inverter gate of the plurality of inverter gates, and A delay circuit design method for designing a delay circuit formed by connecting an output terminal and an output terminal of a final stage inverter gate in a stage inverter gate, the P channel type of the inverter gates other than the final stage inverter gate Transient analysis simulation of an output signal output from the output terminal with respect to a predetermined input signal input to the input terminal, using as a variable at least one value of each gate length and each gate width of the MOS transistor and the N-channel MOS transistor The rise of the input signal obtained by the transient analysis simulation is performed. Rise propagation delay time from the transition of the output signal to the transition of the output signal, Fall propagation delay time from the fall of the input signal to the transition of the output signal, Rising waveform round and falling waveform round of the output signal Determining a combination of the variables to be a desired design value, and setting each gate length and each gate width of the P-channel MOS transistor and the N-channel MOS transistor based on the determined combination of variables. Is the first feature.

  In order to achieve the above object, a delay circuit design method according to the present invention comprises connecting a plurality of inverter gates in cascade, connecting an input and an input terminal of a first-stage inverter gate of the plurality of inverter gates, and A delay circuit design method for designing a delay circuit formed by connecting an output terminal and an output terminal of a final-stage inverter gate in an inverter gate of a stage, wherein the inverters other than the first-stage inverter gate and the final-stage inverter gate An output output from the output terminal for a predetermined input signal input to the input terminal, using as a variable at least one value of each gate length and each gate width of the P-channel MOS transistor and the N-channel MOS transistor of the gate Perform a transient analysis simulation of the signal. Rise propagation delay time from the rising edge of the input signal to the transition of the output signal, falling propagation delay time from the falling edge of the input signal to the transition of the output signal, rounding and falling edge of the rising waveform of the output signal Each value of the waveform rounding determines a combination of the variables that becomes a desired design value, and based on the determined combination of the variables, each gate length and each of the P-channel MOS transistor and the N-channel MOS transistor The second feature is to set the gate width.

  According to the delay circuit design method according to the first or second feature of the present invention, a combination of the variables having a desired design value can be obtained by executing a transient analysis simulation while changing the variables. As a result, the rise propagation delay time, the fall propagation delay time, and the rising waveform rounding and falling waveform rounding values of the output signal can be freely designed, for example, the rising propagation delay time and the falling propagation delay time. It is also possible to make the rising waveform round and the falling waveform round of the output signal equal.

  Preferably, in the delay circuit designing method according to the second aspect of the present invention, the design specification of the input signal is set as each gate width in the P-channel MOS transistor and the N-channel MOS transistor of the first-stage inverter gate. A third feature is to use a minimum value within a range that matches the above-described and use a minimum value or an optimum value determined by a semiconductor manufacturing process to be used as each gate length.

  According to the third feature, the gate capacitance of each MOS transistor constituting the first-stage inverter gate can be minimized, and the influence of the load capacitance and load resistance on the previous-stage circuit that drives the delay circuit can be reduced.

  More preferably, in the delay circuit design method according to the present invention having any one of the above features, the design specifications of the output signal as the gate width in the P-channel MOS transistor and the N-channel MOS transistor of the final stage inverter gate It is a fourth feature that the maximum value in a range matching the above is used, and the minimum value or the optimum value determined by the semiconductor manufacturing process to be used is used as each gate length.

  According to the fourth feature, the drive capability of the delay circuit can be increased sufficiently and the influence of the load resistance and load capacitance of the subsequent circuit to be driven by the delay circuit can be reduced.

  More preferably, in the delay circuit design method according to the present invention having any one of the above characteristics, a π-type or T-type RC circuit modeling a wiring load resistance and a wiring load capacitance is connected to the output terminal, and the RC A fifth feature is that the same delay circuit as the delay circuit to be designed is connected to the output of the circuit.

  According to the fifth feature, since the output signal waveform in the transient analysis simulation can be approximated to the actual drive waveform of the circuit, the simulation accuracy can be increased.

  An embodiment of a delay circuit design method according to the present invention (hereinafter simply referred to as “method of the present invention”) will be described with reference to the drawings.

  FIG. 3 is a circuit diagram showing an embodiment of a delay circuit to be designed by the method of the present invention. The delay circuit 100 shown in FIG. 3 has a configuration in which inverter gates 1, 2, 3, and 4 are connected in cascade along the signal propagation direction. Further, four stages (even stages) of inverter gates are provided between the input terminal A and the output terminal Y so that the phase of the input signal does not reverse. The first-stage inverter gate 1 includes a P-channel MOS transistor 1a having a source connected to the power supply VDD and an N-channel MOS transistor 1b having a source connected to the power supply GND. Similarly, the inverter gates 2, 3, 4 are composed of P-channel MOS transistors 2a, 3a, 4a and N-channel MOS transistors 2b, 3b, 4b.

  In order to perform analog circuit simulation (transient analysis simulation) for transient analysis of the delay circuit 100 described above, the output terminal Y of the delay circuit 100 is a π-type RC circuit that models wiring load resistance and wiring load capacitance. 200 is connected, and a delay circuit 101 that is the same circuit as the delay circuit 100 is connected to the output Sout of the π-type RC circuit 200. The π-type RC circuit 200 and the delay circuit 101 are virtual circuits provided for convenience for simulation.

  When actually designing a semiconductor integrated circuit, the output terminal Y of the delay circuit 100 is connected to a subsequent circuit using a metal wiring such as aluminum or copper, and a metal wiring is used between the connection of the delay circuit 100 and the subsequent circuit. Wiring load resistance and wiring load capacitance always exist, and in order to perform simulation close to the actual semiconductor integrated circuit state and with high accuracy, the wiring load resistance and wiring load capacitance due to this metal wiring should be considered. . For this reason, it is necessary to model the wiring load resistance and the wiring load capacity of the actual metal wiring as in the π-type RC circuit 200 and to simulate the delay circuit 100. This makes it possible to accurately simulate the characteristics of the delay circuit.

  The first-stage inverter gate 1 closest to the input terminal A shown in FIG. 3 has the gate width WP1 of the P-channel MOS transistor 1a and the gate width WN1 of the N-channel MOS transistor 1b within a range that matches the design specifications of the input signal. The input load resistance and the input load capacity are reduced as much as possible. The gate length LP1 of the P-channel MOS transistor 1a of the inverter gate 1 and the gate length LN1 of the N-channel MOS transistor 1b use the minimum value or the optimum value of the semiconductor manufacturing process.

  The optimum value here is estimated so that as the gate length (channel length) of the MOS transistor becomes shorter, the gate threshold voltage does not decrease due to the short channel effect, and further, the increase in off-leakage current does not occur. Value. Therefore, the minimum value or optimum value of the semiconductor manufacturing process is used as the minimum value on the design rule. In addition, as the design specification of the input signal, for example, the inversion level of the input signal can be considered, but the minimum value of the semiconductor manufacturing process (or the minimum value in the design rule) is used as the gate width WP1 and the gate width WN1. If the design specification of the input signal can be satisfied, the minimum value of the semiconductor manufacturing process is used.

  The reason why the gate length and gate width of the inverter gate 1 are reduced will be described below. As a result of changing the gate length and the gate width of the inverter gate 1 so that the rising propagation delay time and the falling propagation delay time are equal, the rising waveform rounding and the falling waveform rounding are also equal. Assume that the gate length and gate width are increased, and the input load resistance and input load capacitance are increased. At this time, since the output of the pre-stage circuit is connected to the gate which is the input of the inverter gate 1, the influence of the load resistance and load capacity on the pre-stage circuit becomes large, and the pre-stage circuit cannot drive the inverter gate 1. Sometimes. As a result, a malfunction occurs in the operation of the semiconductor integrated circuit, and the normal delay circuit that is the object of the present invention cannot be achieved.

  As described above, by reducing the gate length and gate width of the inverter gate 1, in the actual semiconductor integrated circuit design, the influence of the load resistance and load capacitance on the previous circuit that drives the delay circuit 100 is reduced. Therefore, the delay circuit that is the object of the present invention can be achieved.

  In the final stage inverter gate 4 closest to the output terminal Y shown in FIG. 3, the gate width WP4 of the P-channel MOS transistor 4a and the gate width WN4 of the N-channel MOS transistor 4b are within a range that matches the design specifications of the output signal. In FIG. 4, the output drive capacity is increased as much as possible. The gate length LP4 of the P-channel MOS transistor 4a of the inverter gate 4 and the gate length LN4 of the N-channel MOS transistor 4b use the minimum value or the optimum value of the semiconductor manufacturing process.

  The optimum value here is estimated so that as the gate length (channel length) of the MOS transistor becomes shorter, the gate threshold voltage does not decrease due to the short channel effect, and further, the increase in off-leakage current does not occur. Value. As the design specifications of the output signal, a layout area that can be allocated as the final stage inverter gate 4, a through DC current generated in the final stage inverter gate 4 when the input signal of the final stage inverter gate 4 transitions, and the like are assumed. Therefore, the gate width WP4 and the gate width WN4 naturally have an upper limit value, and are within a range not less than the lower limit value and not more than the upper limit value sufficient to drive the subsequent circuit.

  The reason why the gate length of the inverter gate 4 is reduced and the gate width is increased will be described below. As a result of changing the gate length and the gate width of the inverter gate 4 so that the rising propagation delay time and the falling propagation delay time are equal, the rising waveform rounding and the falling waveform rounding are also equal. Suppose that the gate length is large, the gate width is small, and the output drive capability is small. At this time, since the output of the inverter gate 4 is connected to the input of the post-stage circuit, the influence of the load resistance and load capacitance of the post-stage circuit increases, and the inverter gate 4 may not be able to drive the post-stage circuit. As a result, a malfunction occurs in the operation of the semiconductor integrated circuit, and the normal delay circuit that is the object of the present invention cannot be achieved.

  As described above, by reducing the gate length of the inverter gate 4 and increasing the gate width, in the actual semiconductor integrated circuit design, the influence of the load resistance and load capacitance of the subsequent circuit driven by the delay circuit 100 is reduced. The delay circuit that is the object of the present invention can be achieved.

  FIG. 4 is a signal waveform diagram showing an operation of delay circuit 100 shown in FIG. When the input signal Sin is input to the input Sin of the delay circuit 100 shown in FIG. 3 in the order of rising and falling as shown in FIG. 4, the output Sout of the π-type RC circuit 200 shown in FIG. As shown in FIG. 4, the transition occurs in the order of rising and falling.

  Here, the rising propagation delay time tpdLH and the falling propagation delay time tpdHL are times from when the input signal Sin reaches the power supply voltage 50% to when the output signal Sout reaches the power supply voltage 50%. The rising waveform round tr and the falling waveform round tf are transition times between the power supply voltage 20% and the power supply voltage 80% of the output signal Sout.

  In the signal propagation from the input signal Sin to the output signal Sout shown in FIG. 3, the rising propagation delay time tpdLH and the falling propagation delay time tpdHL of the output signal Sout shown in FIG. 4 are equal, and the rising waveform round tr of the output signal Sout is shown. When designing a delay circuit having the same falling waveform round tf, that is, a delay circuit having tpdLH = tpdHL and tr = tf, the transient analysis simulation of the simulation circuit shown in FIG. 3 is performed by tpdLH = tpdHL and tr = tf. Thus, the optimum values of the gate lengths and the gate widths of the P-channel MOS transistor and the N-channel MOS transistor of the inverter gates 2 and 3 are obtained, and the sizes thereof are determined.

  In the simulation described above, the rising propagation delay time tpdLH and the falling propagation delay time tptHL shown in FIG. 4 are the same, and the rising waveform round tr and the falling waveform round tf are equal to each other at the input terminal A shown in FIG. In the inverter gates 2 and 3 other than the nearest first-stage inverter gate 1 and the last-stage inverter gate 4 closest to the output terminal Y, the gate lengths LP2 of the P-channel MOS transistors 2a and 3a and the N-channel MOS transistors 2b and 3b, LN2, LP3, LN3 and the respective gate widths WP2, WN2, WP3, WN3 are simultaneously controlled to obtain optimum values of the gate length and gate width.

  The control here uses the sizes of the gate length and gate width of the P-channel MOS transistor and the N-channel MOS transistor of the inverter gates 2 and 3 as variables, and tpdLH is a target characteristic for the variables. = TpdHL and tr = tf are satisfied, or the circuit simulation is repeated until the optimized solution is found, and the value of the variable is obtained.

  In the analog circuit simulation, a transient analysis simulator (Hspice or the like) having an optimization function such as automatically generating model parameter values and device values from specified electrical specifications and measurement data is used.

  Thus, the gate length and gate width of the result obtained from the simulation are determined as the optimum gate length and gate width of the P-channel MOS transistor and N-channel MOS transistor of the inverter gates 2 and 3. .

  Depending on the optimum gate length and gate width of the P-channel MOS transistor and the N-channel MOS transistor of the inverter gates 2 and 3, the input Sin of the delay circuit 100 shown in FIG. 3 is changed to the output Sout of the π-type RC circuit 200. In signal propagation, a delay circuit in which a desired rising propagation delay time tpdLH and a falling propagation delay time tpdHL are equal to 1 ns, for example, and the rising waveform round tr and the falling waveform round tf of the output signal Sout are designed to be the same is designed. Is possible.

  FIG. 5 is a layout pattern in which four inverter gates of the delay circuit 100 shown in FIG. 3 according to the present embodiment are arranged. The inverter gates 1, 2, 3, and 4 are formed by disposing each MOS transistor in a P-channel MOS transistor formation region and an N-channel MOS transistor formation region.

  The gate lengths LP1 and LN1 and the gate widths WP1 and WN1 of the inverter gate 1 are designed so that the input load resistance and the input load capacitance are as small as possible. The gate lengths LP4 and LN4 and the gate widths WP4 and WN4 of the inverter gate 4 are designed so that the output drive capability is as large as possible. Here, the gate width is set not to cross the power supply VDD and the power supply GND.

  The gate lengths LP2, LN2, LP3, LN3 and the gate widths WP2, WN2, WP3, WN3 of the P-channel MOS transistor and the N-channel MOS transistor of the inverter gates 2, 3 have a desired rise propagation delay time and fall The optimal gate length and gate width are determined by simulation so that the propagation delay times are equal and the rising waveform round and the falling waveform round are equal.

  The net list of the delay circuit 100 in FIG. 3, the signal propagation delay time and the signal waveform rounding, which are the characteristics of the delay circuit 100, and the layout pattern in FIG. 5 are standardized by registering them in the CAD as standard cells.

  In the above-described embodiment, an example in which four inverter gates are connected in cascade along the signal propagation direction is shown. However, the number of inverter gates may be an even number, for example, six or eight. This makes it possible to have a larger signal propagation delay time. Further, a delay circuit having an odd number of inverter gates and a reverse polarity delay signal may be used.

  Furthermore, in the above embodiment, the simulation is performed using the gate length and gate width of the P-channel MOS transistor and the N-channel MOS transistor of the inverter gate included in the delay circuit as variables. For example, the gate length is a fixed value. Then, simulation may be performed with the gate width as a variable, or simulation may be performed with the gate length as a variable and the gate width as a fixed value.

  Further, the RC circuit 200 used for the simulation is not limited to the π-type circuit illustrated in FIG. 3, and may be a T-type circuit, for example.

  In the above embodiment, the control is performed so that the rising propagation delay time and the falling propagation delay time are equal, and the rising waveform rounding and the falling waveform rounding are equal. However, the rising propagation delay time and the falling propagation delay time are the same. The rising waveform round and the falling waveform round may be different, or the rising propagation delay time and the falling propagation delay time may be different so that the rising waveform round and the falling waveform round are equal.

  As described above, according to the method for designing the delay circuit of the present invention, the simulation is performed using the gate length and gate width of the P-channel MOS transistor and the N-channel MOS transistor of the inverter gate included in the circuit as variables. By determining the gate length and the gate width, it is possible to have a desired rising propagation delay time and falling propagation delay time, and rising waveform rounding and falling waveform rounding. As a result, there is an effect of suppressing occurrence of an undesirable operation when the delay circuit described above is used.

Circuit diagram showing an example of a typical conventional delay circuit Signal waveform diagram for explaining the operation of a conventional typical delay circuit The circuit diagram which shows one Example of the delay circuit used as the design object by the delay circuit design method concerning this invention Signal waveform diagram showing operation of delay circuit to be designed by delay circuit designing method according to the present invention Layout pattern diagram showing a layout example of a delay circuit to be designed by the delay circuit design method according to the present invention Circuit diagram showing RC delay circuit disclosed in Patent Document 1 Signal waveform diagram for explaining an undesirable operation state (problem) in the conventional delay circuit

Explanation of symbols

1, 2, 3, 4: Inverter gates 10, 11: Inverter gates 1a, 2a, 3a, 4a: P-channel MOS transistors 1b, 2b, 3b, 4b: N-channel MOS transistors LP1, LP2, LP3, LP4: P-channel MOS transistor gate lengths WP1, WP2, WP3, WP4: P-channel MOS transistor gate widths LN1, LN2, LN3, LN4: N-channel MOS transistor gate lengths WN1, WN2, WN3, WN4: N-channel MOS transistor gate widths R1, R2, R3: resistors C1, C2, C3, C4: capacitance 100: delay circuit 101: delay circuit 200: π-type RC circuit 20, 22: data holding time 21, 23: data setting Time 1011: First delay circuit (conventional technique of Patent Document 1) )
1012: Second delay circuit (prior art of Patent Document 1)
1110: First RC circuit (prior art of Patent Document 1)
1120: 2nd RC circuit (prior art of patent document 1)

Claims (6)

Connect multiple stages of inverter gates in cascade, connect the input and input terminals of the first stage inverter gate of the multiple stages of inverter gates, and connect the output and output terminals of the final stage inverter gate of the multiple stages of inverter gates. A delay circuit design method for designing a connected delay circuit,
A predetermined input that is input to the input terminal using at least one value of each gate length and each gate width of the P-channel MOS transistor and the N-channel MOS transistor of the inverter gate other than the final-stage inverter gate as a variable Perform a transient analysis simulation of the output signal output from the output terminal for the signal,
Rise propagation delay time from the rise of the input signal to the transition of the output signal obtained by the transient analysis simulation, fall propagation delay time from the fall of the input signal to the transition of the output signal, Each value of the rising waveform rounding and the falling waveform rounding determines a combination of the variables that becomes a desired design value,
A delay circuit design method comprising: setting each gate length and each gate width of the P-channel MOS transistor and the N-channel MOS transistor based on the determined combination of variables. Connect multiple stages of inverter gates in cascade, connect the input and input terminals of the first stage inverter gate of the multiple stages of inverter gates, and connect the output and output terminals of the final stage inverter gate of the multiple stages of inverter gates. A delay circuit design method for designing a connected delay circuit,
Using at least one value of each gate length and each gate width of the P-channel MOS transistor and N-channel MOS transistor of the inverter gate other than the first-stage inverter gate and the final-stage inverter gate as a variable, Perform a transient analysis simulation of the output signal output from the output terminal with respect to a predetermined input signal to be input,
Rise propagation delay time from the rising edge of the input signal to the transition of the output signal obtained by the transient analysis simulation, falling propagation delay time from the falling edge of the input signal to the transition of the output signal, Each value of the rising waveform rounding and the falling waveform rounding determines a combination of the variables that becomes a desired design value,
A delay circuit design method comprising: setting each gate length and each gate width of the P-channel MOS transistor and the N-channel MOS transistor based on the determined combination of variables.   In the first-stage inverter gate P-channel MOS transistor and N-channel MOS transistor, a semiconductor manufacturing process to be used as each gate width by using a minimum value within a range that matches the design specification of the input signal as each gate width 3. The delay circuit design method according to claim 2, wherein a minimum value or an optimum value determined by the following equation is used.   In the P-channel MOS transistor and the N-channel MOS transistor of the final stage inverter gate, the maximum value within the range that matches the design specifications of the output signal is used as the gate width, and the semiconductor manufacturing used as each gate length 4. The delay circuit design method according to claim 1, wherein a minimum value or an optimum value determined by a process is used. A π-type or T-type RC circuit modeling the wiring load resistance and the wiring load capacitance is connected to the output terminal,
The delay circuit design method according to claim 1, wherein the same delay circuit as the delay circuit to be designed is connected to the output of the RC circuit.   A delay circuit designed by the delay circuit design method according to claim 1.

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