JP2005151184A - Digital signal processing circuit, and sound signal recording and reproducing apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a digital signal processing circuit, by which a circuit scale is reduced and power consumption is saved. <P>SOLUTION: A sound signal, inputted from a microphone 1, is oversampled by an oversampling circuit 4. When a 24-bit digital signal obtained by oversampling is inputted to an n-order delta-sigma modulation circuit 5, first, an operation is performed as a digital filter function part 5a so as to erase the noise. Then, the operation is performed as a delta-sigma modulation function part 5b. Accordingly, the signal is converted into a 6-bit digital signal and outputted to a PWM modulation circuit 6. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a digital signal processing circuit used for audio signal processing and the like, and an audio signal recording / reproducing apparatus having the digital signal processing circuit, and more particularly, digital signal processing having a function as delta-sigma modulation or a filter. The present invention relates to a circuit and an audio signal recording / reproducing apparatus having the digital signal processing circuit.

  Conventionally used audio signal reproduction apparatuses include a delta-sigma modulation circuit for 1-bit digital encoding of an audio signal, which is an input analog signal, due to stability in a transmission path of the 1-bit digital encoding system. (See Patent Document 1). In this audio signal reproducing apparatus, an input audio signal, which is an analog signal, is converted into a 1-bit digital signal by delta-sigma modulation and transmitted to a reproduction portion at a subsequent stage. In the reproduction portion, the 1-bit digital signal is demodulated into an analog audio signal by, for example, a low-order low-pass filter to reproduce the audio.

  Further, as a conventional audio signal reproducing apparatus, one having a configuration as shown in FIG. 12 is used. The audio signal reproduction device in FIG. 12 encodes a microphone 1 to which audio is input, an AD converter 2 that converts the audio signal input from the microphone 1 into a 24-bit digital signal, and a signal from the AD converter 2. An encoding circuit 3; an oversampling circuit 4 for oversampling the 24-bit digital signal encoded by the encoding circuit 3 to perform multi-bit digital encoding; and a PCM (Pulse Code Modulation) signal that is a multi-bit digital signal Delta-sigma modulation circuit 100 that generates 1-bit PDM (Pulse Density Modulation) signals for the left channel and right channel, and the left channel that is a 1-bit digital signal generated by delta-sigma modulation circuit 100 Convert PDM signals for the right and right channels into analog signals Low-pass filters (LPF) 9 and 10 that remove high-frequency components from the analog signals from the switching amplifiers 7 and 8, and speakers 11 and 12 that reproduce and output audio from the analog signals from the LPFs 9 and 10. And comprising.

  FIG. 13 shows the configuration of the delta-sigma modulation circuit 100 used in the audio signal reproducing apparatus having such a configuration. The delta-sigma modulation circuit 100 shown in FIG. 13 includes an input terminal IN, an output terminal OUT, multipliers 101 to 111, adders 112 to 119, a quantizer 120, and delay units 121 to 128. -A sigma modulation circuit. FIG. 13 shows a configuration for one of the left and right channels, and actually a 7th-order delta-sigma modulation circuit configured as shown in FIG. 13 is provided for each of the left and right channels.

In the delta-sigma modulation circuit 100, the multiplication coefficients m1 to m11 of the multipliers 101 to 111 are set for the left and right channels, respectively. Further, the adders 112 to 118 perform the integration operation by feeding back the signals of the delay units 121 to 127 to the adders 112 to 118, respectively. Further, the signals from the adders 114, 116, and 118 are fed back to the adders 113, 115, and 117 through the delay units 123, 125, and 127 and the multipliers 108, 109, and 110, respectively. Since the delta-sigma modulation circuit 100 functions as an IIR (Infinite-duration Impulse Response) filter that performs noise shaping to move the quantization noise to a high frequency, the high frequency quantization noise is removed in the LPFs 9 and 10. The speakers 11 and 12 can reproduce and output sound.
Japanese Patent Laid-Open No. 10-322215

  In the audio signal reproducing apparatus in Patent Document 1 and the audio signal reproducing apparatus having the configuration as shown in FIG. 12, when an automatic level control function for detecting the signal level of the input audio signal and changing the signal level is provided, it is input. The signal level of the noise signal superimposed on the audio signal also changes with the audio signal. Therefore, in order to amplify an audio signal having a low signal level, when the amplification factor is increased by the automatic level control function, the signal level of the noise signal input together with the audio signal is amplified and increased. Therefore, sound including noise is reproduced and output. In addition, in order to remove such a noise signal, a band pass filter (BPF) that allows the voice signal to pass through is necessary to remove the noise signal.

  Further, when the delta-sigma modulation circuit is configured as shown in Patent Document 1 or FIG. 13, it is difficult to mount on a LSI (Large Scale Integration) because the circuit scale is large and the power consumption is large. For this reason, the audio signal reproduction apparatus cannot be reduced in size and weight. Furthermore, in the audio signal reproduction apparatus of Patent Document 1 or FIG. 12, in order to reproduce sound faithful to the original sound, the sampling frequency of the 1-bit digital signal output from the delta-sigma modulation circuit is set to 2.8 MHz or 5. It is necessary to set a high frequency such as 6 MHz. Therefore, it is necessary to operate the oversampling circuit and the delta-sigma modulation circuit at a high frequency, and the power consumption is further increased. Furthermore, it is necessary to perform sufficient noise shielding to prevent the influence of unnecessary radiation due to the high sampling frequency, which causes the apparatus to be increased in size and weight.

  In view of such problems, it is an object of the present invention to provide a digital signal processing circuit that reduces the circuit scale and reduces power consumption. Another object of the present invention is to provide an audio signal recording / reproducing apparatus having a digital signal processing circuit having a function other than the delta-sigma modulation function.

  In order to achieve the above object, a digital signal processing circuit according to the present invention includes a plurality of multipliers for multiplying a set multiplication coefficient, an adder for adding and subtracting signals from the plurality of multipliers, and an operation of the adder. A storage unit that stores the resulting signal and each input signal in each of the plurality of storage areas, and a quantizer that quantizes the signal that is the final operation result stored in the storage unit, When a part of the storage area of the storage unit is a first storage area and the storage area other than the first storage area of the storage unit is a second storage area, each storage of the first storage area By operating the plurality of multipliers and the adder repeatedly using an area, the digital filter function unit that removes a noise component from the input signal is operated, and then each storage area of the second storage area is Using said It operates as a delta-sigma modulation function unit that performs delta-sigma modulation on the signal that has passed through the digital filter function unit by repeatedly operating the multiplier and the adder and then quantizing with the quantizer It is characterized by doing.

  According to such a digital signal processing circuit, the digital filter function unit and the delta-sigma modulation are performed by using the storage area of the storage unit as a delay unit and repeatedly performing arithmetic processing in the multiplier and the adder. Operation as a functional unit can be performed.

  Further, the digital signal processing circuit of the present invention includes a plurality of multipliers for multiplying a set multiplication coefficient, an adder for adding / subtracting signals from the plurality of multipliers, a signal and an input as an operation result of the adder. A storage unit that stores each of the signals to be stored in each of a plurality of storage areas, and a quantizer that quantizes a signal that is a final operation result stored in the storage unit, the storage unit of the storage A part of the area is a first storage area, a part of the storage area other than the first storage area of the storage unit is a second storage area, and a part other than the first storage area and the second storage area of the storage unit When a part of the storage area is a third storage area, the plurality of multipliers and the adder are operated repeatedly using each storage area of the first storage area. Digital filter machine that removes noise components And the sampling frequency of the signal that has passed through the digital filter function unit is increased by repeatedly operating the plurality of multipliers and the adder using each storage area of the third storage area. After operating as an oversampling function unit, the plurality of multipliers and the adder are repeatedly operated using each storage area of the second storage area, and then quantized by the quantizer. It operates as a delta-sigma modulation function unit that performs delta-sigma modulation on the signal oversampled by the sampling function unit.

  According to such a digital signal processing circuit, the digital filter function unit and the oversampling function unit are obtained by using the storage area of the storage unit as a delay unit and repeatedly performing arithmetic processing in the multiplier and the adder. In addition, the operation as the delta-sigma modulation function unit can be performed. In such a digital signal processing circuit, when the oversampling function unit performs oversampling to a sampling frequency of n times, the oversampling function unit and the oversampling function unit The delta-sigma modulation function unit operates for n cycles.

  Further, in each of the digital signal processing circuits described above, an operation result storage unit that temporarily stores a signal that is an operation result of the adder, and an input signal, a signal from the operation result storage unit, and a signal whose value is 0 A first selection unit that selects one signal from the three signals; a first selection unit that selects one signal from among a plurality of signals stored in the plurality of storage areas of the storage unit and a value of 0; And a third selection unit that selects one signal from a plurality of signals stored in the plurality of storage areas of the storage unit and a signal having a value of 0, and the multiplier A first multiplier to which the signal selected by the first selection unit is given, a second multiplier to which the signal selected by the second selection unit is given and non-inverted output to the adder, When the signal selected by the third selector is given And a third multiplier for the inverted output to the adder as well. At this time, in the first multiplier, the output may be switched between an inverted output and a non-inverted output.

  In each of the digital signal processing circuits described above, the multiplier is a shifter that shifts a binary digit of an input signal, and the number of digits shifted by the multiplier and the multiplier and the adder The multiplication coefficient is set according to the number of repetitions.

  The audio signal recording / reproducing apparatus of the present invention includes an oversampling circuit for increasing a sampling frequency of an input digital signal, a digital signal oversampled by the oversampling circuit, and the digital filter function unit, One of the above-described digital signal processing circuits provided with the delta-sigma modulation function unit, and a PWM modulation circuit that performs pulse width modulation on the digital signal arithmetically processed by the digital signal processing circuit. .

  With this configuration, when external sound such as a microphone is converted into a digital signal and input, noise is removed by the digital filter function unit in the digital signal processing circuit, and then the delta-sigma Delta-sigma modulation is performed in the modulation function unit, and the number of bits of the digital signal is lowered.

  In such an audio signal recording / reproducing apparatus, a downsampling circuit for lowering the sampling frequency of the digital signal processed by the digital filter function unit of the digital signal processing circuit, and a digital signal output from the downsampling circuit are recorded. And a recording unit for recording on a medium. At this time, the recording unit may include a compression unit that compresses the digital signal. Further, a signal reading unit that reads a digital signal recorded on the recording medium may be provided, and the digital signal read by the signal reading unit may be provided to the oversampling circuit. At this time, the signal reading unit may include a decompressing unit that decompresses the digital signal read from the recording medium.

  The audio signal recording / reproducing apparatus according to the present invention includes any one of the above-described digital signal processing circuits including the digital filter function unit, the oversampling function unit, and the delta-sigma modulation function unit, and the digital signal processing circuit. And a PWM modulation circuit that performs pulse width modulation on the digital signal that has been arithmetically processed.

  With this configuration, when external sound such as a microphone is converted into a digital signal and input, noise is removed by the digital filter function unit in the digital signal processing circuit, and the oversampling function unit After the sampling frequency is increased, the delta-sigma modulation function unit performs delta-sigma modulation to reduce the number of bits of the digital signal.

  Such an audio signal recording / reproducing apparatus may include a recording unit that records the digital signal processed by the digital filter function unit of the digital signal processing circuit on a recording medium. At this time, the recording unit may include a compression unit that compresses the digital signal. In addition, a signal reading unit that reads a digital signal from a recording medium may be provided, and the digital signal read from the signal reading unit may be provided to the oversampling function unit of the digital signal processing circuit. At this time, the signal reading unit may include a decompressing unit that decompresses the digital signal read from the recording medium.

  Further, in each of the above audio signal recording / reproducing apparatuses, when the recording unit records a digital signal on a recording medium, the entire storage area in the storage unit of the digital signal processing circuit is used as the digital filter function unit. It doesn't matter.

  According to the present invention, the digital filter function and the delta-sigma function can be provided by one digital processing circuit, and the digital elements are implemented by repeatedly operating the arithmetic elements constituting the digital processing circuit. The circuit scale of the processing circuit can be reduced. Further, in the audio signal recording / reproducing apparatus provided with such a digital processing circuit, by providing one digital processing circuit, a digital filter function and a delta-sigma function can be realized. There is no need to configure the filter circuit and the delta-sigma modulation circuit separately. Therefore, the apparatus can be reduced in size and weight. Furthermore, by providing an oversampling function unit in the digital signal processing circuit, the audio signal recording / reproducing apparatus can be further miniaturized.

<First Embodiment>
A first embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the internal configuration of the audio signal recording / reproducing apparatus of this embodiment. FIG. 2 is a block diagram showing the configuration of the signal processing circuit of the audio signal recording / reproducing apparatus of FIG. In the audio signal recording / reproducing apparatus of FIG. 1, parts used for the same purpose as those of the audio signal reproducing apparatus of FIG. 12 are denoted by the same reference numerals, and detailed description thereof is omitted.

  1 includes a microphone 1, an AD converter 2, an encoding circuit 3, an oversampling circuit 4, switching amplifiers 7 and 8, LPFs 9 and 10, speakers 11 and 12, and an oversampling circuit. An n-order delta-sigma modulation circuit 5 that performs delta-sigma modulation on the 24-bit PCM signal oversampled by the sampling circuit 4 to generate 6-bit PCM signals for the left channel and the right channel; -PWM modulation circuit 6 that applies pulse width modulation (PWM modulation) to the PCM signals for the left channel and the right channel generated by the sigma modulation circuit 5, and recording such as an optical disk or magneto-optical disk on which an audio signal is recorded An optical pickup device 14 that reads and writes audio signals to and from the media 13, and an optical pickup. The decompression circuit 15 that decompresses the audio signal read by the up device 14 in accordance with a data compression method such as an ATRAC (Adaptive TRansform Acoustic Coding) method, and the 24-bit PCM from which noise has been removed by the n-order delta-sigma modulation circuit 5 A down-sampling circuit 16 that down-samples the signal, and a compression circuit 17 that compresses a 24-bit digital signal from the down-sampling circuit 16 according to a data compression method such as the ATRAC method.

  In the audio signal recording / reproducing apparatus having such a configuration, when audio is input to the microphone 1, an audio signal that is an analog signal is supplied to the AD converter 2 and a digital signal having a sampling frequency fs (fs = 44.1 kHz). Is converted to The audio signal to be a digital signal is encoded by the encoding circuit 3 to be converted into a 24-bit digital signal S1, and then converted into a PCM signal S2 having a sampling frequency of 8 fs by the oversampling circuit 4. The PCM signal S2 having a sampling frequency of 8 fs is supplied to the nth-order delta-sigma modulation circuit 5.

  The n-order delta-sigma modulation circuit 5 includes an α-order digital filter function unit 5a that functions as a high-pass filter (HPF), LPF, BPF, or notch filter that removes noise from the input PCM signal S2, and a digital filter function unit 5a. And a delta-sigma modulation function unit 5b that performs n-α-th order delta-sigma modulation on the PCM signal S2 from which noise has been removed. The n-order delta-sigma modulation circuit 5 will be described later. Then, the 6-bit PCM signal S3 for the left channel and the 6-bit PCM signal S4 for the right channel generated by the delta-sigma modulation function unit 5b of the n-th order delta-sigma modulation circuit 5 are supplied to the PWM modulation circuit 6. It is done.

  The PWM modulation circuit 6 generates a 1-bit PWM signal S5 for the left channel by performing PWM modulation based on the PCM signal S3 for the left channel, and performs PWM modulation based on the PCM signal S4 for the right channel. To generate a 1-bit PWM signal S6 for the right channel. When the PWM signals S5 and S6 are supplied to the switching amplifiers 7 and 8, respectively, the left channel PWM signal S5 is converted into an analog signal by the switching amplifier 7 and amplified, and the right channel PWM signal S6 is converted into an analog signal. It is converted into an analog signal by the switching amplifier 8 and amplified. Thereafter, the high frequency component of the analog signal from the switching amplifier 7 is removed by the LPF 9 and the left channel sound is reproduced by the speaker 11, and the high frequency component of the analog signal from the switching amplifier 8 is removed by the LPF 10 and the speaker. 12, the right channel sound is reproduced.

  Also, when playing back an audio signal recorded on the recording medium 13, the audio signal, which is a digital signal read from the recording medium 13 by the optical pickup device 14, is decompressed by the expansion circuit 15 in accordance with a compression method such as the ATRAC method. Is done. The 24-bit digital signal S1a decompressed by the decompression circuit 15 is a digital signal having a sampling frequency fs. When this digital signal S1a is supplied to the oversampling circuit 4, as with the digital signal S1 from the encoding circuit 3, it is oversampled at a sampling frequency of 8 fs to generate a 24-bit PCM signal S2. Thereafter, the oversampling circuit 4, the n-order delta-sigma modulation circuit 5, the PWM modulation circuit 6, the switching amplifiers 7 and 8, and the LPFs 9 and 10 perform the above-described operation, and sound is reproduced from the speakers 11 and 12.

  When recording the sound input to the microphone 1 on the recording medium 13, the 24-bit PCM signal S2 generated from the sound signal from the microphone 1 is given to the n-order delta-sigma modulation circuit 5, and the digital filter function The PCM signal S2a from which noise has been removed by the unit 5a is applied to the downsampling circuit 16. In the downsampling circuit 16, the sampling frequency of the 24-bit PCM signal S2a is converted from 8 fs to fs, and is converted to the same sampling frequency as the PCM signals S1 and S1a input to the oversampling circuit 4. The 24-bit PCM signal S1b having the sampling frequency fs is compressed in the compression circuit 17 in accordance with a compression method such as the ATRAC method. When a digital signal obtained by compressing data by the compression circuit 17 is applied to the optical pickup device 14, the applied digital signal is recorded on the recording medium 13. When the recording medium 13 is a magneto-optical disk, the optical pickup device 14 is provided with a magnetic head.

  In the audio recording / reproducing apparatus operating as described above, the encoding circuit 3, the oversampling circuit 4, the n-order delta-sigma modulation circuit 5, the PWM modulation circuit 6, the expansion circuit 15, the downsampling circuit 16, and the compression circuit 17 are It is mounted on one system LSI 20. In the present embodiment, the system LSI 20 is configured as described above, but the encoding circuit 3, the oversampling circuit 4, the n-order delta-sigma modulation circuit 5, the PWM modulation circuit 6, the expansion circuit 15, and the downsampling. The circuit 16 and the compression circuit 17 are not mounted on one LSI, but may be mounted on separate LSIs.

(N-order delta-sigma modulation circuit)
Hereinafter, the configuration and operation of the nth-order delta-sigma modulation circuit 5 in such an audio recording / reproducing apparatus will be described with reference to the drawings. FIG. 2 is a diagram showing an internal configuration of the nth-order delta-sigma modulation circuit 5.

  The n-order delta-sigma modulation circuit 5 in FIG. 2 includes an input terminal IN to which the PCM signal S2 from the oversampling circuit 4 is input, an output terminal OUT to output the PCM signals S3 and S4 of the left and right channels, and 24 bits. Registers ds1_reg to dsn_reg, out_reg, ACC, a selector 51 for selecting either a digital signal from the input terminal IN or the register ACC or a digital signal with a sign 0, registers ds1_reg to dsn_reg and quantization Selectors 52a and 53a for selecting a digital signal from the device 58, selectors 52b and 53b for selecting either a digital signal selected by the selectors 52a and 53a or a digital signal having a code 0, and selectors 51 and 52b 53b it Shifters 54 to 56 for shifting the digital signal from the shifter by the set number of bits, an adder 57 for adding and subtracting the digital signal from the shifters 54 to 56, and the lower 18 bits of the 24-bit digital signal from the register out_reg Is a digital signal processing device that includes a quantizer 58 that quantizes 6 bits with 0 and a register reg that stores only the upper 6 bits of the digital signal from the quantizer 58.

In the n-order delta-sigma modulation circuit having such a configuration, when the selection signal asel is input to the selector 51, the 24-bit PCM signal from the input terminal IN, the 24-bit digital signal in the register ACC, and the code 0 Is selected and output to the shifter 54. In the shifter 54, the magnification is set by the input control signal ctl1, and the digit of the digital signal is shifted left and right in accordance with the magnification. That is, when multiplying by 1/2 ^k (0 ≦ k <24), the input digital signal is shifted to the right by k bits, and when multiplying by 2 ^k , the input digital signal is by k bits. Shift left.

  Further, when the selection signal regsel_1 is input to the selector 52a, any one of the registers ds1_reg to dsn_reg and the 24-bit digital signal in the quantizer 58 is selected and output to the selector 52b. In the quantizer 58, the 24-bit digital signal given from the register out_reg is set to 0 except for the upper 6 bits, so that the 24-bit digital signal quantized to 6 bits is stored. In addition, when the selection signal bsel is input to the selector 52b, either the 24-bit digital signal selected by the selector 52a or the 24-bit digital signal having the code 0 is selected and output to the shifter 55. . In the shifter 55, the magnification is set by the input control signal ctl2, and, similarly to the shifter 54, the digit of the digital signal is shifted to the left and right according to the magnification.

  Further, when the selection signal regsel_2 is input to the selector 53a, any one of the registers ds1_reg to dsn_reg and the 24-bit digital signal in the quantizer 58 is selected and output to the selector 53b. In addition, when the selection signal csel is input to the selector 53b, either the 24-bit digital signal selected by the selector 53a or the 24-bit digital signal having the code 0 is selected and output to the shifter 56. . In the shifter 56, the magnification is set by the input control signal ctl3, and, like the shifter 54, the digit of the digital signal is shifted left and right in accordance with the magnification.

  In this manner, the 24-bit digital signal accumulated at each magnification by the shifters 54 to 56 is supplied to the adder 57. In the adder 57, the digital signal from the shifter 55 is non-inverted and the digital signal from the shifter 56 is inverted. The digital signal from the shifter 54 is set to be non-inverted or inverted. When the digital signals of the shifters 54 to 56 are input in this way, the adder 57 adds / subtracts the added / subtracted 24-bit digital signal to the register ACC and stores it in the register ACC. The 24-bit digital signal quantized to 6 bits by setting the bits other than the upper 6 bits to 0 in the quantizer 58 is stored as a 6-bit digital signal in the register reg, and then left and right from the output terminal OUT. It is output to the PWM modulation circuit 6 as a 6-bit PCM signal for each channel.

  At this time, it is controlled whether or not the registers ds1_reg to dsn_reg can be rewritten by the control signals enable_1 to enable_n, respectively. Further, whether or not the registers out_reg and reg can be rewritten is controlled by control signals enable_o and enable_q, respectively.

  In the n-order delta-sigma modulation circuit 5 having such a configuration, for example, as shown in FIG. 3A, the signal input to the input terminal IN is multiplied by the multiplier 101 and then added by the adder 112. It is assumed that the signal from the delay device 121 is added and the signal from the delay device 128 multiplied by the multiplier 111 is subtracted. Further, it is assumed that the register ds1_reg corresponds to the delay device 121 and the register out_reg corresponds to the delay device 128. The operation at this time will be described below. Further, it is assumed that a 24-bit digital signal serving as data dx is stored in the register ds1_reg, and a 24-bit digital signal serving as data dy is stored in the register out_reg.

Since the selection signal asel that becomes “01” is supplied to the selector 51, the PCM signal of the data “da” input to the input terminal IN connected to the “01” input terminal of the selector 51 is selected, and the shifter is selected. Data “da” is input to 54. The shifter 54 shifts the data “da” to the right by k1 bits corresponding to the magnification ½ ^k1 set by the control signal ctl1, and then outputs it to the adder 57.

  Further, since the selection signal regsel_1 which is “d1” is given to the selector 52a, the digital signal of the data “dx” of the register ds1_reg connected to the “d1” input terminal of the selector 52a is selected, and is sent to the selector 52b. Entered. Since the selection signal bsel that is “1” is given to the selector 52b, the output of the selector 52a connected to the “1” input terminal of the selector 52b is given to the shifter 55. That is, the data “dx” selected by the selector 52 a is supplied to the shifter 55. Further, in the shifter 55, since the magnification set by the control signal ctl2 is this magnification, the shifter 55 outputs it to the adder 57 without performing a shift operation.

Further, since the selection signal regsel_2 which is “do” is given to the selector 53a, the digital signal quantized by the quantizer 58 connected to the “do” input terminal of the selector 53a is selected, and the selector 53b is selected. Is input. That is, in the quantizer 58, the lower 18 bits of the data “dy” in the register out_reg are quantized to 6 bits, and a digital signal that becomes data “dyq” is obtained. The digital signal to be the data “dyq” is selected by the selector 53a and is supplied to the selector 53b. Since the selection signal csel that is “1” is given to the selector 53b, the output of the selector 53a connected to the “1” input terminal of the selector 53b is given to the shifter 56. In other words, the data “dyq” selected by the selector 53a is supplied to the shifter 56. Further, the shifter 56 shifts the data “dyq” to the right by k2 bits corresponding to the magnification ½ ^k2 set by the control signal ctl3, and then outputs it to the adder 57.

The adder 57 adds the data provided from the shifter 55 to the data provided from the shifter 54 and subtracts the data provided from the shifter 56. Therefore, the output from the adder 57 becomes “1/2 ^k1 × da + dx−1 / 2 ^k2 × dyq” and is output to the register ACC. Therefore, “1/2 ^k1 × da + dx−1 / 2 ^k2 × dyq” is temporarily stored in the register ACC. Thereafter, since the control signal enable_1 that permits rewriting to the register ds1_reg is given, the data “1/2 ^k × da + dx−1 / 2 ^k2 × dyq” stored in the register ACC is stored in the register ds1_reg.

In this case, each multiplier coefficient of the multiplier 101 and ^{111, 1/2 k1, 1/} 2 when it is ^k2, the result of calculation as described above ^{"1/2 k1 × da + dx-} 1/2 k2 × dyq "Is the output from the adder 112, the data" 1/2 ^k1 * da + dx-1 / 2 ^k2 * dyq "is stored in the register ds1_reg, and the operation is terminated. That is, for example, if the multiplication coefficients of the multipliers 101 and 111 are 0.5 (= 1/2) and 0.25 (= 1/4), respectively, the shifter 54 shifts the data to the right by 1 bit and the shifter 56 By shifting to the right by 2 bits, data of “1/2 × da + dx−1 / 4 × dyq” is input to the register ACC. Then, the data “1/2 × da + dx−1 / 4 × dyq” is stored in the register ds1_reg, and the arithmetic processing in FIG. At this time, the input from the shifter 54 to the adder 57 is a non-inverting input.

When the multiplication coefficients of the multipliers 101 and 111 are Σ (1/2 ^k1 ) and Σ (1/2 ^k2 ), respectively, the selectors 51, 52a, 52b, The processing operations in 53a and 53b, the shifters 54 to 56, and the adder 57 are repeated. Regarding the operation at this time, first, the multiplication coefficient of the multiplier 101 is 0.75 (= 1/2 + 1/4) and the multiplication coefficient of the multiplier 111 is 0.875 (= 1/2 + 1/4 + 1/8). An operation at a certain time will be described as an example.

  First, control signals ctl1 and ctl3 for shifting data to the right by 1 bit are given to the shifters 54 and 56, and the input from the shifter 54 to the adder 57 is a non-inverted input. At this time, a control signal ctl2 for preventing the shift operation is applied to the shifter 55. The value of the selection signal asel is “01”, the values of the selection signals bsel and csel are each “1”, the value of the selection signal reg_sel1 is “d1”, and the value of the selection signal reg_sel2 is “do”. The

  Therefore, the data “da” from the input terminal IN selected by the selector 51 is shifted to the right by 1 bit by the shifter 54. When the data “dyq” in the register out_reg is quantized by the quantizer 58 to obtain data “dyq”, the data “dyq” is selected by the selectors 53a and 53b, and then the shifter 56 1 bit right. Shifted to. At this time, the data “dx” of the register ds1_reg is given to the shift 55 that does not perform the shift operation. Then, the adder 57 adds “dx” from the shifter 55 to “1/2 × da” from the shifter 54 and subtracts “1/2 × dyq” from the shifter 56. Therefore, the data “1/2 × da + dx−1 / 2 × dyq” is stored in the register ACC and then stored in the register ds1_reg.

  Next, control signals ctl1 and ctl3 for shifting data to the right by 2 bits are given to the shifters 54 and 56, respectively. At this time, the selection signals asel to csel, reg_sel1, reg_sel2 are the same. Therefore, the data “da” from the input terminal IN selected by the selector 51 is shifted to the right by 2 bits by the shifter 54, and the data “dyq” quantized by the quantizer 58 selected by the selectors 53a and 53b. "Is shifted right by 2 bits in the shifter 56. Then, the data “1/2 × da + dx−1 / 2 × dyq” of the register ds1_reg is given to the shift 55 that does not perform the shift operation. Then, the adder 57 adds “1/2 × da + dx−1 / 2 × dyq” from the shifter 55 to “¼ × da” from the shifter 54, and also adds “1 / × from the shifter 56. 4 × dyq ″ is subtracted. Therefore, the data “(1/2 + 1/4) × da + dx− (1/2 + 1/4) × dyq” is stored in the register ACC and then stored in the register ds1_reg.

  Finally, the selection signal asel is set to “00” and the control signal ctl3 for shifting the data to the right by 3 bits is given to the shifter 56. At this time, the selection signals bsel, csel, reg_sel1, reg_sel2 are the same. Therefore, the selector 51 selects data in which all 24-bit digits that are input to the “00” input terminal are 0, and supplies the selected data to the adder 57 via the shifter 54. Further, the data “dyq” quantized by the quantizer 58 selected by the selectors 53a and 53b is shifted rightward by 3 bits by the shifter 56. Then, the data “(1/2 + 1/4) × da + dx− (1/2 + 1/4) × dyq” of the register ds1_reg is given to the shift 55 that does not perform the shift operation. Then, the adder 57 subtracts “1/8 × dyq” from the shifter 56 to “(1/2 + 1/4) × da + dx− (1/2 + 1/4) × dyq” from the shifter 55. Therefore, data “(1/2 + 1/4) × da + dx− (1/2 + 1/4 + 1/8) × dyq” is stored in the register ACC and then stored in the register ds1_reg.

  In this way, by performing the addition process three times in the adder 57, the operations by the multipliers 101 and 111 and the adder 112 having the multiplication coefficients of 0.75 and 0875 are performed, and the calculation result is stored in the register ds1_reg. . In other words, the operation for the multiplier 101 and the adder 112 with a multiplication coefficient of 0.75 is performed by two addition processes in the adder 57, and the multiplication coefficient of 0.875 is obtained by three addition processes in the adder 57. Operations for the multiplier 111 and the adder 112 are performed.

  Next, the multiplication coefficient of the multiplier 101 is 0.9375 (= 1/2 + 1/4 + 1/8 + 1/16) and the multiplication coefficient of the multiplier 111 is 0.875 (= 1/2 + 1/4 + 1/8). The operation at that time will be described as an example.

  First, control signals ctl1 to ctl3 for preventing the shift operation are applied to the shifters 54 to 56, and the input from the shifter 54 to the adder 57 is a non-inverting input. The value of the selection signal asel is “01”, the values of the selection signals bsel and csel are each “1”, the value of the selection signal reg_sel1 is “d1”, and the value of the selection signal reg_sel2 is “do”. It is said. Therefore, the data “da” from the input terminal IN, the data “dx” of the register ds1_reg, and the data “dyq” of the quantizer 58 are supplied to the adder 57 from the shifters 54 to 56 that do not perform the shift operation. Then, by performing addition processing in the adder 57, data “da + dx−dyq” is stored in the register ACC and then stored in the register ds1_reg.

  Next, a control signal ctl1 for shifting data to the right by 4 bits is given to the shifter 54, and an input from the shifter 54 to the adder 57 is an inverted input. Further, the selection signal csel is set to “0”. Therefore, the data “da” from the input terminal IN selected by the selector 51 is shifted right by 4 bits by the shifter 54. The selector 53 b selects data in which all 24-bit digits that are input to the “0” input terminal are 0, and supplies the selected data to the adder 57 via the shifter 56. Since the data “da + dx−dyq” of the register ds1_reg is given to the shift 55 that does not perform the shift operation, the addition processing is performed by the adder 57, so that “(1-1 / 16) × da + dx−dyq” is obtained. Is stored in the register ACC and then in the register ds1_reg.

  Finally, a control signal ctl1 for preventing the shift operation is given to the shifter 54, and a control signal ctl2 for shifting the data to the right by 3 bits is given to the shifter 55. Further, the selection signal regsel_1 is set to “do” and the selection signal asel is set to “10”. Further, the input from the shifter 54 to the adder 57 is a non-inverting input. Therefore, the selector 51 selects data “(1-1 / 16) × da + dx−dyq” stored in the register ACC connected to the “10” input terminal, and adds the adder 57 via the shifter 54. Given to. Also, the data “dyq” of the quantizer 58 selected by the selectors 52a and 52b is shifted right by 3 bits by the shifter 55. Then, by adding the data in the adder 57, the data “(1-1 / 16) × da + dx− (1-1 / 8) dyq” is stored in the register ACC and then stored in the register ds1_reg. Is done.

  The data “(1-1 / 16) × da + dx− (1-1 / 8) dyq” obtained by the arithmetic processing as described above is “(1/2 + 1/4 + 1/8 + 1/16) × da + dx”. -(1/2 + 1/4 + 1/8) dyq ". In this way, by performing the addition process three times in the adder 57, the operations of the multipliers 101 and 111 and the adder 112 having multiplication coefficients of 0.9375 and 0875 are performed, and the calculation result is stored in the register ds1_reg. To do. That is, in the first and second addition processing in the adder 57, the multiplication coefficient 0.9375 is operated on the multiplier 101 and the adder 112, and in the first and third addition processing in the adder 57, Operations are performed on the multiplier 111 and the adder 112 having a multiplication coefficient of 0.875. As in this example, by using the subtraction process in the adder 57, the number of calculation processes in the adder 57 can be reduced, and the burden on the calculation process can be reduced.

  Further, in the n-order delta-sigma modulation circuit 5, for example, as shown in FIG. 3B, the signal from the adder 112 is multiplied by the multiplier 102, and then the adder 113 outputs the signal from the delay device 122. It is assumed that the signal is added and the signal from the delay unit 123 multiplied by the multiplier 108 is subtracted. Further, it is assumed that the register ds2_reg corresponds to the delay device 122 and the register ds3_reg corresponds to the delay device 123. The operation at this time will be described below. It is assumed that a 24-bit digital signal serving as data “ds” is stored in the register ds2_reg, and a 24-bit digital signal serving as data “dt” is stored in the register ds3_reg. The multiplication coefficients of the multipliers 102 and 108 are set to 0.875 and 0.75, respectively.

  First, when data “db”, which is an operation result in the previous stage of the adder 112, is stored in the registers ACC and ds1_reg, the selection signals asel, bsel, and csel are “10”, “1”, and “1”, respectively. Is done. The selection signals regsel_1 and regsel_2 are set to “d2” and “d3”, respectively. Further, control signals ctl1 to ctl3 for preventing the shift operation are supplied to the shifters 54 to 56, and the input from the shifter 54 to the adder 57 is a non-inverting input.

  Therefore, the data “db” stored in the register ACC connected to the “10” input terminal of the selector 51 is supplied to the adder 57 via the shifter 54. Further, when the data “ds” stored in the register ds2_reg is selected by the selectors 52a and 52b, it is given to the adder 57 via the shifter 55. Further, when the data “dt” stored in the register ds3_reg is selected by the selectors 53a and 53b, it is given to the adder 57 via the shifter 56. The adder 57 performs addition processing, so that the data “db + ds−dt” is stored in the register ACC and then stored in the register ds2_reg that is permitted to be rewritten by the control signal enable_2.

  Next, the selection signals regsel_1 and regsel_2 are set to “d3” and “d1”, respectively. A control signal ctl2 for shifting data to the right by 1 bit is given to the shifter 55, and a control signal ctl3 for shifting data to the right by 1 bit is given to the shifter. Therefore, the data “db + ds−dt” stored in the register ACC connected to the “10” input terminal of the selector 51 is supplied to the adder 57 via the shifter 54. Further, when the data “dt” stored in the register ds3_reg is selected by the selectors 52a and 52b, the data is shifted right by 2 bits by the shifter 55 and supplied to the adder 57. Further, when the data “db” stored in the register ds1_reg is selected by the selectors 53a and 53b, the data is shifted to the right by 3 bits by the shifter 56 and supplied to the adder 57. Then, by adding the data in the adder 57, the data “(1-1 / 8) db + ds− (1-1 / 4) dt” is stored in the register ACC and then in the register ds2_reg. The

  In this way, by performing the addition process twice in the adder 57, the operations of the multipliers 102 and 108 and the adder 113 having the multiplication coefficients of 0.875 and 075 are performed, and the calculation result is stored in the register ds2_reg. .

  Further, in the n-order delta-sigma modulation circuit 5, for example, as shown in FIG. 3C, the signals from the adders 112 to 114 are added by the adder 119 and converted to 6 bits by the quantizer 120. It shall be quantized. Also, it is assumed that the registers ds1_reg to ds3_reg store the calculation results of the adders 112 to 114, respectively. The operation at this time will be described below. It is assumed that 24-bit digital signals serving as data “dj”, “dk”, and “dl” are stored in the registers ds1_reg, ds2_reg, and ds3_reg, respectively.

  First, when the data “dl” that is the operation result in the adder 119 is stored in the registers ACC and ds3_reg, the selection signals asel, bsel, and csel are set to “10”, “1”, and “0”, respectively. . The selection signal regsel_1 is set to “d1”. Further, control signals ctl1 to ctl3 for preventing the shift operation are supplied to the shifters 54 to 56, and the input from the shifter 54 to the adder 57 is a non-inverting input.

  Therefore, the data “dl” stored in the register ACC connected to the “10” input terminal of the selector 51 is supplied to the adder 57 via the shifter 54. Further, when the data “dj” stored in the register ds1_reg is selected by the selectors 52a and 52b, it is given to the adder 57 via the shifter 55. Further, the selector 53 b selects data in which all 24-bit digits that are input to the “0” input terminal are 0, and supplies the selected data to the adder 57 via the shifter 56. Then, by performing addition processing in the adder 57, data “dj + dl” is stored in the register ACC and then stored in the register out_reg that is rewritten by the control signal enable_o.

  Next, the selection signal regsel_1 is set to “d2”. Therefore, the data “dj + dl” stored in the register ACC connected to the “10” input terminal of the selector 51 is supplied to the adder 57 via the shifter 54. Further, when the data “dk” stored in the register ds2_reg is selected by the selectors 52a and 52b, it is given to the adder 57 through the shifter 55. Then, addition processing is performed by the adder 57, whereby data “dj + dk + dl” is stored in the register ACC and then stored in the register out_reg. The data “dj + dk + dl” stored in the register out_reg is quantized into a 6-bit digital signal by the quantizer 58 by setting the lower 16 bits of data to 0. The high-order 6-bit data of the digital signal quantized by the quantizer 58 is stored in the register reg that is permitted to be rewritten by the control signal enable_q, and then the 6-bit digital signal is stored from the output terminal OUT.

  In this manner, by performing the addition process twice in the adder 57, the operation by the adder 119 that adds the calculation results of the adders 112 to 114 is performed, and the calculation result is stored in the register out_reg. The operation of the quantizer 120 that quantizes the calculation result to 6 bits is performed by the quantizer 58 and the register reg, and then output from the output terminal OUT.

  In the n-order delta-sigma modulation circuit 5 operating as described above, the registers ds1_reg to dsα_reg are used as a part of the digital filter function unit 5a, and the registers dsα + 1_reg to dsn_reg are n-αth order delta-sigma modulation function units. Used as part of 5b. Hereinafter, in order to simplify the description, the operation will be described with n = 4 and α = 1. The configuration of the n (4) -order delta-sigma modulation circuit 5 at this time is shown in FIG. That is, in FIG. 4, the registers ds1_reg to ds4_reg are configured, the register ds1_reg operates as a part of the digital filter function unit 5a, and the registers ds2_reg to ds4_reg are one of the delta-sigma modulation function unit 5b. Operates as a part.

  When the n-th order delta-sigma modulation circuit 5 is configured as shown in FIG. 4, the digital filter function unit 5a is further formed of a two-element filter as shown in FIG. 5, and the delta-sigma modulation function unit 5b. Is constituted by a third-order delta-sigma modulation circuit as shown in FIG. That is, the digital filter function unit 5a includes a delay unit 61 to which the PCM signal S2 from the oversampling circuit 4 is input, a multiplier 62 that multiplies the PCM signal S2 by the coefficient ma, and a signal from the delay unit 61 to the coefficient mb. This is equivalent to a two-element filter constituted by a multiplier 63 that multiplies and an adder 64 that adds signals from the multipliers 62 and 63. Further, the delta-sigma modulation function unit 5b is a third order composed of multipliers 101 to 103, 108 and 111, adders 112 to 114 and 119, delay units 121 to 123 and 128, and a quantizer 120. This is equivalent to a delta-sigma modulation circuit.

  In such a configuration, first, when the PCM signal from the oversampling circuit 4 is input from the input terminal IN, the digital signal stored in the register ds1_reg is read out. At this time, the selectors 51, 52a, 52b, 53a, 53b, the shifters 54 to 56, and the adder 57 operate as described above, thereby converting the digital signal from the input terminal IN and the digital signal in the register ds1_reg. Arithmetic processing is performed. Thus, the digital signal input to the input terminal IN is multiplied by the multiplication coefficient of the multiplier 62, and the digital signal read from the register ds1_reg corresponding to the delay unit 61 is multiplied by the multiplier 63. The coefficients are multiplied and added. Thereafter, when the digital signal obtained by the adder 64 is output from the adder 57, it is stored in the register ACC and then in the register ds1_reg. That is, the register ds1_reg stores a digital signal obtained by passing the PCM signal from the oversampling circuit 4 through the two-element filter.

  When the digital signal processed by the digital filter function unit 5a is stored in the registers ACC and ds1_reg in this way, first, the digital signal stored in the register ACC is selected by the selector 51 and supplied to the shifter 54. Then, digital signals stored in the registers ds2_reg and out_reg are read out. At this time, the selectors 51, 52a, 52b, 53a, and 53b, the shifters 54 to 56, and the adder 57 operate as described above, thereby calculating the digital signals in the registers ACC, ds1_reg, ds2_reg, and out_reg. Apply processing.

  In this way, the digital signal processed by the digital filter function unit 5a and stored in the registers ACC and ds1_reg is multiplied by the multiplication coefficient of the multiplier 101 and read out from the register ds2_reg corresponding to the delay device 121. Added digital signals. Further, after the digital signal stored in the register out_reg corresponding to the delay unit 128 is quantized by the quantizer 58, the multiplication coefficient of the multiplier 111 is multiplied, and the digital signal of the delay unit 121 is added. Subtracted from the digital signal from the device 101. Thereafter, when the digital signal obtained by the adder 112 is output from the adder 57, it is stored in the register ACC and then in the register ds2_reg. As described above, when the storing operation in the register ds2_reg is completed, the PCM signal from the oversampling circuit 4 input to the input terminal IN is selected by the selector 51, and is stored in the register ds1_reg via the shifter 54 and the register ACC. Stored.

  Next, digital signals stored in the registers ds3_reg and ds4_reg are read. At this time, the selectors 51, 52a, 52b, 53a, 53b, the shifters 54 to 56, and the adder 57 operate as described above, so that arithmetic processing is performed on the digital signals in the registers ACC, ds2_reg to ds4_reg. Apply. In this way, the digital signal from the adder 112 stored in the register ACC, ds2_reg is multiplied by the multiplication coefficient of the multiplier 102, and the digital signal read from the register ds3_reg corresponding to the delay unit 122 is obtained. Is added. Further, the digital signal stored in the register ds4_reg corresponding to the delay unit 123 is multiplied by the multiplication coefficient of the multiplier 108 and subtracted from the digital signal from the multiplier 102 to which the digital signal of the delay unit 122 is added. Thereafter, when the digital signal obtained by the adder 113 is output from the adder 57, it is stored in the register ACC and then in the register ds3_reg.

  Then, the digital signal stored in the register ds4_reg is read out. At this time, the selectors 51, 52a, 52b, 53a, 53b, the shifters 54 to 56, and the adder 57 operate as described above, thereby performing arithmetic processing on the digital signals in the registers ACC, ds3_reg, ds4_reg. Apply. In this way, the digital signal from the adder 113 stored in the register ACC, ds3_reg is multiplied by the multiplication coefficient of the multiplier 103, and the digital signal read from the register ds4_reg corresponding to the delay unit 123 is obtained. Is added. Thereafter, when the digital signal obtained by the adder 114 is output from the adder 57, it is stored in the register ACC and then in the register ds4_reg.

  Finally, digital signals stored in the registers ds2_reg and ds3_reg are read out. At this time, the selectors 51, 52a, 52b, 53a, 53b, the shifters 54 to 56, and the adder 57 operate as described above, so that the digital signals in the registers ACC, ds2_reg, ds3_reg are added by the adder 57. Is done. In this way, the digital signals from the adders 112 to 114 stored in the registers ds2_reg, ds3_reg, and ACC are added. Thereafter, when the digital signal obtained by the adder 119 is output from the adder 57, it is stored in the register ACC and then in the register out_reg. Then, the signal is quantized into a 6-bit digital signal by the quantizer 58 and output to the PWM modulation circuit 6 from the output terminal OUT via the register reg.

  The operations in the digital filter function unit 5a and the delta-sigma modulation function unit 5b are performed for each of the left channel and the right channel with respect to the PCM signal provided from the oversampling circuit 4, so that the registers ds1_reg to dsn_reg, out_reg, reg and quantizer 58 and output terminal OUT are provided for the left channel and the right channel, respectively. At this time, the selectors 51, 52a, 52b, 53a, 53b, the shifters 54 to 56, the adder 57, and the register ACC may be configured for the left channel and the right channel, respectively. May be configured in common.

  The digital filter function unit 5a has been described by taking a two-element filter as shown in FIG. 5 as an example, but by increasing the number of registers dsk_reg used as a delay element of the digital filter function unit 5a, a four-element filter or Digital filters having other configurations such as an 8-element filter and an FIR filter can be configured. Furthermore, the multiplication coefficient in the digital filter function unit 5a is set based on the frequency of the signal compressed by the detected compression circuit 17, so that the filter coefficient can be changed. The filter of the digital filter function unit 5a may be freely set from the outside. Also, the delta-sigma modulation function unit 5b has been described by taking a third order example as shown in FIG. 6 as an example, but by increasing the number of registers dsk_reg used as delay elements of the delta-sigma modulation function unit 5b. The order can be increased.

  Further, the n-order delta-sigma modulation circuit 5 is configured as shown in FIG. 2, but as shown in FIG. 7, it is assumed that a selector 52c capable of selecting a signal from the register ACC is provided instead of the selector 52b. It doesn't matter. With this configuration, when the signal input to the input terminal IN is multiplied, the selection signal bsel is set to “10”, and the signal from the register ACC is selected by the selector 52b and supplied to the shifter 55. Thus, the number of arithmetic processings in the adder 57 when multiplying the signal given from the oversampling circuit 4 can be reduced.

  Since the n-th order delta-sigma modulation circuit 5 is configured as shown in FIG. 2 or FIG. 7 as described above, it is not necessary to provide a multiplier, so that the circuit scale can be reduced. In addition, since the order of delta-sigma modulation and the order of the digital filter can be easily increased, the noise characteristics can be made very good. Furthermore, the sampling frequency of the input signal can be kept very low.

  Further, the frequency of the main clock is calculated from all the processing times in the n-th order delta-sigma modulation circuit 5, and is necessary for a ROM (not shown) provided in the n-th order delta-sigma modulation circuit 5 in FIG. An address counter may be created. That is, if 24 steps are required for each of the left channel and the right channel in the 8 fs period, a clock of 8 fs × (24 steps × 2 ch) = 384 fs (16.8688 MHz) is required. This clock or a signal whose phase is shifted from this clock becomes the clock of each register.

  At this time, the n-order delta-sigma modulation circuit 5 shown in FIG. 2 or FIG. 7 is provided with a 24-bit counter (not shown), and the counter value of the 24-bit counter becomes the above-mentioned ROM address. Signals enable_1 to enable_n, enable_o, enable_q, selection signals asel, bsel, csel, regsel_1, regsel_2 of the selectors 51, 52a, 52b, 53a, 53b, and control signals ctl1 to ctl3 for controlling the shift amounts of the shifters 54 to 56, And the contents of those signals output at every clock are changed.

<Second Embodiment>
A second embodiment of the present invention will be described below with reference to the drawings. FIG. 8 is a block diagram showing the internal configuration of the audio signal recording / reproducing apparatus of this embodiment. In the audio signal recording / reproducing apparatus of FIG. 8, parts used for the same purpose as those of the audio signal recording / reproducing apparatus of FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted. Further, the configuration of the signal processing circuit of the present embodiment is as shown in FIG. 2 or FIG. 7 as in the first embodiment.

  The audio signal recording / reproducing apparatus in FIG. 8 has an n-order delta-sigma modulation circuit 5x provided with an oversampling function unit 5c instead of the oversampling circuit 4, and has a configuration in which the downsampling circuit 16 is removed. That is, a 24-bit digital signal S1 with the sampling frequency fs from the encoding circuit 3 is supplied to the n-th order delta-sigma modulation circuit 5x. In the n-th order delta-sigma modulation circuit 5x, first, after passing through the digital filter function unit 5a, the oversampling function unit 5c converts it into a 24-bit PCM signal S2 with a sampling frequency of 8fs, and finally, the delta-sigma The modulation function unit 5b performs delta-sigma modulation and outputs 6-bit PCM signals S3 and S4 for the left and right channels, respectively.

  Further, a 24-bit digital signal S1c having a sampling frequency fs that has passed through the digital filter function unit 5a of the n-th order delta-sigma modulation circuit 5x is supplied to the compression circuit 17 and is compressed according to a compression method such as the ATRAC method. The data is recorded on the recording medium 13 by the optical pickup device 14. Further, after the digital signal read from the recording medium 13 by the optical pickup device 14 is decompressed by the decompression circuit 15 in accordance with a compression method such as the ATRAC method, the oversampling function unit 5c of the n-th order delta-sigma modulation circuit 5x. Given to. Then, after being converted into a 24-bit PCM signal S2 by the sampling frequency 8fs by the oversampling function unit 5c, the delta-sigma modulation function unit 5b performs delta-sigma modulation.

  In this audio recording / reproducing apparatus, the encoding circuit 3, the n-th order delta-sigma modulation circuit 5x, the PWM modulation circuit 6, the expansion circuit 15, and the compression circuit 17 are mounted on one system LSI 20a.

  In the audio signal recording / reproducing apparatus configured as described above, the n-th order delta-sigma modulation circuit 5x is configured as shown in FIG. 2 or FIG. 7 as in the first embodiment. The registers ds1_reg to dsα_reg are used as the digital filter function unit 5a, the registers dsα + 1_reg to dsβ_reg are used as the oversampling function unit 5c, the registers dsβ + 1_reg to dsn_reg, out_reg, reg, and the quantizer 58 are used as the delta-sigma modulation function unit 5b. use. The selectors 51, 52a to 52c, 53a, 53b, the shifters 54 to 56, the adder 57, and the register ACC are respectively connected to the digital filter function unit 5a, the delta-sigma modulation function unit 5b, and the oversampling function unit 5c. These are used in the same manner as in the first embodiment, and serve as multipliers or adders configured in the digital filter function unit 5a, the delta-sigma modulation function unit 5b, and the oversampling function unit 5c.

  The operation of the n-th order delta-sigma modulation circuit 5x will be described below. As in the first embodiment, the selectors 51, 52a to 52c, and the selectors 51, 52a to 52c, according to the multiplication coefficient of the multiplier configured in the digital filter function unit 5a, the delta-sigma modulation function unit 5b, and the oversampling function unit 5c 53a and 53b, the shifters 54 to 56, the adder 57, and the register ACC operate. Therefore, detailed description thereof will be omitted with reference to the first embodiment. In the following, for the sake of simplicity, the digital filter function unit 5a is a two-element filter configured as shown in FIG. 5, and the delta-sigma modulation function unit 5b is a third-order delta-sigma configured as shown in FIG. It is assumed that the oversampling function unit 5c performs linear interpolation processing while operating as a modulation circuit.

  Thus, the n (5) -order delta-sigma modulation circuit 5x having the two-element filter function, the oversampling function, and the third-order delta-sigma modulation function is configured as shown in FIG. That is, the n (5) th order delta-sigma modulation circuit 5x includes registers ds1_reg to ds5_reg, the register ds1_reg operates as a part of the digital filter function unit 5a, and the register ds2_reg is a part of the oversampling function unit 5c. Also, the registers ds3_reg to ds5_reg operate as part of the delta-sigma modulation function unit 5b.

  In such a configuration, first, when a digital signal serving as data “Da1” of the sampling frequency fs from the encoding circuit 3 is input to the input terminal IN, the cycle Ts (= 1/1 /) stored in the register ds1_reg. A digital signal serving as data “Da2” from the encoding circuit 3 that has been input by fs) is read out. At this time, the selectors 51, 52a, 52b, 53a, 53b, the shifters 54 to 56, and the adder 57 operate as described above, thereby converting the digital signal from the input terminal IN and the digital signal in the register ds1_reg. On the other hand, arithmetic processing is performed in the digital filter function unit 5a. Then, the data “Db1” as the calculation result in the digital filter function unit 5a that functions as the two-element filter is stored in the registers ACC and ds1_reg.

  In this way, when the digital signal that becomes the data “Db1” processed by the digital filter function unit 5a is stored in the registers ACC and ds1_reg, the data “Db2” stored in the register ds2_reg only by the period Ts / 8. The digital signal “Db 2” that is “is read by the selectors 53 a and 53 b and supplied to the adder 57 via the shifter 56. The data “Db2” stored in the register ds2_reg has a value equal to the digital signal obtained by the digital filter function unit 5a before the period Ts. At this time, the data “Db1” stored in one of the registers ACC and ds1_reg is given to the adder 57, and the adder 57 subtracts the data “Db1” from the data “Db1”. Db2 ″ is obtained. This data “Db1-Db2” is stored in the register ACC and then in the register ds1_reg.

  Then, in the shifter 54, the data “Db1-Db2” stored in the register ACC selected by the selector 51 is shifted to the right by 3 bits, so that the multiplication coefficient 1/8 is multiplied and given to the adder 57. The data “Db2” from the register ds2_reg selected by the selectors 52a and 52b is supplied to the adder 57 via the shift 55. Therefore, addition operation processing is performed by the adder 57 and data “Db2 + (1/8) × (Db1−Db2)” is stored in the register ACC and then stored in the register ds2_reg.

  Thereafter, when data “Db2 + (1/8) (Db1−Db2)” is read from the register ACC by the selector 51, the same operation as in the first embodiment is performed, and the third-order delta-sigma modulation is performed. Is given. Therefore, the 6-bit PCM signal subjected to the arithmetic processing in the delta-sigma modulation function unit 5b is temporarily stored in the register reg and then output from the output terminal OUT. That is, the above-described operation is performed on each of the left channel and the right channel, whereby 6-bit PCM signals S3 and S4 are output from the output terminal OUT.

  As described above, when the oversampling process and the delta-sigma modulation in the period Ts / 8 are performed, the data “Db1−Db2” in the register ds1_reg and the data “Db2 + (1/8) × (Db1−) in the register ds2_reg. Db2) "is read out and added by the adder 57. When the data “Db2 + (2/8) × (Db1−Db2)” obtained by the addition processing by the adder 57 is stored in the registers ACC and ds2_reg, the calculation in the delta-sigma modulation function unit 5b is performed. Processing is performed. In this way, when the arithmetic processing in the oversampling function unit 5c and the delta-sigma modulation function unit 5b is performed eight times during the period Ts, the data “Db1” is stored in the register ds2_reg. That is, the register “ds2_reg” stores data “Db1” obtained by performing arithmetic processing in the digital filter function unit 5a on the data “Da1” input from the encoding circuit 3 to the input terminal IN. At this time, the data “Da1” input from the encoding circuit 3 to the input terminal IN is stored in the register ds1_reg.

  By operating in this way, the digital filter function unit 5a operates every cycle Ts, and the oversampling function unit 5c and the delta-sigma modulation function unit 5b each operate every cycle Ts / 8. At this time, since the operation of the digital filter function unit 5a is performed in the first period Ts / 8 in the period Ts, the number of processes is larger than the operation process in the second to eighth periods Ts / 8 in the period Ts. . Therefore, the number of operation processes in the first to eighth cycles Ts / 8 in the cycle Ts may be the same, and the operation may be stopped for the remaining number of processes in the second to eighth cycles Ts / 8. .

  Further, when the number of operation processes in the first to eighth cycles Ts / 8 in the cycle Ts is the same, the remaining number of processing in the second to eighth cycles Ts / 8 is used for the processing for the digital filter function unit 5a. You may make it allocate. At this time, a FIFO (First In First Out) circuit or the like is provided at the subsequent stage of the n-order delta-sigma modulation circuit 5x so that the PCM signals S3 and S4 are input to the PWM modulation 6 in order every 1/8 period. In addition, the timing may be adjusted. In this way, more complicated processing can be performed in the digital filter function unit 5a.

  In the present embodiment, the digital filter function unit 5a is a two-element filter and the delta-sigma modulation function unit 5b is a third-order delta-sigma modulation circuit for the sake of simplicity. However, the present invention is not limited to this. For example, the digital filter function unit 5a may be configured as a four-element filter, an eight-element filter, an FIR filter, or the like, or the order of the delta-sigma modulation function unit 5b may be increased. In addition, although the linear interpolation process is performed in the oversampling function unit 5c, a nonlinear interpolation process may be performed.

  In the audio signal recording / reproducing apparatus of the first and second embodiments described above, the sound input to the microphone 1 is stored in the recording medium 13 by the optical pickup device 14 without being reproduced by the speakers 11 and 12. The n-order delta-sigma modulation circuits 5 and 5x are also operated as the digital filter function unit with respect to the delta-sigma modulation function unit 5b and the oversampling function unit 5c, respectively, and the digital filter circuit 5y as shown in FIGS. , 5z. By doing so, a steeper and more accurate filter configuration can be realized. The functional operation of the delta-sigma modulation function unit 5b and the oversampling function unit 5c is performed by changing the values and input timings of the selection signals asel to csel, regsel_1, regsel_2 and the control signals enable_1 to enable, enable_acc, enable_q, ctl1 to stl3. Can be switched. Similarly, in the audio signal recording / reproducing apparatus of the first and second embodiments, when the audio signal from the recording medium 13 is reproduced by the speakers 11 and 12, the digital filter function unit 5a is also changed to the delta-sigma modulation function unit 5b. You may make it operate as a part of.

  Audio signals obtained by inputting audio from outside are recorded on a recording medium such as MD, MO, CD, CD-R, CD-RW, DVD, DVD-RW, HDD, flash memory and the like. The present invention can be applied to an audio signal recording / reproducing apparatus that reproduces a reproduced audio signal.

These are block diagrams which show the internal structure of the audio | voice signal recording / reproducing apparatus of 1st Embodiment. FIG. 2 is a block diagram showing a configuration of an n-order delta-sigma modulation circuit of the audio signal recording / reproducing apparatus of FIG. 1. These are equalization circuit diagrams corresponding to a part of operation | movement of the n-th order delta-sigma modulation circuit of FIG. FIG. 3 is a block diagram showing a configuration of a fourth-order delta-sigma modulation circuit. These are circuit diagrams which show the structure of the digital filter function part in the delta-sigma modulation circuit of FIG. These are circuit diagrams which show the structure of the delta-sigma function part in the delta-sigma modulation circuit of FIG. FIG. 5 is a block diagram showing another configuration of the n-order delta-sigma modulation circuit of the audio signal recording / reproducing apparatus of FIG. 1. These are block diagrams which show the internal structure of the audio | voice signal recording / reproducing apparatus of 2nd Embodiment. FIG. 3 is a block diagram showing a configuration of a fifth-order delta-sigma modulation circuit. These are block diagrams which show a structure when only the recording block of the audio | voice signal recording / reproducing apparatus of FIG. 1 is used. These are block diagrams which show a structure when only the recording block of the audio | voice signal recording / reproducing apparatus of FIG. 8 is used. These are block diagrams which show the internal structure of the conventional audio | voice signal reproduction | regeneration apparatus. FIG. 13 is a block diagram showing a configuration of a seventh-order delta-sigma modulation circuit of the audio signal reproduction device of FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Microphone 2 A / D converter 3 Coding circuit 4 Oversampling circuit 5 nth-order delta-sigma modulation circuit 6 PWM modulation circuit 7,8 Switching amplifier 9,10 LPF
DESCRIPTION OF SYMBOLS 11, 12 Speaker 13 Recording medium 14 Optical pick-up apparatus 15 Expansion circuit 16 Downsampling circuit 17 Compression circuit

Claims (11)

A plurality of multipliers for multiplying a set multiplication coefficient;
An adder for adding and subtracting signals from a plurality of multipliers;
A storage unit for storing a signal as a calculation result of the adder and an input signal in each of a plurality of storage areas;
A quantizer that quantizes a signal that is a final calculation result stored in the storage unit;
With
When a part of the storage area of the storage unit is a first storage area and the storage area other than the first storage area of the storage unit is a second storage area,
After operating as a digital filter function unit that removes a noise component from an input signal by repeatedly operating the plurality of multipliers and the adder using each storage area of the first storage area,
The plurality of multipliers and the adder are operated repeatedly using each storage area of the second storage area, and then quantized by the quantizer, so that a signal that has passed through the digital filter function unit is deltaed. A digital signal processing circuit that operates as a delta-sigma modulation function unit that performs sigma modulation. A plurality of multipliers for multiplying a set multiplication coefficient;
An adder for adding and subtracting signals from a plurality of multipliers;
A storage unit for storing a signal as a calculation result of the adder and an input signal in each of a plurality of storage areas;
A quantizer that quantizes a signal that is a final calculation result stored in the storage unit;
With
A part of the storage area of the storage unit is a first storage area, a part of the storage area other than the first storage area of the storage part is a second storage area, a first storage area of the storage unit, and When a part of the storage area other than the second storage area is a third storage area,
By operating the plurality of multipliers and the adder repeatedly using each storage area of the first storage area, and operating as a digital filter function unit that removes noise components from the input signal,
Operates as an oversampling function unit that increases the sampling frequency of the signal that has passed through the digital filter function unit by repeatedly operating the plurality of multipliers and the adder using each storage area of the third storage area After
The signal oversampled by the oversampling function unit by quantizing the quantizer after repeatedly operating the plurality of multipliers and the adder using each storage area of the second storage area A digital signal processing circuit which operates as a delta-sigma modulation function unit for performing delta-sigma modulation on the signal. In the oversampling function unit, when oversampling to n times the sampling frequency,
3. The digital signal processing circuit according to claim 2, wherein the oversampling function unit and the delta-sigma modulation function unit operate for n cycles while the digital filter function unit operates for one cycle. A calculation result storage unit for temporarily storing a signal that is a calculation result of the adder;
A first selection unit that selects one signal from three signals: an input signal, a signal from the calculation result storage unit, and a signal having a value of 0;
A second selection unit that selects one signal from a plurality of signals stored in the plurality of storage areas of the storage unit and a signal having a value of 0;
A third selection unit that selects one signal from a plurality of signals stored in the plurality of storage areas of the storage unit and a signal having a value of 0;
With
As the multiplier, a first multiplier to which a signal selected by the first selection unit is given, and a second multiplier to which a signal selected by the second selection unit is given and which is non-inverted and outputted to the adder The digital signal according to any one of claims 1 to 3, further comprising: a third multiplier that receives the signal selected by the third selection unit and outputs the inverted signal to the adder. Signal processing circuit. The multiplier is a shifter for shifting a binary digit of an input signal;
5. The digital signal processing according to claim 1, wherein a multiplication coefficient is set by the number of digits shifted by the multiplier and the number of repetitions by the multiplier and the adder. circuit. An oversampling circuit that increases the sampling frequency of the input digital signal;
The digital signal processing circuit according to claim 1, wherein the digital signal oversampled by the oversampling circuit is input;
A PWM modulation circuit that performs pulse width modulation on the digital signal calculated by the digital signal processing circuit;
An audio signal recording / reproducing apparatus comprising: A downsampling circuit that lowers the sampling frequency of the digital signal processed by the digital filter function unit of the digital signal processing circuit;
A recording unit for recording a digital signal output from the downsampling circuit on a recording medium;
The audio signal recording / reproducing apparatus according to claim 6, comprising: A digital signal processing circuit according to any one of claims 2 to 5,
A PWM modulation circuit that performs pulse width modulation on the digital signal calculated by the digital signal processing circuit;
An audio signal recording / reproducing apparatus comprising:   9. The audio signal recording / reproducing apparatus according to claim 8, further comprising a recording unit that records the digital signal processed by the digital filter function unit of the digital signal processing circuit on a recording medium. A signal reading unit for reading a digital signal from a recording medium is provided.
10. The audio signal recording / reproducing apparatus according to claim 8, wherein the digital signal read from the signal reading unit is supplied to the oversampling function unit of the digital signal processing circuit.   11. When recording a digital signal on a recording medium by the recording unit, the entire storage area in the storage unit of the digital signal processing circuit is used as the digital filter function unit. An audio signal recording / reproducing apparatus according to claim 1.

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