JP2005149170A - Data sending and receiving system and program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the time required to send and receive data. <P>SOLUTION: A test system 2 for a semiconductor integrated circuit comprises a host computer 10 and a plurality of testing devices 11. The testing device 11 is provided with a USB host connector 23 for sending data to the outside, a USB host controller 25 for controlling the transmission of the data, a USB device connector 24 for receiving data from the outside, and a USB device controller 26 for controlling the reception of data. The testing device #1 sends the data received from the host computer 10 to the testing device #2, and sends the data received from the testing device #2 to the host computer 10. Each of the testing devices 11 behind the testing device #2 sends the data from the host computer 10 received from the upper testing device 11 to the lower testing device 11, and sends the data received from the lower testing device 11 to the upper testing device 11. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a data transmission / reception system and a data transmission / reception program for transmitting / receiving data between a host computer and a plurality of logical devices.

  When verifying the operation of a semiconductor integrated circuit such as a semiconductor memory or a logic integrated circuit, a programmable device such as an FPGA (Field Programmable Gate Array) capable of rewriting any logic by a user is mounted on a circuit board. A technique for configuring a test circuit capable of executing desired test contents described in HDL (Hardware Description language) or C language in a device has been proposed (see Patent Documents 1 and 2).

  FIG. 7 shows a schematic configuration of a semiconductor integrated circuit test apparatus described in Patent Documents 1 and 2. The test apparatus 100 includes a test board in which an AD converter (ADC) 102, a DA converter (DAC) 103, and an associated amplifier (AMP) 104 are mounted on a circuit board, with an FPGA 101 as a center. . The test apparatus 100 can input and output voltage and current via input / output terminals 105 and 106 connected to the AMP 104. The FPGA 101 is connected to the digital terminals of the ADC 102 and the DAC 103. Further, it is selectively connected to a semiconductor integrated circuit (not shown) to be verified through a switching device such as a relay.

  In the techniques described in Patent Documents 1 and 2, a test pattern according to product specifications is generated, a test program debugged with the test pattern is converted into HDL, and simulation is performed as necessary. A desired test circuit is configured in the FPGA 101 by logically synthesizing the HDL-converted test program. According to this technique, the manufacturing cost and the number of man-hours can be greatly reduced as compared with the conventional method of verifying a product using a tester in which a fixed test circuit is formed.

International Publication No. 98/57281 Pamphlet JP 2002-123562 A

  When configuring a test circuit in the FPGA 101, a large amount of test pattern data (which may be several megabytes) is sent from a host computer on the data transmission side to a test apparatus (hereinafter also referred to as a test board) on the data reception side. And test program data (having several hundred kilobytes) as test condition data must be transmitted to the test board in advance. More specifically, although not clearly shown in FIG. 7, a nonvolatile memory such as a flash memory is mounted on a test board, and logic synthesis is performed from HDL or C language description stored in the host computer. A method is adopted in which a test circuit is transmitted to a test board, stored in a memory mounted on the test board, and then written directly into the FPGA 101 from this memory.

  In an actual semiconductor integrated circuit test, a plurality of test apparatuses are prepared for the purpose of reducing the test time, and a plurality of (for example, 16) test objects (semiconductor wafer chips) are tested at a time by one operation. I am doing so. Therefore, when a test pattern and a test program (typically the same data) are transmitted from a host computer to a memory mounted on each of a plurality of test apparatuses, a communication method capable of parallel transfer, for example, Ethernet (registered trademark) ) Method is generally used. However, in this Ethernet (registered trademark) system, it is necessary to set a special IP address for the communication target, and for the sake of convenience of testing or to solve the problems of some test devices, a plurality of In a test of a semiconductor integrated circuit in which the order of test devices is frequently changed or replaced with another test device, handling is very complicated and it is difficult to use.

  On the other hand, when the USB (Universal Serial Bus) method is used, a special IP address as in the Ethernet (registered trademark) method is not required. The part can be replaced with another test apparatus, and handling becomes extremely easy.

  However, when the USB method is used, parallel transfer cannot be performed, and a plurality of test devices connected via a hub are individually specified, and test data (test pattern and test program) are sequentially transmitted to these test devices. It is necessary to do. Therefore, when the USB method is used as it is, this test data transmission requires a load time obtained by multiplying the load time required for one test device by the number of test devices. In general, the time for loading test data from the host computer to each test apparatus (test board) often takes approximately several to several tens of minutes per unit.

  Furthermore, since loading test data from the host computer to the test equipment must be performed each time the test target is switched, the load time described above becomes a particularly serious problem in small-lot, high-mix production where the test target is frequently switched. This contributed to increase the non-operation time of the test equipment. In addition to sending test data to the test equipment, the host computer generally sends / receives production management data to / from the production management equipment that controls the entire semiconductor manufacturing process, and communicates with the prober and handler that operates the test equipment. Since the communication processing is performed at the same time, if the load time of the test data becomes long as described above, the operation efficiency of the entire semiconductor manufacturing process may be lowered.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a data transmission / reception system and a data transmission / reception program capable of shortening the time required for data transmission / reception.

  In order to achieve the above object, the present invention provides a system for transmitting and receiving data between a host computer and a plurality of logical devices, and a USB host connector for transmitting the data to the logical devices to the outside. And a USB host controller for controlling the transmission of the data, a USB device connector for receiving the data from the outside, and a USB device controller for controlling the reception of the data. The host computer and the plurality of logical devices are connected in a daisy chain via the USB host connector and the USB device connector, and the first logical device connected immediately below the host computer is the host computer. Received from To the second logical device, and the data received from the second logical device is transmitted to the host computer, and each logical device after the second logical device The data from the host computer received from the lower logical device is transmitted to the lower logical device, and the data received from the lower logical device is transmitted to the upper logical device. .

  The logical device preferably only relays transmission / reception of the data when the data is not captured. The logic device is preferably a test apparatus that creates a test circuit from a test program for a semiconductor integrated circuit and verifies the operation of the semiconductor integrated circuit.

  A data transmission / reception program according to the present invention includes a host computer and a plurality of logical devices. The logical device includes a USB host connector for transmitting data to the outside, a USB host controller for controlling transmission of the data, And a USB device connector for receiving the data from the outside and a USB device controller for controlling the reception of the data, and the host computer and the plurality of logical devices include the USB host connector and the USB Used in a data transmission / reception system connected in a daisy chain via a device connector, data received from the host computer is transferred to a first logical device connected immediately below the host computer. And a function for transmitting the data received from the second logical device to the host computer, and receiving each of the logical devices after the second logical device from the upper logical device. The function of transmitting the data from the host computer to the lower logical device and transmitting the data received from the lower logical device to the upper logical device is realized.

  When the data is not taken into the logical device, it is preferable that the logical device realizes a function of only relaying the transmission / reception of the data. The logic device is preferably a test apparatus that creates a test circuit from a test program for a semiconductor integrated circuit and verifies the operation of the semiconductor integrated circuit.

  According to the data transmission / reception system and the data transmission / reception program of the present invention, a USB host connector for transmitting data to the logical device, a USB host controller for controlling transmission of data, and a data host for receiving data from the outside A USB device connector and a USB device controller that controls data reception are provided, and the host computer and a plurality of logical devices are connected in a daisy chain via the USB host connector and the USB device connector with the host computer as the highest level. The first logical device connected directly under the host computer transmits the data received from the host computer to the second logical device, and also receives the data received from the second logical device. Each of the logical devices after the second logical device transmits the data from the host computer received from the upper logical device to the lower logical device and receives from the lower logical device. Since the processed data is transmitted to the upper logical device, it is possible to reduce the time required for transmitting test data including a large number of test patterns and test programs transmitted from the host computer to each test apparatus.

  In FIG. 1, a semiconductor integrated circuit test system 2 to which the present invention is applied includes a host computer 10, a plurality of test apparatuses 11 (# 1 to #m), and a plurality of test objects 12 (# 1 to #n). Consists of. The test pattern and test program used in the test system 2 are made up of a test circuit created according to the test object 12 to be inspected and described in HDL or C language, and a test pattern and test program. Test data is stored in the host computer 10, and these data are transmitted to a memory 22 (see FIG. 2) comprising a flash memory, SRAM, and DRAM provided on the test apparatus 11.

  In the test apparatus 11, under the control of the CPU 20 (see FIG. 2), test data is directly written from the memory 22 to the FPGA 21 (see FIG. 2), and the test object 12 is a plurality of chips formed on a semiconductor wafer, for example. On the other hand, a desired test is executed.

  The test object 12 typically indicates a predetermined combination unit (for example, 16) of a plurality of chips formed on the semiconductor wafer, and the test apparatus 11 is made relative to the semiconductor wafer after one test is completed. The unit test target when testing the whole chip formed on the semiconductor wafer is shown by moving the unit for each unit. Note that the test target 12 is not limited to a semiconductor wafer chip, and may be a plurality of identical semiconductor chips after mounting, for example.

  In general, the host computer 10 is connected to the test apparatus 11 to transmit test data, and is connected to the system LAN 14 by the Ethernet (registered trademark) system to control the entire semiconductor manufacturing factory. Send and receive production management data. The host computer 10 is connected to a control device 13 such as a prober for moving the test device 11 and the test object 12 relative to each other and a handler for controlling the start / end of the test in GPIB (General Purpose Interface Bus) connection. The signal transmission / reception with the control device 13 is performed. Further, the host computer 10 is connected to each test apparatus 11 by USB and manages an ID number unique to each test apparatus 11.

  The host computer 10 and the plurality of test devices 11 do not take the form of connection by a conventional hub, but the test device # 1 is directly connected to the host computer 10 with the host computer 10 as the highest level. Device # 2 and test devices # 3 to #m on its lower side are daisy chain connected. Thus, a large amount of test data can be transmitted from the host computer 10 to each test apparatus 11 by a so-called bucket relay system.

  As shown in FIG. 2, the test apparatus 11 includes a USB controller 27 having a CPU 20, FPGA 21, memory 22, USB host connector 23, USB device connector 24, USB host controller 25, and USB device controller 26. Similar to the FPGA 101 of the test apparatus 100 shown in FIG. 7, the FPGA 21 performs a test on the test target 12 by logically synthesizing a test circuit described in HDL or C language, a test pattern, and a test program. The test circuit is formed in the FPGA 21 by inputting a test pattern and a test program stored in the memory 22 under the control of the CPU 20. Further, the FPGA 21 transmits the test result to the memory 22 under the control of the CPU 20 and accumulates the test result in the memory 22.

  The memory 22 stores and holds a test circuit transmitted as a bit stream from the host computer 10 and test data including a test pattern and a test program under the control of the CPU 20. The memory 22 transmits test data including a test pattern and a test program to the FPGA 21 under the control of the CPU 20 so that an arbitrary test can be performed. Further, the memory 22 receives and accumulates test results from the FPGA 21 under the control of the CPU 20. Furthermore, the memory 22 transmits the test result to the USB controller 27 under the control of the CPU 20.

  The USB host controller 25 transmits test data including a test pattern and a test program transmitted from the upper side via the USB device connector 24 and the USB device controller 26 under the control of the CPU 20 via the USB host connector 23. Forward to the side. Further, the USB host controller 25 sends data (for example, test result data) transmitted from the lower side via the USB host connector 23 under the control of the CPU 20 via the USB device controller 26 and the USB device connector 24. Transfer to the upper side. If necessary, the USB host controller 25 can store the data transmitted from the lower side in the memory 22 under the control of the CPU 20.

  Under the control of the CPU 20, the USB device controller 26 transfers test data including a test pattern and a test program transmitted from the upper side via the USB device connector 24 to the lower side via the USB host controller 25. Further, the USB device controller 26 is under the control of the CPU 20 when the test data including the test pattern and the test program transmitted from the upper side via the USB device connector 24 designates its own test apparatus 11. The data is taken into the memory 22 under the control of the CPU 20. Further, the USB device controller 26 receives data (for example, test result data) transmitted from the lower side via the USB host connector 23 and the USB host controller 25 under the control of the CPU 20, and the USB device connector 24. To the upper side.

  The USB host connector 23 and the USB device connector 24 respectively connect the USB host controller 25 to the lower side and connect the USB device controller 26 to the upper side.

  The CPU 20 is bus-connected to the FPGA 21, the memory 22, the USB host controller 25, and the USB device controller 26. The CPU 20 performs the above-described control, and communicates with the FPGA 21 during the test period. In addition to monitoring the flow, control such as test suspension, interruption, and test skipping is performed according to the test results.

  In FIG. 3 showing the program configuration of the host computer 10 and each test apparatus 11, a program 30 realizes communication between the respective applications, causes the USB controller 27 to function as a bridge, and allows the host computer 10 and each test apparatus 11 to In order to make it possible to construct an application without directly being aware of the daisy chain connection, it has three layers of protocols: a USB physical layer 31, an inter-site communication layer 32, and a system communication layer 33. Each of these layers 31 to 33 provides an application interface (API) to the upper layer.

  The USB physical layer 31 performs communication processing between the host and the device in conformity with the USB 1.1 standard, for example. As the communication method using the USB physical layer 31, for example, interrupt transfer and bulk transfer are used.

  The inter-site communication layer 32 of the test apparatus # 1 connected immediately below the host computer 10 transmits the test data received from the host computer 10 to the test apparatus # 2 and data received from the test apparatus # 2 (for example, Test result data) is transmitted to the host computer 10. Further, the inter-site communication layer 32 of each of the test devices 11 after the test device # 2 transmits the test data from the host computer 10 received from the higher-order test device 11 to the lower-order test device 11 and the lower-order test device 11 Data (for example, test result data) received from the side test apparatus 11 is transmitted to the upper side test apparatus 11. In the following description, the upper test apparatus 11 is expressed as an upper site, and the lower test apparatus 11 is expressed as a lower site.

  Transfer of test data from the host computer 10 is performed to a plurality of test apparatuses 11 at the most efficient size in consideration of the transfer size of the USB 1.1 standard. On the other hand, the test result from the test apparatus 11 is transferred to the host computer 10 for each test apparatus 11. Here, for example, when the test data from the host computer 10 does not specify the test device # 1, but specifies the test device # 2, as shown in FIG. Communication is relayed only by the inter-site communication layer 32 without passing through the system communication layer 33 and the microcomputer control application layer 34b. Thereby, it can be considered that the host computer 10 and each test apparatus 11 are virtually connected by 1: 1. Further, when viewed from the host computer 10 side, one request can be simultaneously transmitted to a plurality of designated test apparatuses 11.

  The system communication layer 33 realizes system communication between the host computer 10 and the test apparatus 11 in association with a UI (User Interface) application layer 34a and a microcomputer control application layer 34b. This system communication layer 33 mainly performs message assembly / analysis, sequence control, data transfer waiting timer, event notification by function end, and the like.

  In the transmission / reception of data with the upper site, cooperation with the inter-site communication task of the lower site is performed using a message queue API. Here, if there is a specification for the own site, the message is also queued to the application task. An event is generated by this message queue. However, if the status must be changed immediately, such as when an error occurs, communication is performed using a shared memory.

  In the transmission / reception of data with the lower site, cooperation with the inter-site communication task of the lower site is performed using a message queue API. An event is generated by this message queue as in the case of data transmission / reception with an upper site. However, if the status must be changed immediately, such as when an error occurs, communication is performed using a shared memory.

  In system communication, a message is received from the host computer 10 or an upper site or a lower site, and an appropriate application module is selected from parameters or commands in the message to execute processing. An event is generated by an interrupt signal from the message queue and FPGA 21.

  Next, the effect | action by the said structure is demonstrated with reference to the flowchart of FIG. 5 and FIG. 5 shows a processing procedure in the host computer 10, and FIG. 6 shows a processing procedure in the test apparatus 11.

  First, the host computer 10 is connected to the control device 13 and the system LAN 14, and the host computer 10 and the plurality of test devices 11 are daisy chain connected via the USB host connector 23 and the USB device connector 24. A semiconductor integrated circuit test system 2 is constructed.

  In FIG. 5, the host computer 10 performs application processing by the UI application layer 34a. When a message is queued in this state, an interface (I / F) with the system communication layer 33 of the lower site is established, and system communication is performed.

  If the data communication direction in the system communication layer 33 is from the UI application layer 34a, the system communication layer 33 analyzes and assembles the message, and the UI application layer 34a performs sequence control corresponding to the message. After that, an I / F with the inter-site communication layer 32 is established. On the other hand, when the communication direction is from the inter-site communication layer 32, the message is transferred to the UI application layer 34a.

  When the data communication direction in the inter-site communication layer 32 is from the USB physical layer 31, the message is transferred to the system communication layer 33. On the other hand, if the communication direction is from the system communication layer 33, the message is transferred to the host side of the USB physical layer 31.

  In FIG. 6, in the test apparatus 11, application processing by the microcomputer control application layer 34b is performed. When a message is queued in this state, an I / F with the system communication layer 33 of the lower site is established, and the local site system communication is performed.

  If the data communication direction in the system communication layer 33 is from the microcomputer control application layer 34b, the system communication layer 33 analyzes and assembles the message, and then the I / F with the inter-site communication layer 32 is Established. On the other hand, when the communication direction is from the inter-site communication layer 32, the message is transferred to the microcomputer control application layer 34b.

  When the data communication direction in the inter-site communication layer 32 is from the USB physical layer 31 and is intended for the own site, the message is transferred to the system communication layer 33. If it is not intended for its own site, the message is transferred to the host side of the USB physical layer 31. On the other hand, if the communication direction is from the system communication layer 33, the message is transferred to the device side of the USB physical layer 31.

  As described above, in the test apparatus # 1 connected immediately below the host computer 10, the data received from the host computer 10 is transmitted to the test apparatus # 2, and the data received from the test apparatus # 2 is transmitted to the host computer 10. In each of the test apparatuses 11 after the test apparatus # 2, the data from the host computer 10 received from the upper test apparatus 11 is transmitted to the lower test apparatus 11 and the lower test apparatus 11 receives the test data. Data received from the apparatus 11 is transmitted to the higher-level test apparatus 11.

  In each test apparatus 11, a test program from the host computer 10 is stored in the memory 22. The test program stored in the memory 22 is read out to the FPGA 21. A desired test circuit is configured by the FPGA 21, and a desired test is executed on each test target 12.

  After the test is completed, the test result is transmitted to the host computer 10 for each test apparatus 11. In the host computer 10, evaluation data for each test object 12 is created based on the transmitted test results.

  With the configuration as described above, the load time of test data consisting of test patterns and test programs, which conventionally takes the number of test devices 11, can be reduced by the load time for one unit. Time can be shortened dramatically. That is, as a communication method, a USB method that does not require setting of a special IP address such as the Ethernet (registered trademark) method is used, and the host computer 10 is set at the highest level and the host computer 10 is directly connected to the host computer 10. Is connected, and the lower-level test device 11 is daisy chain-connected, so that a large amount of test pattern data (several megabytes) is transmitted from the host computer 10 on the data transmission side to the test device 11 on the data reception side. And test program data as test condition data (having several hundred kilobytes) may be transmitted once, and loading can be performed with a load time of one unit. On the other hand, test result data individually transmitted from each test apparatus 11 is transmitted from the lower-level test apparatus 11 to the highest-level host computer 10. Since the data is remarkably small in comparison with the test data composed of the pattern and the test program, the transmission / reception is not a problem. Therefore, the operation efficiency of the entire semiconductor manufacturing process can be improved.

  In the above embodiment, the semiconductor integrated circuit test system 2 has been described as an example. However, the present invention is not limited to this, and a large amount of data is commonly transmitted from the host computer 10 to a plurality of devices. For example, a small amount of data for each device is transmitted from each device to the host computer 10, for example, the same data is transmitted from the host computer to a terminal that is a plurality of devices, and an answer is transmitted from each terminal to the host computer. It can also be used for a video / audio dubbing system in which a video signal is transmitted from a host system to a large number of terminals.

It is a figure which shows schematic structure of the test system of the semiconductor integrated circuit to which this invention is applied. It is a block diagram which shows the internal structure of a test apparatus. It is a schematic diagram which shows the program structure of a host computer and a test apparatus. It is a schematic diagram which shows the example when not taking in data to the test apparatus # 1. It is a flowchart which shows the process sequence in a host computer. It is a flowchart which shows the process sequence in a test apparatus. It is a figure which shows schematic structure of the conventional test apparatus.

Explanation of symbols

2 Test System 10 Host Computer 11, 100 Test Device 12 Test Target 20 CPU
21, 101 FPGA
22 Memory 23 USB Host Connector 24 USB Device Connector 25 USB Host Controller 26 USB Device Controller 27 USB Controller 30 Program 31 USB Physical Layer 32 Intersite Communication Layer 33 System Communication Layer

Claims (6)

A system for transmitting and receiving data between a host computer and a plurality of logical devices,
A USB host connector for transmitting the data to the logic device, and a USB host controller for controlling the transmission of the data;
A USB device connector for receiving the data from the outside, and a USB device controller for controlling the reception of the data;
With the host computer as the highest level, the host computer and the plurality of logical devices are daisy chain connected via the USB host connector and the USB device connector,
The first logical device connected directly under the host computer transmits data received from the host computer to the second logical device, and receives data received from the second logical device. To the host computer,
Each logical device after the second logical device transmits data received from the host logical device to the lower logical device and data received from the lower logical device. Is transmitted to the upper logical device.   The data transmission / reception system according to claim 1, wherein the logical device only relays transmission / reception of the data when the data is not captured.   The data transmission / reception system according to claim 1, wherein the logic device is a test apparatus that creates a test circuit from a test program for a semiconductor integrated circuit and verifies the operation of the semiconductor integrated circuit. A host computer and a plurality of logical devices, the logical device including a USB host connector for transmitting data to the outside, a USB host controller for controlling transmission of the data, and for receiving the data from the outside A USB device connector and a USB device controller for controlling reception of the data are provided;
The host computer and the plurality of logical devices are used in a data transmission / reception system in which the USB host connector and the USB device connector are connected in a daisy chain,
The first logical device connected immediately below the host computer causes the data received from the host computer to be transmitted to the second logical device, and the data received from the second logical device is Realizing the function of sending to the host computer,
Data received from the host logical device received from the upper logical device is transmitted to the lower logical device by each logical device after the second logical device and data received from the lower logical device. A data transmission / reception program that realizes a function of transmitting a message to the upper logical device.   5. The data transmission / reception program according to claim 4, wherein when the data is not taken into the logical device, the logical device is allowed to realize a function of only relaying the transmission / reception of the data.   6. The data transmission / reception program according to claim 4, wherein the logic device is a test apparatus that creates a test circuit from a test program for a semiconductor integrated circuit and verifies the operation of the semiconductor integrated circuit.

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