JP2005149051A - Data conversion device and method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the memory capacity needed for data storage, without deteriorating interpolation accuracy even if data conversion for color space conversion is carried out using interpolation operations. <P>SOLUTION: This data conversion device which calculates output color data corresponding to input color data through, e.g., four-point interpolation, has a plurality of independently controllable memory spaces with number smaller than the number of predetermined data for interpolation operations. The basic data needed for the interpolation operations are stored in the memory spaces. The basic data are grouped so that each constitutes an independent plane according to their differences in the direction of growth. The plurality of basic data in each group is stored in the corresponding memory space. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a data conversion apparatus and a data conversion method for converting input image data belonging to a certain color space into output image data belonging to another color space, for example, RGB color space → CMYK color space.

  In general, an image input device such as a scanner and an image output device such as a printer use color signals (data values) defined in a color space unique to each device. For example, a scanner expresses colors in the RGB space, and a printer expresses colors in the CMYK space. Therefore, when the image data read by the scanner is printed out by the printer, it is necessary to perform a color space conversion process on the image data such as the RGB color space → the CMYK color space.

It is known that such a color space conversion process is performed using a multi-dimensional LUT (Look Up Table). When a multi-dimensional LUT is used, an output value corresponding to an input signal is usually calculated in advance, and the value is stored as a table so that an output value corresponding to the input value can be obtained without calculation. Is possible.
However, for example, if a color space conversion process such as RGB color space → CMYK color space is performed using only a multidimensional LUT, a large-capacity memory is required. Specifically, if each color of R, G, B is an 8-bit signal and each color of output, Y, M, C, K is also an 8-bit signal, the combination of input values is 2 ⁸ × 2 ^8. × 2 ⁸ = 16,777,216 types, and a 16 megabyte (Mbyte) memory is required to convert R, G, B input into one of Y, M, C, K colors Become. Therefore, in order to convert into four colors of Y, M, C, and K, a memory of 64 megabytes, which is four times 16 megabytes, is required. That is, an LUT corresponding to input 24 bits and output 8 bits is required. In this case, the memory capacity per output color is 16 M (mega) bytes, and the above-described memory is required for the number of colors of the output device. Therefore, the actual memory capacity is as large as 48 to 64 Mbytes. Therefore, this memory capacity has a large impact on the system from the viewpoint of cost, and is not realistic.
For this reason, when a multi-dimensional LUT is used in color conversion processing, it has been proposed to reduce the memory capacity of the LUT by using interpolation processing together. This is because an output value corresponding to only the upper multiple bits of the input signal is configured as an LUT, and if there is no output value corresponding to the input signal, interpolation processing is performed using the neighborhood data of the spatial position indicated by the input value. By calculating the applied output value, the capacity of the LUT can be reduced.

As an interpolation calculation process combining the LUT and the interpolation process, for example, a four-point interpolation method (Tetra-Hydra interpolation) is known (see, for example, Patent Documents 1, 2, and 3). Tetra-hydra interpolation calculation (tetrahedral interpolation calculation), for example, constitutes a grid consisting of data of three input elements, and determines which grid contains the corresponding data from the upper bits of the three input elements Then, it is further divided into six tetrahedrons, and it is determined which tetrahedron contains the corresponding data from the lower bits of the three input elements, and the basic data obtained from the tetrahedron vertex and each tetrahedron are determined. The calculation is based on the obtained multiplier (interpolation coefficient). In this case, since the required tetrahedron is uniquely determined when the input data is determined, in order to determine the tetrahedron, a total of four vertices obtained from two line segments that do not intersect with each other are sufficient.
Using such a tetra-hydra interpolation operation, for example, when converting input R, G, B to any one color (output color), the number of data stored in the LUT is 17 data × 17 data × 17 data. When defined, the LUT capacity can be realized by 4.9 kilobytes, and the capacity can be significantly reduced as compared with 16 megabytes in a method not using interpolation processing.
In addition to tetra-hydra interpolation, it has also been proposed to use a five-point interpolation method (for example, see Patent Document 1) or a cubic interpolation method (eight-point interpolation method) as an interpolation calculation process. (For example, refer to Patent Document 2).

  As described above, the interpolation calculation processing combining the LUT and the interpolation processing is performed depending on how many pieces of data (grid point data) read out from the LUT are used and what kind of relation is used. Can be classified into methods. In general, in the method using a lot of grid point data, the interpolation accuracy is improved, but the scale of the interpolation circuit is increased. Tetra-hydra interpolation is known as an interpolation method with a relatively small circuit scale, and 8-point interpolation is known as an interpolation method with a large circuit scale but good interpolation accuracy. Regardless of which method is used, the number of grid point data (number of interpolation calculation data) when performing interpolation calculation using each grid point data of the three-dimensional cubic grid is determined by the grid point of the original LUT. It is determined according to the polyhedron that internally divides the unit cube. For example, when a cubic lattice is targeted, the number of interpolation calculation data is a minimum of 4 (tetra-hydra interpolation) and a maximum of 8 (8-point interpolation method).

JP-A-8-181874 Japanese Examined Patent Publication No. 58-16180 JP-A-56-14237

However, the above-described conventional color space conversion process, that is, the interpolation calculation process combining the LUT and the interpolation process has the following problems.
For example, in the color space conversion process described in Patent Document 1, when the time allocated as the color space conversion processing time for one pixel is very short, a plurality of data is stored from the memory used as the LUT. Since it is impossible to read the data once, it is necessary to use the same amount of memory as the number of data for the interpolating operation.
In the case of tetra-hydra interpolation, assuming conversion from RGB to YMCK, four for extracting four grid points for conversion to Y, four for conversion to M, and for conversion to C A total of 16 memories of the same capacity are required. Therefore, when the number of data stored in the LUT is defined as 17 data × 17 data × 17 data as described above, the total memory capacity is 78.6 kilobytes. In addition, when emphasizing interpolation accuracy and assuming 8-point interpolation, 32 memories are required, and the total memory capacity is 157.2 kilobytes.
On the other hand, simultaneously accessing a large number of memories in a certain unit time as well as an increase in memory capacity may increase power consumption and radiation noise.

  Therefore, the present invention does not deteriorate the interpolation accuracy even when data conversion for color space conversion is performed using an interpolation operation, and further, the memory capacity for data storage, power consumption, An object of the present invention is to provide a data conversion apparatus and a data conversion method that can reduce radiation noise.

  The present invention is a data conversion device devised to achieve the above object. That is, based on the grid point data used when converting the input color data to the output color data, for each pixel data of the input color data, the unit grid of which the pixel data constitutes the set of grid point data A unit grid determining unit that determines which one belongs, and a corresponding unit grid determined by the unit grid determining unit is further divided into a plurality of polyhedrons, and the pixel data is assigned to which polyhedron. A polyhedron determination unit that determines whether the pixel belongs to, and an interpolation calculation processing unit that determines pixel data for output corresponding to the input pixel data by interpolation calculation in the corresponding polyhedron determined by the polyhedron determination unit A plurality of memory spaces that can be controlled independently of each other than the number of interpolation calculation data defined in accordance with the polyhedron, and input color signals of k colors The basic data corresponding to the lattice point data associated with each lattice point of the k-dimensional lattice space defined by the prime is stored, and the basic data is divided into a plurality of groups according to a predetermined criterion, A data storage unit that stores the plurality of basic data in the group in corresponding ones of the plurality of memory spaces, and a plurality of the basic data associated with the group stored in the data storage unit. Basic data corresponding to the number of data for the interpolation calculation station corresponding to the pixel data to be processed is extracted from the inside, and the interpolation calculation processing unit interpolates the basic data for the number of data for the interpolation calculation station extracted in the polyhedron A basic data extraction unit that is used as basic data to be used when performing calculations, and the plurality of groups include basic data belonging to the group. It is characterized in that each the difference in the growth direction are grouped to constitute an independent planes.

  The present invention is also a data conversion method devised to achieve the above object. That is, based on the grid point data used when converting the input color data to the output color data, for each pixel data of the input color data, the unit grid of which the pixel data constitutes the set of grid point data It is determined which one belongs, and the corresponding unit lattice is further divided into a plurality of polyhedrons to determine to which polyhedron the pixel data belongs, and by interpolation operation in the corresponding polyhedron A data conversion method for determining pixel data for output corresponding to the input pixel data, the number of which can be independently controlled less than the number of interpolation calculation data defined according to the polyhedron The basic data corresponding to the grid point data associated with each grid point of the k-dimensional grid space defined by the k-color input color signal elements is used as a predetermined reference. Therefore, it is divided into a plurality of groups, and for each group, the plurality of basic data in this group are stored in the corresponding ones in the plurality of memory spaces, and the plurality of basic data associated with the group are selected from the plurality of basic data. In addition, the basic data for the number of data for the interpolation calculation office corresponding to the pixel data to be processed is extracted, and the basic data for the number of data for the interpolation calculation office extracted is used to perform the interpolation calculation in the polyhedron, The plurality of groups are grouped so that each of them forms an independent plane depending on the growth direction of basic data belonging to the group.

According to the data conversion apparatus having the above-described configuration and the data conversion method according to the above-described procedure, when determining pixel data for output corresponding to pixel data input by interpolation calculation within a polyhedron, it is defined according to the polyhedron. A memory space that is independently controllable in number smaller than the number of data for interpolation operation is used. Here, the “number of data for interpolation calculation” means the number of basic data necessary for the interpolation calculation. For example, in the case of the four-point interpolation method (tetra-hydra interpolation), four or eight-point interpolation is performed. In the case of the law, the number is 8. The “basic data” is data necessary for the interpolation calculation, and may be the original LUT lattice point data itself, or is not limited to this, but is predetermined data corresponding to the original LUT lattice point data. There may be. In addition, “independently controllable memory space” means that at least a read address can be set independently for each memory space when reading basic data required for interpolation calculation from the data storage unit. Means. More preferably, the read clock can also be set independently. Further, it is more preferable that the output of each memory space can be set to a high impedance state independently.
In each memory space, basic data corresponding to lattice point data associated with each lattice point of the k-dimensional lattice space defined by the k input color signal elements is divided into a plurality of groups according to a predetermined standard. For each group, a plurality of basic data in the group are stored in corresponding ones in a plurality of memory spaces. That is, for each memory space, basic data is grouped according to a predetermined standard, a common address is assigned to each basic data in each group, and stored in each memory cell. Here, “k” is the number of colors in the input color data. For example, if “k color” is three colors, “k dimension” in the input color space is three dimensions.
However, at this time, when grouping the basic data, the grouping is performed so that each group forms an independent plane depending on the growth direction of the basic data belonging to the group. Therefore, even if not all the basic data corresponding to the grid point data associated with each grid point in the k-dimensional grid space is stored in the memory space, the basic data is stored in the memory space for at least two planes. If stored, lattice point data associated with each lattice point can be specified. That is, it is not necessary to provide the same capacity of independently controllable memory space as the number of data for interpolation calculation, and it is not necessary to make the number of grid point data and the number of memory spaces required for the interpolation calculation the same.
In the actual interpolation calculation, basic data corresponding to the number of interpolation calculation data corresponding to the pixel data to be processed is extracted from the plurality of basic data associated with the group, and the extracted interpolation calculation data is used. Interpolation calculation within the polyhedron is performed using the basic data for the number of data.

According to the data conversion device and the data conversion method of the present invention, each group of basic data corresponding to a plurality of memory spaces forms an independent plane depending on the growth direction of the basic data belonging to the group. Since it is divided into groups, if the basic data for two planes is stored in the memory space, it is possible to specify the grid point data associated with each grid point and control them independently with the same capacity It is not necessary to provide as many memory spaces as there are data for the interpolation operation, and it is not necessary to make the number of grid point data and the number of memory spaces required for the interpolation operation the same. Therefore, for example, in the case of four-point interpolation, it is only necessary to have a memory for holding grid point data less than four times (for example, twice), and the total memory capacity necessary for achieving the same function and independent control are possible. The number of memory spaces can be reduced. For example, conventionally, 17 × 17 × 17, that is, 4,193 bytes are required to extract one interpolation calculation data, and in the case of four-point interpolation, the number of four grid points is extracted at the same time. Double, that is, 4913 bytes × 4 = 19,652 bytes, but according to the present invention, it is possible to simultaneously extract data of 4 lattice points with a memory having a capacity of 2/4. It becomes.
In addition, since the number of memory spaces for simultaneous access can be reduced, power consumption and radiation noise can be reduced.

  Hereinafter, a data conversion apparatus and a data conversion method according to the present invention will be described with reference to the drawings.

[First Embodiment]
First, a first embodiment of the present invention will be described. Here, an R, G, B 8-bit input digital color separation signal is inputted, and a data conversion apparatus and data for color-converting it into 8-bit data of each of the output color components Y, M, C, K The conversion method will be described as an example. However, the format of the input data and output data is merely an example, and other color series may be used, and it goes without saying that the number of bits is not limited to “8”.

FIG. 1 is a block diagram showing a first embodiment of a data conversion apparatus according to the present invention.
As shown in the figure, the data conversion apparatus 1 described in the present embodiment includes a data storage unit 2, an arithmetic processing unit 4, an address bus 6, and a data bus 8.

The data storage unit 2 stores basic data for each output color. The basic data is used when obtaining output data Y, M, C, and K after color conversion corresponding to the input data R, G, and B by interpolation calculation. For example, the interpolation calculation by the tetra-hydra method is performed. If so, the original lattice point data of the three-dimensional LUT corresponds to this.
The data storage unit 2 is divided into two memory spaces, an RG plane memory circuit 2RG and an RB plane memory circuit 2RB, so as to correspond to the input data R, G, B. As will be described in detail later, each of the planar memory circuits 2RG and 2RB, that is, each of the two memory spaces that can be controlled independently, has a three-dimensional lattice space (three-dimensional) defined by input color signal elements of three colors. The basic data corresponding to the grid point data associated with each grid point of the LUT) is grouped according to a predetermined standard for each axis of the input color, and a plurality of basic data in the group is associated with one address. The lookup table LUT for each axis is configured.

  These memory circuits 2RG and 2RB are independently addressable and readable so as to be able to cope with the case where the time allocated as the color space conversion processing time for one pixel is very short. In other words, the read access is made independently. It is preferable to use an independent read enable terminal RE or chip select terminal CS that can set the output of a memory circuit that is not necessary for reading to a high impedance state.

  The arithmetic processing unit 4 obtains output pixel data corresponding to input pixel data by interpolation calculation for each output color while exchanging data with the data storage unit 2. Therefore, the arithmetic processing unit 4 has a Y signal generation unit 4Y, an M signal generation unit 4M, and a C signal generation unit so as to correspond to the output color components Y, M, C, and K as signal processing systems. 4C and K signal generator 4K. The arithmetic processing unit 4 may be constituted by, for example, a central processing unit (CPU) or a DSP (Digital Signal Processor).

  The address bus 6 connects between the data storage unit 2 and the arithmetic processing unit 4. In order for the arithmetic processing unit 4 to read basic data from the data storage unit 2, a control signal such as an address signal is transmitted to the data storage unit. 2 to send. Specifically, an address signal, a clock, a chip select signal, or the like for setting a reading position of basic data in each memory space (memory circuits 2RG, 2RB) in the data storage unit 2 is transmitted.

  The data bus 8 also connects between the data storage unit 2 and the arithmetic processing unit 4. However, the data bus 8 is configured to send the basic data read from the data storage unit 2 to the arithmetic processing unit 4. Further, the data bus 8 is used for inputting input data before data conversion from an external device (not shown) and for outputting output data after conversion to the same or another external device.

Next, an example of processing operation in the data conversion apparatus 1 configured as described above, that is, a data conversion method according to the present invention will be described.
FIG. 2 is a flowchart showing an outline of the first embodiment of the data conversion method according to the present invention.

When converting the color data, the arithmetic processing unit 4 uses the grid point data of the color conversion LUT (look-up table) stored in the data storage unit 2 to input R, G, B input from an external device. Is converted into Y, M, C, and K color data, interpolation processing using a tetra-hydra method (tetrahedral interpolation method) is used.
Therefore, when image data R, G, and B are input, the arithmetic processing unit 4 first converts the input 8-bit R, G, and B digital color separation signals into upper m bits (most significant) for each pixel. It is divided into m consecutive from the bit side) and lower n bits (n consecutive from the least significant bit side) (step 100; hereinafter, step is abbreviated as “S”). The arithmetic processing unit 4 configures a three-dimensional lattice (three-dimensional LUT) composed of R, G, B data of the three input elements based on the upper m bits of data RH, GH, BH of the three input elements. At this time, it is determined which unit cube of a large number of unit lattices (in this example, unit cubes) defined by each lattice point contains the corresponding data (S102). The processing of steps S100 to S102 is hereinafter referred to as “unit cube determination processing”.

  When the unit cube determination process is completed, the arithmetic processing unit 4 further divides the corresponding unit cube into six tetrahedrons (S104), and converts the input three element lower n-bit data RL, GL, BL into Based on which tetrahedron the corresponding data is included is determined (S106). The processing of steps S104 to S106 is hereinafter referred to as “tetrahedron determination processing”.

When the tetrahedron determination process ends, the arithmetic processing unit 4 then outputs the output corresponding to the input value (input pixel data) by the tetra-hydra method (tetrahedral interpolation method) which is an interpolation calculation within the corresponding tetrahedron. A value (pixel data to be output) is obtained (S108).
Specifically, the arithmetic processing unit 4 first selects two memory planes from which the basic data of the four lattice points necessary for the interpolation calculation processing by the tetra-hydra method is extracted from the two memory circuits 2RG and 2RB. An access memory specifying process is specified (S108a). Next, the arithmetic processing unit 4 specifies and extracts four grid points necessary for the interpolation calculation in the data group of the same address specified in the access memory plane specifying process based on the coordinate value of the base point including the input point. The four grid point specifying process is performed (S108b). The access memory specifying process (S108a) and the 4-grid point specifying process (S108b) are collectively referred to as an access address specifying process.
In addition to the access memory specifying process (S108a) and the four lattice point specifying process (S108b), the arithmetic processing unit 4 performs four basic data (in this example, the original data obtained from the tetrahedron vertices) for the corresponding tetrahedron. An interpolation coefficient calculation process is performed to calculate an interpolation coefficient that is a weighting coefficient (multiplication coefficient) for the grid point data itself (S108c). Then, the arithmetic processing unit 4 is based on the basic data (grid point data) obtained by the 4-grid point specifying process (S108b) and the interpolation coefficient obtained by the interpolation coefficient calculation process (S108c) for the corresponding tetrahedron. Then, an interpolation calculation process for obtaining the output value Dout corresponding to the input value is performed (S108d).

  The arithmetic processing unit 4 performs the above-described series of processing for each of the output colors Y, M, C, and K (S112) and all the pixels (S100), so that the input color data in the RGB color space is obtained. Is converted to YMCK color space data.

Here, the LUT necessary for the series of processes as described above will be described in more detail.
FIG. 3 and FIG. 4 are diagrams for explaining an LUT that constitutes grid point data that is a representative value of output values. Here, for each of the R, G, and B axes, a three-dimensional LUT storing the converted data corresponding to 17 × 17 × 17 = 4913 lattice points as representative values is used as the original lattice point data. A case will be described as an example. The data storage unit 2 of the present embodiment has the same grid point data in two memory spaces of the same capacity corresponding to the input color signals R, G, and B. For this reason, as shown in FIG. 1, two memory circuits 2RG and 2RB are provided.
Each of (A) in FIGS. 3 and 4 shows a part of the RGB three-dimensional space. Each of FIGS. 3 and 4 (B) shows the relationship between addresses and basic data in the memory space of the memory circuits 2RG and 2RB, that is, the LUT of each axis. Note that the method of using the “address in the case of a two-dimensional address” shown at the bottom of the table in each of FIGS. 3 and 4 is the second embodiment (see FIG. 18) or the second specific circuit configuration. An example (see FIG. 20) and a third example (see FIG. 21) will be described.

In the prior art, representative values of output values are stored as LUTs for each grid point position indicated by a circle in the figure, and each grid point position is an address on a memory for storing grid point data. That is, as described above, 4913 addresses were defined.
On the other hand, in the present embodiment, a plurality of basic data (in this example, lattice point data itself) is associated with one address and stored (mapped) in units of groups. That is, when an arbitrary address is set, a plurality of basic data in a group registered in association with the address are collectively output as packing data. Here, “output a plurality of basic data collectively as packing data” is not limited to outputting a plurality of basic data in parallel at the same time, but sequentially outputs the basic data in time series. Including. The form in which a plurality of basic data is output depends on the configuration of the memory circuits 2RG and 2RB for each axis and the configuration of the readout circuit.

  For example, as shown in FIG. 3 (A), the basic data in the R-axis direction is divided into a plurality of groups along the axis parallel (bundled), and the basic data in the G-axis direction is further parallel to the axis. By dividing into a plurality of groups, the RG plane memory circuit 2RG stores the RG plane LUT. The thick line in the figure indicates that the basic data is divided into groups (in a lump). That is, basic data (lattice point data itself in this example) is addressed by an arbitrary combination of GH and BH, and basic data for 17 × 17 = 289 grids is held in one address. FIG. 3B shows an RG plane LUT which is a relationship between the address and basic data on the RG plane memory circuit 2RG.

  Similarly, as shown in FIG. 4A, in the G-axis memory circuit 2G, basic data in the G-axis direction is divided into a plurality of groups along the axis in parallel (in a lump), and further in the B-axis direction. Are stored in the RB plane memory circuit 2RB to form an RB plane LUT. The thick line in the figure indicates that the basic data is divided into groups (in a lump). Here, basic data (lattice point data itself in this example) is addressed by any combination of GH and BH, and basic data for 17 × 17 = 289 lattice points is held in one address. FIG. 4B shows an RB plane LUT which is a relationship between addresses and basic data on the RB plane memory circuit 2RB.

  At the time of interpolation processing in the arithmetic processing unit 4, two basic data matching the input data are read out from the above-described data string held together in the memory circuits 2RG and 2RB. When this method is used, the LUT capacity can be realized with 4.9 kilobytes when converting the input data R, G, B to one color, which is much larger than 16 megabytes in the method that does not use interpolation processing. The advantages of the Tetra Hydra method that it can be reduced can be enjoyed, and the number of memories to be used (number of memory spaces) and the number of memories that are simultaneously read-accessed can be reduced as compared with the conventional configuration.

Next, the unit cube determination process (S100 to S102) in the series of processes shown in FIG. 2 will be described in more detail.
FIG. 5 is a diagram for explaining the unit cube determination processing by the arithmetic processing unit 4, and is a diagram for explaining the relationship between the original three-dimensional LUT constituting the lattice point data that is the representative value of the output value and the input data. is there. Here, FIG. 5A shows a conceptual diagram of the LUT in a three-dimensional space, and FIG. 5B shows a three-dimensional LUT in which each 8-bit RGB input signal corresponds to the upper 4-bit signal of each signal. The positional relationship is shown above.

  As shown in FIG. 5A, the range of possible values for each of the R, G, and B axes is divided into a plurality. Here, an example in which each axis is divided into 16 is shown. The LUT is configured by using the grid point obtained by such division as an address and associating the converted value (representative value) at the grid point. Therefore, in this example, it is possible to create a three-dimensional LUT that stores the corresponding converted data as representative values for 17 × 17 × 17 = 4913 lattice points.

  Arithmetic processing unit 4 receives input 8-bit R, G, B digital color separation signals as upper m bits (m consecutive from the most significant bit) and lower n bits (n consecutive from the least significant bit). ). For example, the arithmetic processing unit 4 sets m = n = 4, and divides input R, G, B into upper 4 bits RH, GH, BH and lower 4 bits RL, GL, BL, respectively. Of course, m and n may be other than this. Note that “m + n” is preferably equal to 8 bits of input data.

  As shown in FIG. 5B, the spatial position of the combination value of 8-bit data (input pixel data) of any input R, G, B in the unit cube formed by the combination value of the upper 4-bit data Since P22 is included, it is possible to specify a unit cube that includes input 8-bit data by a unit cube (unit grid) based on the spatial position P21 indicated by the upper 4-bit data RH, GH, BH. Become.

  Each vertex constituting the unit cube can be generated with reference to the spatial position P21. That is, with (RH, GH, BH) as a base point, (RH + 1, GH, BH), (RH + 1, GH + 1, BH), (RH, GH + 1, BH), (RH, GH, BH + 1), (RH + 1, GH, BH + 1), (RH, GH + 1, BH + 1), (RH + 1, GH + 1, BH + 1) are the coordinates of the vertex of this unit cube. In the present embodiment, the coordinates of these vertices coincide with the coordinates of the lattice points of the original three-dimensional LUT.

  The arithmetic processing unit 4 outputs the output value corresponding to the combination value of the 8-bit data of the inputs R, G, and B, the neighboring grid point data, that is, the coordinates of the vertexes of the unit cube shown in FIG. Using the data as basic data, it is determined by the tetra-hydra method (tetrahedral interpolation method).

Next, the tetrahedron determination process (S104 to S106) in the series of processes shown in FIG. 2 will be described in more detail.
FIG. 6 is a diagram illustrating tetrahedron determination processing by the arithmetic processing unit 4. As described above, the arithmetic processing unit 4 of this embodiment stores the output signals YMCK corresponding to the combination values of the input digital color separation signals R, G, and B in the data storage unit 2. Based on the basic data (grid point data), it is obtained by interpolation calculation using the tetra-hydra method. FIG. 6 shows a relationship between a unit cube containing input data and a tetrahedron obtained by dividing the unit cube into six. The unit cube shown in FIG. 5B can be further divided into six unit tetrahedrons of the same volume as shown in FIG.

Which tetrahedron the spatial position P22 of the inputs R, G, B is included can be specified as shown in Table 1 shown in the lower part of FIG. 6 based on the magnitude relationship of the lower bit data RL, GL, BL. Further, the LUT and the access address to be accessed by the data selection unit 16 can also be specified as shown in Table 1.
In Table 1, X, Y, and Z are generalized three-dimensional input data. In this embodiment, X = R, Y = G, and Z = B. “17” shown at the base points A and B is the number of grid points obtained by dividing each axis of the three-dimensional LUT. Table 1 shows an access address when the input RGB is 8 bits each, the output is YMCK, and the LUT is composed of 17 × 17 × 17 = 4913 data corresponding to the upper 4 bits per color. This is a calculation formula.

  For example, when the lower bit data RL, GL, and BL have a relationship of RL ≧ GL ≧ BL, the inputs R, G, and B are (RH, GH, BH), (RH + 1, GH, BH), (RH + 1, GH + 1, BH), (RH + 1, GH + 1, BH + 1) belong to tetrahedron 1 having apexes. When RL> BL> GL, the inputs R, G, B are (RH, GH, BH), (RH + 1, GH, BH), (RH + 1, GH, BH + 1), (RH + 1, GH + 1, BH + 1). It belongs to tetrahedron 2 as a vertex. When BL ≧ RL> GL, the inputs R, G, B are (RH, GH, BH), (RH + 1, GH, BH + 1), (RH, GH, BH + 1), (RH + 1, GH + 1, BH + 1). Belongs to the tetrahedron 3 with apex as the apex.

  Similarly, when BL> GL ≧ RL, the inputs R, G, B are (RH, GH, BH), (RH, GH, BH + 1), (RH, GH + 1, BH + 1), (RH + 1, GH + 1). , BH + 1) belongs to the tetrahedron 4. When GL ≧ BL> RL, the inputs R, G, B are (RH, GH, BH), (RH, GH + 1, BH), (RH, GH + 1, BH + 1), (RH + 1, GH + 1, BH + 1). Belongs to the tetrahedron 5 with apex as the apex. When GL> RL ≧ BL, the inputs R, G, B are (RH, GH, BH), (RH, GH + 1, BH), (RH + 1, GH + 1, BH), (RH + 1, GH + 1, BH + 1). Belongs to the tetrahedron 6 with 頂点 as the apex.

  The arithmetic processing unit 4 performs such determination (tetrahedron determination) to identify four neighboring grid points on the three-dimensional LUT of the inputs R, G, and B. That is, first, the tetrahedron to which the input data belongs is specified based on the lower bit data RL, GL, and BL. In response to this result, two planes corresponding to the specified tetrahedron are specified, and the upper bit data RH, GH, BH specifying the unit cube containing the input data and the address calculation shown in Table 1 of FIG. An access address to the two planes is calculated according to the equation. Then, the arithmetic processing unit 4 acquires basic data of four neighboring lattice points by selecting basic data by tetrahedral determination from four basic data from the obtained access addresses of the two planes. When the LUT is configured with two planes in contact with each other, the two points in contact with each other are read from both LUTs. Therefore, if only two basic data are read from one LUT from the beginning, It is possible to reduce the scale of the selected portion of the basic data of the four neighboring grid points.

Next, the access memory specifying process (S108a) and the 4-grid point specifying process (S108b), which are the first stage of the output value calculating process (S108) in the series of processes shown in FIG. 2, will be described in more detail. .
FIG. 7 is a diagram for explaining the access memory specifying process and the four grid point specifying process by the arithmetic processing unit 4, and the relationship between the shape of each tetrahedron obtained by dividing a unit cube and the vertices constituting the tetrahedron FIG.

The tetrahedron 1 in the figure is composed of vertices of D1, D2, D3, and D4. Here, D1 and D2 are the same spatial position on the G and B coordinates, and can be collectively extracted from the RG plane LUT shown in FIG. On the other hand, the remaining D3 and D4 are the same spatial positions on the R and G coordinates, and in the RB plane LUT shown in FIG. 4, the spatial positions with a fixed difference of +17 with respect to α and α ′ are β, β It is possible to extract all at once.
Similarly, for the tetrahedrons 2 to 6, desired basic data can be obtained from the RG plane LUT shown in FIG. 3 and the RB plane LUT shown in FIG. 4.

  Therefore, the arithmetic processing unit 4 receives the determination result of the tetrahedron determination processing, and performs interpolation calculation by the tetra-hydra method from the two memory circuits 2RG and 2RB according to the selection conditions shown in Table 1 of FIG. An access memory specifying process for specifying two memories (that is, two LUTs storing a data group including four grid points) from which basic data of necessary four grid points is to be extracted is performed.

  Specifically, the arithmetic processing unit 4 indicates the upper bit data RH, GH, BH for specifying the unit cube containing the input data, that is, the coordinate value of the base point P21 in FIG. 5B and the table 1 in FIG. By calculating an access address to the two LUTs according to the access address formula, a data group including four lattice points necessary for the interpolation calculation by the tetra-hydra method is specified. After that, the arithmetic processing unit 4 is based on the coordinate values (RH, GH, BH) of the base point including the input point, and the four grid points necessary for the interpolation calculation by the tetra-hydra method in the data group having the same address. 4 grid point specifying process is performed for specifying and extracting.

  8 to 14 are diagrams for explaining specific examples of LUT access. Here, FIG. 8 is a diagram showing the positional relationship between the input data and the data in the three-dimensional LUT space. 9 to 14 are diagrams showing the correlation between the vertexes of the corresponding tetrahedron and the data structure of the LUT, respectively.

  In FIG. 8, the number of grid points is simplified to 3 × 3 × 3 = 27 data in total for 3 each of R, G, and B. It is assumed that the position in the three-dimensional space indicated by each arbitrary 8-bit RGB value (input data) is a position P121 in FIG. In this case, one vertex of the cube in which the input point is included is determined at the position P122 in FIG. 8 from the upper 4 bits of the input value. The coordinate value is (RH, GH, BH) = (0, 1, 0), and this position P122 is defined as the base point coordinate.

Hereinafter, the LUT access will be described separately when the input point belongs to each of the six tetrahedrons in the unit cube. In the illustrated example, the input position P121 is the data of “3, 4, 6, 7, 12, 13, 15, 16” determined by the base point P122 (0, 1, 0) in the data group of the three-dimensional LUT. It is contained in a unit cube surrounded by coordinate positions.
The arithmetic processing unit 4 uses the four basics corresponding to the processing target pixel from the basic data (lattice point data) of each vertex of the corresponding unit cube based on the spatial position P21 of the combination value of the upper 4-bit data. Extract data.

  For example, when it is determined that the input point belongs to the tetrahedron 1 constituted by the vertices shown in FIG. 9, the arithmetic processing unit 4 accesses the RG plane LUT (RG plane memory circuit 2RG) to obtain α1 and α1 ′. , Α2 and α2 ′, and RB plane LUT (RB plane memory circuit 2RB) are accessed to extract β1, β1 ′, β2 and β2 ′. The same value is extracted from the joint surface.

  Specifically, the arithmetic processing unit 4 calculates the access address ADRG to the RG plane LUT based on (RH, GH, BH) based on the base point A in Table 1 of FIG. Here, the access address ADRG is “1”, and the data group of the address 1 is extracted. Then, the arithmetic processing unit 4 has the 0th (3) and 1st (4) in the data group because the R-axis component of the base coordinate P122 (0, 1, 0) is “0” in the extracted data group. Is the desired basic data. Here, the 0th (3) basic data indicated by “address in the case of a two-dimensional address” shown at the bottom of the table in FIG. 9 is α1, and the first (4) basic data is α1 ′.

  On the RG plane, the address difference is always constant between α1 and α1 ′ and α2 and α2 ′. Therefore, when the arithmetic processing unit 4 specifies the access address ADRG for α1 and α1 ′ as described above, the arithmetic processing unit 4 calculates the access address ADRG for α2 and α2 ′ based on the addresses. Here, the access address ADRG is “2”, and the data group of the address 2 is extracted. Then, the arithmetic processing unit 4 has the 0th (6) and 1st (7) in the data group because the R-axis component of the base coordinate P122 (0, 1, 0) is “0” in the extracted data group. Is the desired basic data. Here, the 0th (6) basic data indicated by “address in the case of a two-dimensional address” shown at the bottom of the table in FIG. 9 is α2, and the first (7) basic data is α2 ′.

  Similarly, the arithmetic processing unit 4 calculates the access address ADRB to the RB plane LUT based on (RH, GH + 3, BH) based on Table 1 in FIG. Here, the access address ADRB is “6”, and the data group of the address 6 is extracted. Then, the arithmetic processing unit 4 has the 0th (6) and 1st (7) in the data group because the R-axis component of the base coordinate P122 (0, 1, 0) is “0” in the extracted data group. Is the desired basic data. Here, the 0th (6) basic data is β1, and the first (7) basic data is β1 ′.

  On the RB plane, address differences are always constant between β1 and β1 ′ and β2 and β2 ′. From this, the arithmetic processing unit 4 specifies the access address ADRB for β1 and β1 ′ as described above, and calculates the access address ADRB for β2 and β2 ′ based on the addresses. Here, the access address ADRB is “7”, and the data group of the address 7 is extracted. Then, the arithmetic processing unit 4 has the 0th (15) and 1st (16) in the data group because the R-axis component of the base coordinate P122 (0, 1, 0) is “0” in the extracted data group. Is the desired basic data. Here, the 0th (15) basic data indicated by “address in the case of a two-dimensional address” shown at the bottom of the table in FIG. 9 is β2, and the first (16) basic data is β2 ′.

  By doing so, the arithmetic processing unit 4 can identify α1, α1 ′, α2, α2 ′, β1, β1 ′, β2, and β2 ′, and therefore, the tetrahedron 1 is configured based on these 4 It is possible to extract point data, that is, desired four-point data necessary for tetrahedral interpolation calculation. In the case of the tetrahedron 1, the arithmetic processing unit 4 sets the four points of data as D1 = α1, D2 = α1 ′, D3 = β1 ′ or α2 ′, D4 = β2 ′, respectively.

  Even in the case of belonging to another tetrahedron, the arithmetic processing unit 4 calculates the access addresses ADRG and ADGB based on Table 1 in FIG. 6 and accesses the calculated two LUTs to extract a data group. From the extracted data group, two desired basic data according to the base point coordinates are extracted for every two LUTs.

For example, as illustrated in FIG. 10, when the input point belongs to the tetrahedron 2, the arithmetic processing unit 4 sets the access address ADRG of the RG plane LUT (RG plane memory circuit 2 RG) based on (RH, GH, BH + 3). Is calculated as “4”, and the 0th (12) basic data corresponding to the base point coordinate P122 (0, 1, 0) is extracted as α1, and the first (13) basic data is extracted as α1 ′. Furthermore, since the address difference between α1 and α1 ′ and α2 and α2 ′ is always constant, the access address ADRG for α2 and α2 ′ is calculated as “5”, and the base point coordinate P122 (0, 1, 0) is calculated. The 0th (12) basic data corresponding to) is α2, and the 1st (13) basic data is α2 ′.
Similarly, the arithmetic processing unit 4 calculates “3” based on the access address ADRB (RH, GH, BH) of the RB plane LUT (RB plane memory circuit 2RB), and the base point coordinate P122 (0, 1, 0). The first (3) basic data corresponding to is β1, and the second (4) basic data is β1 ′. Furthermore, since the address difference between β1 and β1 ′ and β2 and β2 ′ is always constant, the access address ADRB for β2 and β2 ′ is calculated as “4”, and the base point coordinates P122 (0, 1, 0) The 0th (12) basic data corresponding to is β2, and the first (13) basic data is β2 ′.

As shown in FIG. 11, when the input point belongs to the tetrahedron 3, the arithmetic processing unit 4 sets the access address ADRG of the RG plane LUT (RG plane memory circuit 2 RG) based on “RH, GH, BH + 3”. 4 ″ and the 0th (12) basic data corresponding to the base coordinate P122 (0, 1, 0) is extracted as α1, and the first (13) basic data is extracted as α1 ′. Furthermore, since the address difference between α1 and α1 ′ and α2 and α2 ′ is always constant, the access address ADRG for α2 and α2 ′ is calculated as “5”, and the base point coordinate P122 (0, 1, 0) is calculated. The 0th (15) basic data corresponding to) is α2, and the 1st (16) basic data is α2 ′.
Similarly, the arithmetic processing unit 4 calculates “3” based on the access address ADRB (RH, GH, BH) of the RB plane LUT (RB plane memory circuit 2RB), and the base point coordinate P122 (0, 1, 0). The first (3) basic data corresponding to is β1, and the second (4) basic data is β1 ′. Furthermore, since the address difference between β1 and β1 ′ and β2 and β2 ′ is always constant, the access address ADRB for β2 and β2 ′ is calculated as “4”, and the base point coordinates P122 (0, 1, 0) The 0th (12) basic data corresponding to is β2, and the first (13) basic data is β2 ′.

As shown in FIG. 12, when the input point belongs to the tetrahedron 4, the arithmetic processing unit 4 sets the access address ADRG of the RG plane LUT (RG plane memory circuit 2RG) based on (RH, GH, BH + 3). 4 ″ and the 0th (12) basic data corresponding to the base point coordinate P122 (0, 1, 0) is extracted as α1, and the first (13) basic data is extracted as α1 ′. Furthermore, since the address difference between α1 and α1 ′ and α2 and α2 ′ is always constant, the access address ADRG for α2 and α2 ′ is calculated as “5”, and the base point coordinate P122 (0, 1, 0) is calculated. The 0th (15) basic data corresponding to) is α2, and the 1st (16) basic data is α2 ′.
Similarly, the arithmetic processing unit 4 calculates “3” based on the access address ADRB (RH, GH, BH) of the RB plane LUT (RB plane memory circuit 2RB), and the base point coordinate P122 (0, 1, 0). The first (3) basic data corresponding to is β1, and the second (4) basic data is β1 ′. Furthermore, since the address difference between β1 and β1 ′ and β2 and β2 ′ is always constant, the access address ADRB for β2 and β2 ′ is calculated as “4”, and the base point coordinates P122 (0, 1, 0) The 0th (12) basic data corresponding to is β2, and the first (13) basic data is β2 ′.

As illustrated in FIG. 13, when the input point belongs to the tetrahedron 5, the arithmetic processing unit 4 sets the access address ADRG of the RG plane LUT (RG plane memory circuit 2 RG) based on (RH, GH, BH). 1 ″, and the 0th (3) basic data corresponding to the base point coordinate P122 (0, 1, 0) is extracted as α1, and the first (4) basic data is extracted as α1 ′. Furthermore, since the address difference between α1 and α1 ′ and α2 and α2 ′ is always constant, the access address ADRG for α2 and α2 ′ is calculated as “2”, and the base point coordinates P122 (0, 1, 0) ), The 0th (6) basic data corresponding to) is α2, and the first (7) basic data is α2 ′.
Similarly, the arithmetic processing unit 4 calculates “6” based on the access address ADRB (RH, GH + 3, BH) of the RB plane LUT (RB plane memory circuit 2RB), and the base point coordinate P122 (0, 1, 0). The first (6) basic data corresponding to is β1, and the second (7) basic data is β1 ′. Furthermore, since the address difference between β1 and β1 ′ and β2 and β2 ′ is always constant, the access address ADRB for β2 and β2 ′ is calculated as “7”, and the base point coordinates P122 (0, 1, 0) The 0th (15) basic data corresponding to is β2, and the first (16) basic data is β2 ′.

As shown in FIG. 14, when the input point belongs to the tetrahedron 6, the arithmetic processing unit 4 sets the access address ADRG of the RG plane LUT (RG plane memory circuit 2 RG) based on (RH, GH, BH). 1 ″, and the 0th (3) basic data corresponding to the base point coordinate P122 (0, 1, 0) is extracted as α1, and the first (4) basic data is extracted as α1 ′. Furthermore, since the address difference between α1 and α1 ′ and α2 and α2 ′ is always constant, the access address ADRG for α2 and α2 ′ is calculated as “2”, and the base point coordinates P122 (0, 1, 0) ), The 0th (6) basic data corresponding to) is α2, and the first (7) basic data is α2 ′.
Similarly, the arithmetic processing unit 4 calculates “6” based on the access address ADRB (RH, GH + 3, BH) of the RB plane LUT (RB plane memory circuit 2RB), and the base point coordinate P122 (0, 1, 0). The first (6) basic data corresponding to is β1, and the second (7) basic data is β1 ′. Furthermore, since the address difference between β1 and β1 ′ and β2 and β2 ′ is always constant, the access address ADRB for β2 and β2 ′ is calculated as “7”, and the base point coordinates P122 (0, 1, 0) The 0th (15) basic data corresponding to is β2, and the first (16) basic data is β2 ′.

  Table 2 shown in FIG. 15 is a diagram for explaining the interpolation coefficient calculation process (S102c) and the interpolation calculation process (S102d), which are the second stage of the output value calculation process (step S108 in FIG. 2) in the calculation processing unit 4. It is. Table 2 shows calculation formulas of interpolation coefficients required for the interpolation calculation by the tetra-hydra method. As can be seen from Table 2, the calculation formula is different for each of the six tetrahedrons.

  The arithmetic processing unit 4 receives the result of the tetrahedron determination process (steps S104 to S106 in FIG. 2), and uses it to calculate the interpolation coefficient according to the tetrahedron in which the input value is included based on Table 2 in FIG. In accordance with a calculation formula determined for each tetrahedron in which the input value is included, the interpolation coefficients W1, W2, and the interpolation coefficients W1, W2, and the lower bit data RL, GL, and BL constituting the tetrahedron are changed. W3 and W4 are calculated. This tetrahedral interpolation calculation process is the same as the process in the conventional data converter.

  Then, the arithmetic processing unit 4 uses a known four-point interpolation calculation to correspond to the interpolation coefficients W1, W2, W3, W4 thus obtained and the input points extracted by the first-stage four-grid point specifying process. Interpolation calculation processing is performed by the tetra-hydra method in which the final output value Dout is calculated based on the basic data (originally grid point data) D1, D2, D3, and D4 of the tetrahedron vertices. For example, the final output value Dout is calculated according to the following equation (1). In Expression (1), the output value is obtained by linear interpolation. However, the present invention is not limited to this, and a quadratic expression or other higher-order interpolation calculation expression may be used.

  Dout = D1 × W1 + D2 × W2 + D3 × W3 + D4 × W4 (1)

  According to the configuration of the first embodiment, when the output data corresponding to the input data is obtained by the tetrahedral interpolation calculation, the number of lattice point data holding memories (spaces) is required for the tetrahedral interpolation calculation. Since it is composed of two instead of four corresponding to the apex, as a result, it is not necessary to have four times the memory of the same data, so it can be doubled, so the total amount of memory required to achieve the same function is It becomes 1/2 of the conventional one.

  In other words, in contrast to the conventional case where it is necessary to provide memories (spaces) of the same capacity that can be independently driven as many as the number of interpolation calculation data, the number of grid point data and the number of memory spaces required for the interpolation calculation are the same. The same function is achieved, for example, in the case of 4-point interpolation, for example, in the case of 4-point interpolation, it is not necessary to have 4 times the memory for holding grid point data, and less than 4 times (for example, 2 times). Therefore, it is possible to reduce the total capacity of the memory required for this and the number of memory spaces that can be independently controlled. In addition, since the number of memory spaces for simultaneous access can be reduced, power consumption and radiation noise can be reduced.

  For example, conventionally, 17 × 17 × 17 pieces, that is, 4,193 bytes, are required to extract one interpolation calculation data. In the case of four-point interpolation, Four times, that is, 4913 bytes × 4 = 19,652 bytes were required. However, with the configuration of the present embodiment, it is possible to simultaneously extract data of four lattice points with a memory having a capacity of 1/2.

  Since the interpolation operation circuit can be used in the almost same configuration as the conventional configuration, the entire circuit is changed only around the memory circuit, so that the above configuration can be easily applied to the actual circuit.

[Second Embodiment]
FIG. 16 is a block diagram showing a second embodiment of the data conversion apparatus according to the present invention. The configuration of the second embodiment shows a first example of a specific circuit configuration in which the above-described interpolation calculation in the case of R, G, B three-dimensional input is performed at high speed in real time.

  As shown in the figure, the Y signal generation unit 4Y in the arithmetic processing unit 4 of the second embodiment performs unit cube determination processing (steps S100 to S102 in FIG. 2) and access memory specifying processing in the arithmetic processing unit 4 of the first embodiment. An address generation unit 10 that executes (S108a), a tetrahedron determination unit 14 that executes tetrahedron determination processing (S104 to S106), a data selection unit 16 that executes 4-lattice point specification processing (S108b), An interpolation coefficient generation unit 20 that executes interpolation coefficient calculation processing (S108c) and an interpolation processing unit 22 that executes interpolation calculation processing (S108d) are provided.

  The address generation unit 10 has both functions of a unit cell determination unit and an address setting unit of the present invention. The tetrahedron determining unit 14 is an example of a unit lattice determining unit of the present invention. The data selection unit 16 is an example of a basic data extraction unit of the present invention. Further, the interpolation coefficient generation unit 20 and the interpolation processing unit 22 constitute an interpolation calculation processing unit of the present invention.

  Although not shown in the figure, the M signal generation unit 4M, the C signal generation unit 4C, and the K signal generation unit 4K have the same configuration as the Y signal generation unit 4Y.

  When the image data R, G, and B are input, the address generator 10 converts the input data R, G, and B into upper bit data RH, GH, and BH (upper 4 bits in this example; collectively referred to as DH). And lower bit data RL, GL, BL (lower 4 bits in this example; collectively referred to as DL), and based on the upper 4 bits of data DH, shown in FIG. 5B and FIG. As described above, the position P22 (corresponding to the base point P122 in FIG. 8) where the input point in the three-dimensional LUT is included is specified, and coordinate information (RH, GH, BH) indicating the base point specifying the unit cube is specified. Is input to the data selection unit 16.

  The address generation unit 10 also inputs the lower bit data DL of the divided data to the tetrahedron determination unit 14 and the interpolation coefficient generation unit 20. The tetrahedron determination unit 14 specifies a tetrahedron including input values among the six tetrahedrons that divide the unit cube based on the lower-order bit data DL input from the address generation unit 10, and specifies the specified tetrahedron. Information indicating the body is input to the address generation unit 10, the data selection unit 16, and the interpolation coefficient generation unit 20 as a determination result.

  The address generation unit 10 receives the tetrahedron determination processing result by the tetrahedron determination unit 14, and in accordance with the selection conditions shown in Table 1 of FIG. 6, the basic data of the four grid points necessary for the interpolation calculation by the tetra-hydra method The read clock signal is controlled independently for the two memory circuits 2RG and 2RB to be extracted (specifically, the read clock to the read access read circuit is stopped). This is because simultaneous access to a large number of memories in a certain unit time leads to an increase in power consumption and an increase in radiation noise, and an improvement from the viewpoint of the environment is desired.

  That is, in the configuration of the present embodiment, the memory circuit including the basic data of the four lattice points necessary for the interpolation calculation, which should be simultaneously read and accessed for the pixel data to be processed, is two memory circuits. In addition to the effect of reducing power consumption and radiation noise due to the reduction from the conventional four, the power consumption and radiation noise are further reduced by stopping the supply of the read clock to the memory circuit that does not require simultaneous access. To reduce.

  Further, the address generation unit 10 determines the upper bit data RH, GH, BH for specifying the unit cube containing the input data, that is, the coordinate value of the base point P21 in FIG. 5B and the access address formula shown in Table 1 in FIG. The access addresses ADRG and ADRB calculated according to are set for each memory circuit to be accessed. Thus, when data is read from the memory circuit, only the memory circuit including the basic data of the four lattice points necessary for the interpolation operation by the tetra-hydra method becomes active among the two memory circuits 2RG and 2RB. A group of data is input to the data selection section 16 from the address set in the active memory circuit.

  For example, when one address is set as the memory circuits 2RG and 2RB, one that can output a plurality of corresponding data in parallel is used. For address input, access addresses ADRG and ADRB are set. For example, in each of (B) of FIGS. 3 to 9, by setting the value in the address field to the access address ADG, ADRB, the memory circuit 2RG, 2RB can change the base point coordinates (RH, GH, BH). All of the group of data including the two corresponding basic data are output in parallel.

  The address generation unit 10 controls the memory control signals CTRG and CTRB, which are inputs to the chip select terminal CS of each memory circuit, independently (specifically, switching to low / high), thereby enabling simultaneous reading. Two necessary memory circuits are made active, and one unnecessary memory circuit is made inactive (high impedance state). In this way, power consumption can be reduced, and the subsequent circuit of the memory circuit can be made compact.

  Next, the data selection unit 16 extracts necessary data from the data (lattice point data) of each vertex of the corresponding unit cube with the spatial position P21 of the combination value of the upper 4-bit data as a base point. For example, when the data selection unit 16 receives from the data storage unit 2 a data group of a predetermined address input from only a memory including basic data of four lattice points necessary for the interpolation calculation by the tetra-hydra method, the tetrahedron determination is performed. 4 lattice points required for the interpolation calculation by the tetra-hydra method based on the tetrahedron determination processing result by the unit 14 and the coordinate values (RH, GH, BH) of the base point including the input point from the address generation unit 10 Basic data D1, D2, D3, and D4 are extracted, and the extracted four data D1, D2, D3, and D4 are input to the interpolation processing unit 22.

  As can be seen from FIGS. 9 to 14, the data (α1, α1 ′, α2, α2 ′, β1, β1 ′, β2, β2 ′) output from the memory is any of D1, D2, D3, and D4. Corresponds to the tetrahedron to which the input point belongs. The data selection unit 16 obtains data (α1, α1 ′ and α2, α2 ′ and β1, β1 ′ and β2, β2 ′) from two memories corresponding to the input values as D1, D2, and D2 in the interpolation calculation process. Which of D3 and D4 is to be determined is determined according to the selection conditions shown in Table 1 of FIG. 6 based on the tetrahedron determination processing result by the tetrahedron determination unit 14.

  In parallel with this, the interpolation coefficient generation unit 20 receives the result of the tetrahedron determination processing by the tetrahedron determination unit 14 and, based on Table 2 in FIG. Interpolation coefficients W1, W2, W3, W4 are calculated based on the four lattice points constituting the tetrahedron and the lower bit data RL, GL, BL in accordance with a calculation formula corresponding to the body, and the calculated interpolation coefficients W1, W2 , W3, W4 are input to the interpolation processing unit 22.

  The interpolation processing unit 22 uses the well-known four-point interpolation calculation, the interpolation coefficients W1, W2, W3, W4 input from the interpolation coefficient generation unit 20 and the data D1, D2, D3 input from the data selection unit 16. Final output values Y, M, C, and K are calculated based on D4 (basic data of four vertices).

  According to the configuration of the second embodiment, when the tetra-hydra method is used when converting the digital color separation signal using the LUT and the interpolation operation into the digital color separation signal of other color components, What required four memories can implement tetrahedral interpolation calculation processing with two memories as in the first embodiment. Further, since the scale of the additional circuit for extracting desired basic data from the basic data is not so large, the data conversion apparatus 1 can be realized without increasing the scale or complexity of the interpolation circuit.

  In addition, conventionally, when extracting data used for the interpolation calculation, it is necessary to access four memories for calculating the output value of one color. According to the configuration of this embodiment, the chip select terminal of the memory is used. By controlling the CS (or the read enable terminal RE), the two memory circuits 2RG and 2RG are made active so that only two half of the conventional memories need to be accessed, reducing system power consumption and radiation noise. You can also

  That is, there is an effect that color data conversion can be realized with a small amount of memory resources when converting a digital color separation signal using an LUT and an interpolation operation into a digital color separation signal of another color component. Conventionally, when extracting data used for the interpolation calculation, it is necessary to simultaneously access four memories for the calculation of the output value of one color. However, in the configuration of the present embodiment, only two of the two are necessary. It also has the effect of reducing system power consumption and radiation noise.

[Third Embodiment]
FIG. 17 is a block diagram showing a third embodiment of the data conversion apparatus according to the present invention. The basic configuration of the third embodiment is the same as that of the second embodiment. The difference from the configuration of the second embodiment is that the data selection unit 16 of the second embodiment is not provided, and the function of the data selection unit 16 is configured to be shared by the address generation unit 10. That is, the address generation unit 10 of the third embodiment also has the function of the basic data extraction unit of the present invention.

  In response to this change, the tetrahedron determination unit 14 specifies a tetrahedron that includes input values from among the six tetrahedrons that divide the unit cube, based on the lower-order bit data DL input from the address generation unit 10. Then, the information indicating the specified tetrahedron is input to the address generation unit 10, the interpolation coefficient generation unit 20, and the interpolation processing unit 22 as a determination result. That is, the position of the unit cube that includes the input point in the three-dimensional LUT is specified, and the information is transmitted to the data selection unit 16.

  In addition, the memory circuits 2RG and 2RB of the third embodiment are not configured to output a group of all data for each address ADRG and ADRB set by the address generator 10 as packing data PRG and PRB. Any two addresses can be set, and those which can be output together are used.

  That is, as in the first and second embodiments, a plurality of grid point data are mapped for each address ADRG and ADRB. However, when reading, four grids are required for the interpolation calculation by the tetra-hydra method. Only two basic data (α1, α1 ′, α2, α2 ′, β1, β1 ′, or β2, β2 ′) are collectively output to the memory of each axis including the point.

  Specifically, an address space that can be controlled two-dimensionally is used, and access addresses ADRG and ADRB are set for one address axis in the same manner as in the first and second embodiments. For the other address axis, values corresponding to the base point coordinates (RH, GH, BH) for specifying the unit cube including the input value by the access address ADXRG, ADXRB for address setting in the X-axis direction 4 grid point specifying process is performed.

  For example, in each of (B) of FIGS. 3 to 9, the address field value is set to the access address ADRG, ADRB, and the base point coordinates of the “address in the case of a two-dimensional address” shown at the bottom of the data field A value (two consecutive addresses of 0, 1,...) Corresponding to (RH, GH, BH) is set as an access address ADXRG, ADXRB for address setting in the X-axis direction. In this way, two basic data corresponding to the base point coordinates (RH, GH, BH) are output in parallel from the memory circuits 2RG, 2RG, respectively.

  The interpolation processing unit 22 performs an interpolation operation on each of the two basic data (α1, α1 ′, α2, α2 ′, β1, β1 ′, β2, β2 ′) input from the two required memories corresponding to the input values. Which of D1, D2, D3, and D4 in the process should be determined is determined according to the selection condition shown in Table 1 of FIG. 6 based on the tetrahedron determination processing result by the tetrahedron determination unit 14. As can be seen from FIGS. 9 to 14, each of the two basic data (α1, α1 ′, α2, α2 ′, β1, β1 ′, β2, β2 ′) output from the memory is represented by D1, D2, This is because which of D3 and D4 corresponds to the tetrahedron to which the input point belongs.

  The interpolation processing unit 22 is input from the interpolation coefficients W1, W2, W3, and W4 input from the interpolation coefficient generation unit 20 and two necessary memories corresponding to the input values using a known four-point interpolation calculation. Based on the data D1, D2, D3, D4 corresponding to the two basic data (α1, α1 ′, α2, α2 ′, β1, β1 ′, β2, β2 ′), the final output values Y, M, C, Each K is calculated.

  According to the configuration of the third embodiment, although the configuration is different from that of the second embodiment, the basic operation is the same as that of the second embodiment. Therefore, in the same way as in the first embodiment, in addition to being able to implement tetrahedral interpolation calculation processing with two memories, by controlling the chip select terminal CS (or read enable terminal RE) of the memory, Power consumption and radiation noise can also be reduced.

  Note that the data storage unit 2, the address generation unit 10, the data selection unit 16, the interpolation calculation processing unit 22, and the like in the configuration described in the first to third embodiments may be realized by appropriately combining known techniques. Specifically, by using a hardware circuit such as a known latch circuit or selector circuit, the drive signals to the memory circuits 2RG and 2RB are controlled to read data from the memory circuits 2RG and 2RB (address and It is conceivable to control the timing. Thus, for example, in the first and second embodiments, all the basic data of the address including the basic data corresponding to the pixel data to be processed is read as packing data, and then the pixel data to be processed is supported. When extracting the basic data for the number of interpolation operation data to be performed, it is possible to realize a configuration in which all basic data at the target address is output from the memory circuit in parallel at almost the same time, or all basic data at the target address is time-sequentially And a “configuration for reading out only basic data necessary for interpolation calculation, and outputting these basic data in parallel at substantially the same time” in the third embodiment. It becomes possible.

  However, these configurations can be realized not by a hardware circuit but by execution of software. Furthermore, the above-described series of processing such as tetrahedron determination and interpolation calculation for memory access can be realized by either a hardware circuit or software. In the case of realization by software, it is conceivable that a program constituting the software is installed in advance in a data conversion device having a function as a computer. However, the program is connected to a wired or wireless communication line. Or may be provided via a computer-readable storage medium.

  Moreover, the above-described first to third embodiments are for describing preferred specific examples of the present invention, and the present invention is of course not limited thereto.

For example, in the above embodiment, as a memory for storing lattice point data, basic data in the direction common to the axis of input data is divided into a plurality of groups, and a plurality of data is mapped (packed) to one address, and the lump All the data (in the case of the first or second embodiment) or two basic data (in the case of the third embodiment) are read out in parallel, but the packing direction and reading method are as follows. The basic data in the directions of mutually orthogonal axes obtained by tilting the three input axes by 45 degrees may be divided into a plurality of groups and a plurality of data may be mapped (packed) to one address. . Even with such a packing method, it is possible to handle all the lattice point data of the original three-dimensional LUT. However, in this case, the most data on the axis passing through the origin is packed, and only one outermost data of the original three-dimensional LUT is packed, so that the same capacity memory can be used for each axis. However, since the number of associated data differs depending on the address, a memory space that is not actually used is generated. Further, the tilt is not limited to 45 degrees, and may be tilted to 60 degrees or any other angle. The tilt angle may be different depending on the axis. Even in these cases, all the lattice point data of the original three-dimensional LUT are handled by associating with the addresses so that all the lattice point data of the original three-dimensional LUT are included in any of the packed groups. It is preferable to make it. Furthermore, there may be a case where some lattice point data of the original three-dimensional LUT are not included in any of the packed groups. In addition, regarding the grid point data that does not pass through the axis among the grid point data of the original LUT, new data generated by, for example, linear interpolation may be assigned as basic data corresponding to the grid point data.
As in the first to third embodiments, if the basic data in the direction common to the axis of the input data is divided into a plurality of groups and a plurality of data is packed into one address, each packed address has It is possible to prevent an unused memory space from being associated with the same number of grid point data, and to handle all grid point data of the original three-dimensional LUT without omission, so that the same capacity of memory is wasted. The overall balance is good.

  In the first to third embodiments, a unit cube constituting a set of lattice point data used when converting input color data to output color data is divided into six tetrahedrons to obtain input values ( 4-point interpolation as a method of determining which tetrahedron the input pixel data) belongs to and determining an output value (pixel data for output) corresponding to the input value by interpolation within the corresponding tetrahedron However, the application of the present invention is not limited to 4-point interpolation, but is applied to other interpolation methods such as cubic interpolation (8-point interpolation) and 5-point interpolation. It is also possible. In other words, the memory of less than the number of interpolation calculation data (effectively less than the number of vertices that define the polyhedron) is used, and the lattice data of the original LUT is set in a predetermined direction (the surface is set according to the number of memories used). Are divided into groups, a plurality of grid point data are associated with one address for each group and stored in the memory, and interpolation processing is necessary for interpolation calculation from the grouped data group. Any configuration that extracts data of lattice points may be used.

In the first to third embodiments, three colors of R, G, and B are handled as k input color data, and converted into four colors of Y, M, C, and K as j color output color data. However, as long as there are three or more color components for each of the input system and the output system, it can be changed to a form that handles other color systems. Of course, any of RGB, Lab, YCbCr, YMCK, etc. can be handled without depending on the color space.
Furthermore, in the first to third embodiments, a k-dimensional hypercube formed by 2 k grid points in a k-dimensional hypercubic lattice space determined based on k (specifically, three) component data. The grid point data associated with each grid point is treated as the original LUT, and the unit grid shape is assumed to be a cube. However, the unit grid shape defined by each grid point is not necessarily It is not limited to a cube.
Furthermore, in the first to third embodiments, the unit lattice (unit cube) is internally divided by a polyhedron of the same capacity (specifically, tetrahedron), but the polyhedron that divides the unit lattice is: It does not necessarily have to be the same capacity.

  In addition to the tetrahedron, the polyhedron includes a pentahedron of a quadrangular pyramid, a hexahedron of a triangular prism or an oblique triangular prism as shown in FIG. That is, as described in the first to third embodiments, the k color is three colors, and the polyhedron is a tetrahedron corresponding to one color which is an output color signal element, and the interpolation calculation is a tetrahedron interpolation calculation. For example, when the k color is three colors, the polyhedron is a pentahedron of a quadrangular pyramid corresponding to one color that is an output color signal element, and the interpolation calculation is a quadrangular pyramid interpolation calculation. Or, if the k color is three colors and the polyhedron is a hexagonal hexahedron corresponding to one color which is an output color signal element, and the interpolation calculation is a triangular prism interpolation calculation, or the k color is three colors, Even in the case where the polyhedron is an oblique triangular prism hexahedron corresponding to one color as an output color signal element and the interpolation operation is an oblique triangular prism interpolation operation, the application of the present invention can be realized in exactly the same manner.

It is a block diagram which shows 1st Embodiment of the data converter which concerns on this invention. It is the flowchart which showed the outline | summary of the process sequence regarding the conversion of the color data in the data converter of 1st Embodiment. It is explanatory drawing which shows the look-up table for RG planes which comprises the grid point data which are the representative values of an output value. It is explanatory drawing which shows the look-up table for RB planes which comprises the grid point data which are the representative values of an output value. It is explanatory drawing which shows the unit cube determination process (S100-S102 of FIG. 2) in an arithmetic processing part. It is explanatory drawing which shows the tetrahedron determination process (S104-S106 of FIG. 2) in an arithmetic processing part. It is explanatory drawing which shows the access memory specific process (S108a of FIG. 2) and the 4-grid-point specific process (S108b of FIG. 2) in an arithmetic processing part. It is the figure which showed the positional relationship of input data and the data on 3D LUT space. It is explanatory drawing which shows the positional relationship of the input data which belongs to the tetrahedron 1, and the data on a three-dimensional LUT space. It is explanatory drawing which shows the positional relationship of the input data which belongs to the tetrahedron 2, and the data on a three-dimensional LUT space. It is explanatory drawing which shows the positional relationship of the input data which belongs to the tetrahedron 3, and the data on a three-dimensional LUT space. It is explanatory drawing which shows the positional relationship of the input data which belongs to the tetrahedron 4, and the data on a three-dimensional LUT space. It is explanatory drawing which shows the positional relationship of the input data which belongs to the tetrahedron 5, and the data on a three-dimensional LUT space. It is explanatory drawing which shows the positional relationship of the input data which belongs to the tetrahedron 6, and the data on a three-dimensional LUT space. It is explanatory drawing which shows the interpolation coefficient calculation process (S102c of FIG. 2) and the interpolation calculation process (S102d of FIG. 2) in a calculation process part. It is a block diagram which shows 2nd Embodiment of the data converter which concerns on this invention. It is a block diagram which shows 3rd Embodiment of the data converter which concerns on this invention. It is explanatory drawing which shows the example at the time of applying the hexahedron of a triangular prism.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Data converter, 2 ... Data storage part, 2R ... R axis memory circuit, 2G ... G axis memory circuit, 2B ... B axis memory circuit, 4 ... Arithmetic processing part, 4Y ... Y signal generation part, 4M ... M signal Generation unit, 4C ... C signal generation unit, 4K ... K signal generation unit, 10 ... address generation unit, 14 ... tetrahedron determination unit, 16 ... data selection unit, 20 ... interpolation coefficient generation unit, 22 ... interpolation processing unit

Claims (2)

Based on the grid point data used when converting the input color data to the output color data, for each pixel data of the input color data, the pixel data is any one of the unit grids constituting the set of grid point data. A unit cell body determination unit for determining whether to belong,
A polyhedron determining unit that further divides the corresponding unit grid determined by the unit grid determining unit into a plurality of polyhedrons and determines to which polyhedron the pixel data belongs;
An interpolation calculation processing unit that determines pixel data for output corresponding to the input pixel data by interpolation calculation in the corresponding polyhedron determined by the polyhedron determination unit;
Each grid in a k-dimensional grid space defined by k input color signal elements is provided with a plurality of independently controllable memory spaces smaller than the number of interpolation operation data defined according to the polyhedron. The basic data corresponding to the grid point data associated with the points is stored, the basic data is divided into a plurality of groups according to a predetermined standard, and for each group, the plurality of basic data in the group is A data storage for storing in a corresponding one of a plurality of memory spaces;
From the plurality of basic data associated with the group stored in the data storage unit, basic data corresponding to the number of interpolation operation data corresponding to the pixel data to be processed is extracted, and this extracted A basic data extraction unit that uses basic data for the number of interpolation calculation data as basic data used when the interpolation calculation processing unit performs interpolation calculation within the polyhedron, and
The plurality of groups are grouped so that each of them forms an independent plane according to the growth direction of basic data belonging to the group. Based on the grid point data used when converting the input color data to the output color data, for each pixel data of the input color data, the pixel data is any one of the unit grids constituting the set of grid point data. To determine whether the pixel data belongs to the polyhedron by dividing the corresponding unit lattice into a plurality of polyhedrons, and input by interpolation operation in the corresponding polyhedron A data conversion method for determining output pixel data corresponding to the pixel data,
Using a memory space that is independently controllable in a number smaller than the number of data for interpolation calculation prescribed according to the polyhedron,
Basic data corresponding to the lattice point data associated with each lattice point of the k-dimensional lattice space defined by the k-color input color signal elements is divided into a plurality of groups according to a predetermined standard. Storing a plurality of the basic data in a group in corresponding ones of the plurality of memory spaces;
From the plurality of basic data associated with the group, basic data for the number of interpolation arithmetic data corresponding to the pixel data to be processed is extracted, and the basic data for the number of interpolation arithmetic data extracted. And performing an interpolation operation in the polyhedron,
The data conversion method, wherein the plurality of groups are grouped so that each of them forms an independent plane according to a difference in growth direction of basic data belonging to the group.

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