JP2005148425A - Display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To apply the invention to a liquid crystal display device which, for example, has each pixel composed of multiple subpixels and represent gradations by driving multiple subpixels and to realize higher gradations and higher resolution of a multi-bit memory type display device by simplifying the layout of pixel circuits and electrodes constituting subpixels and easily realizing multi-bit constitution. <P>SOLUTION: In an area wherein circuits 44A to 44E of respective subpixels are arranged, a memory circuit and a switch circuit are arranged at both end sides, an area AR for electrode connection is formed in the center of the area, and those circuits 44A to 44E and electrodes are connected in the area AR for electrode connection. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a display device, and can be applied to, for example, a liquid crystal display device in which one pixel is constituted by a plurality of sub-pixels and gradation is expressed by driving the plurality of sub-pixels. According to the present invention, in the region where the circuit of each subpixel is arranged, the memory circuit and the switch circuit are arranged on both ends, respectively, and an electrode connection region is formed in the center of this region. By connecting these circuits and electrodes, in a display device using a multi-bit memory system, the layout of pixel circuits and electrodes constituting sub-pixels is simplified, and the number of bits is easily increased to increase the gradation and resolution. To be able to.

  Conventionally, in a liquid crystal display device, a display unit in which pixels are arranged in a matrix is driven by a drive circuit to display a desired image. The frame rate control gradation method is applied.

  In contrast to such a driving method, in a liquid crystal display device, as disclosed in, for example, Japanese Patent Laid-Open No. 6-138844, one pixel is formed by a plurality of sub-pixels whose area is gradually increased by approximately twice. A so-called area gray scale method is also proposed in which the display area or non-display of these sub-pixels is controlled to change the area of a region used for display and thereby change the gray scale of each pixel. . In the case of this method, the driving of each sub-pixel is a simple display / non-display control by binary, so that the corresponding sub-pixel is driven by the logical value of each bit of the input data to be displayed. It is considered that the configuration of the drive circuit can be simplified. Further, as proposed in, for example, Japanese Patent Laid-Open No. 9-243959, etc., each subpixel is provided with a memory, and each subpixel is driven by recording in this memory, thereby greatly reducing the power consumption of the drive circuit. I think it can be done. Hereinafter, such an area gray scale method in which a memory is provided for each pixel is referred to as a multi-bit memory method.

  That is, FIG. 7 is a block diagram showing a configuration studied by the applicant of the present application for the liquid crystal display device using the multi-bit memory system. The liquid crystal display device 1 has a configuration using a voltage gradation method liquid crystal display device, and the display portion of the voltage gradation method liquid crystal display device is configured by pixels of a multi-bit memory system, and the configuration of the pixel The configuration of the horizontal drive circuit is changed to correspond to the above.

  That is, in this liquid crystal display device 1, the display unit 2 is a so-called reflective liquid crystal display panel, and is formed by arranging pixels provided with red, green, and blue color filters in a matrix. Here, as shown in FIG. 8 showing the configuration of one pixel 2A of the display unit 2, each pixel 2A has an area of electrodes 3A, 3B, 3C, 3D, and 3E serving as a display area of 1: 2: 4. : Formed of a plurality of sub-pixels 2AA to 2AE set to 8:16. Here, the sub-pixels 2AA to 2AE are formed in the same manner except that the areas of the electrodes 3A to 3E are set in a certain proportional relationship, and the electrodes 3A to 3A are respectively formed by the pixel circuits 4A to 4E shown in FIG. The liquid crystal cells 5A to 5E by ˜3E are driven.

  That is, the pixel circuits 4A to 4E include an N-channel MOS (hereinafter referred to as NMOS) transistor Q1 and a P-channel MOS whose gates and drains are commonly connected, as shown in the block diagram of the connection diagram of FIG. Similarly, a CMOS inverter 6 composed of a transistor Q2 (hereinafter referred to as PMOS) and a CMOS inverter 7 composed of an NMOS transistor Q3 and a PMOS transistor Q4, whose gates and drains are connected in common, are connected to the positive power supply line VEE and the negative power supply line VEE. The CMOS inverters 6 and 7 are connected in parallel with the side power supply line VSS, and a memory having an SRAM (Static Random Access Memory) configuration is formed.

  In the pixel circuits 4A to 4E, a switch circuit 8 for connecting the signal line SIG to the CMOS inverters 6 and 7 by the NMOS transistor Q5 and supplying the signal level of the signal line SIG to the memory is formed, and as shown in FIG. In addition, the data by the signal line SIG (FIG. 11A) is set in the memory by the control of the NMOS transistor Q5 by the gate signal GATE (FIG. 11B) (FIG. 11C). Here, V1 is the potential on the input side of the inverter 6 which is the input side by the switch circuit 8.

  The pixel circuits 4A to 4E correspond to the common voltage VCOM (FIG. 11 (G)) applied to the common electrodes of the liquid crystal cells 5A (5B to 5E) in accordance with the data thus stored in the memory. The in-phase drive signal FRP (FIG. 11D) or the reverse-phase drive signal XFRP (FIG. 11E) is selected and applied to the liquid crystal cells 5A (5B to 5E), whereby the liquid crystal cell 5A (5B) is selected. ~ 5E). That is, the pixel circuits 4A to 4E control on / off of the switch circuit 9 composed of the NMOS transistor Q6 and the PMOS transistor Q7 by the output of the inverter 7, and the drive signal XFRP having a phase opposite to the common potential VCOM is transmitted through the switch circuit 9 to the liquid crystal cell. Apply to 5A (5B-5E). Further, the switch circuit 10 comprising the same NMOS transistor Q8 and PMOS transistor Q9 is controlled to be turned on and off by the output of the inverter 6, and the drive signal FRP having the same phase as the common potential VCOM is supplied to the liquid crystal cell 5A (5B to 5E) via the switch circuit 10. Apply to.

  As a result, as shown in FIG. 11, when the potential of the signal line SIG is switched, the voltage V5 (FIG. 11 (F)) applied to the liquid crystal cell 5A (5B to 5E) from the time t1 when the subsequent gate signal GATE rises. Is switched from the same phase to the opposite phase with respect to the common potential VCOM, and the display and non-display of the liquid crystal cell 5A (5B to 5E) can be switched. The example shown in FIG. 11 is a case of so-called normally black.

  For the display unit 2 configured as described above, the DC-DC converter 12 operates in accordance with the reference signal DDCV output from the timing generator 14, from the power supply VDD input from the outside to the power supply VDD2 for operation, etc. Is generated and output.

  The interface (IF) 13 is provided with gradation data R [5-1] and G [5-1] indicating the gradation of each of the red, green, and blue pixels that are simultaneously input to the liquid crystal display device 1 in parallel. , B [5-1], the master clock MCK (MCK5) synchronized with the gradation data R [5-1], G [5-1], B [5-1], and the horizontal synchronization signal HSYNC ( HD), vertical synchronization signal VSYNC (VD), and the like are input and output to the timing generator 14. The timing generator 14 generates various reference signals necessary for the operation of each unit based on the input signal from the interface 13. Output.

  The vertical drive circuit 16 generates a gate signal for selecting the pixels 2A of the display unit 2 in units of lines based on the reference signal generated by the timing generator 14, and outputs the gate signal to the gate line GATE. Here, in FIG. 7, symbols GP1, GP2, and GP3 attached to the gate line GATE are symbols indicating groups of pixels 2A arranged in the horizontal direction.

  On the other hand, the horizontal driving circuit 20 samples the corresponding bits of the gradation data R [5-1], G [5-1], and B [5-1] that are sequentially input, and corresponding signal lines SIG. The pixel 2A selected by the vertical drive circuit 16 is driven by the signal line SIG.

  Accordingly, in the liquid crystal display device 1, in the horizontal drive circuit 20, each of the gradation data R [5-1], G [5-1], and B [5-1] corresponding to the sub-pixels 2AA to 2AE is obtained. Since it is only necessary to sample and output the bits, the configuration of the driving circuit can be simplified as compared with a liquid crystal display device or the like based on the voltage gradation method. In addition, it is possible to display a still image by simply stopping the operation of the vertical drive circuit and the horizontal drive circuit and continuing to supply the drive signals FRP and XFRP, thereby reducing the power consumption as compared with a liquid crystal display device using a voltage gradation method. Can also be reduced.

  However, when the display unit 2 is simply formed by the pixels 2A based on the multi-bit memory system in this way, the layout of the pixel circuits 4A to 4E and the electrodes 3A to 3E becomes complicated, thereby increasing the gradation and increasing the number of bits. There is a problem that resolution is difficult.

That is, it is desirable that each of the pixel circuits 4A to 4E is configured in the same manner, so that each of the pixel circuits 4A to 4E is created with the same layout. It is possible to easily cope with a design change related to a change in the number of bits. However, in each of the sub-pixels 2A to 2E, the size of the electrodes 3A to 3E to be driven is greatly different, and the change in size becomes more severe as the number of bits increases. Specifically, when the pixel circuits 4A to 4E are simply created with the same layout, the connection between the pixel circuits 4A to 4E and the corresponding electrodes 3A to 3E intersects between the adjacent pixels 2AA to 2AE. These connections become complicated.
JP-A-6-138844 Japanese Patent Laid-Open No. 9-243995

  The present invention has been made in consideration of the above points. In a display device using a multi-bit memory method, the layout of pixel circuits and electrodes constituting sub-pixels is simplified, and the number of bits is easily increased to increase the gradation and increase the number of bits. The present invention intends to propose a display device capable of achieving a resolution.

  In order to solve such a problem, in the first aspect of the present invention, a display unit in which pixels are arranged in a matrix, a vertical drive circuit for sequentially selecting pixels by gate lines, and gradation data for instructing the gradation of the pixels In accordance with a display device having a horizontal drive circuit that outputs a drive signal for a pixel selected by a vertical drive circuit, an area allocated to one pixel is equally divided in a direction along a signal line. Each pixel circuit area is formed with a memory circuit, a drive signal switch circuit, and a signal line switch circuit arranged in the same manner, and each of the pixel circuit areas is provided with a memory circuit and a drive signal switch circuit. A region for connection to the electrode of the part to be used for display is formed between the memory circuit and the drive signal switch circuit provided at both ends, and the region for connection is used for display. Wiring for outputting a drive signal to the position of the electrodes is made to be connected.

  According to the configuration of claim 1, a region of a pixel circuit in which a region assigned to one pixel is equally divided in a direction along the signal line and a pixel circuit is provided is formed. The region of each pixel circuit includes a memory circuit, The drive signal switch circuit and the signal line switch circuit are arranged in the same manner, and the memory circuit and the drive signal switch circuit are provided at both ends, respectively, for display between the memory circuit and the drive signal switch circuit. If a region for connection to the electrode of the part is formed, and wiring for outputting a drive signal is connected to the electrode of the part for display in the region for connection, each pixel circuit is laid out in the same layout. Further, it is possible to secure a high degree of freedom with respect to the connection with the drive signal wiring while avoiding the corners of the electrode at the site for display. This effectively avoids various problems caused by connecting at the corners of the electrodes, and even when the size of the electrodes is significantly different from the area of these pixel circuits, it can easily correspond to the pixel circuits. It is possible to connect the electrodes to be connected, and it is possible to easily cope with a change in the number of bits. Accordingly, in a display device using a multi-bit memory system, the layout of pixel circuits and electrodes constituting sub-pixels can be simplified, and the number of bits can be easily increased to achieve higher gradation and higher resolution.

  According to the present invention, in a display device using a multi-bit memory system, the layout of pixel circuits and electrodes constituting sub-pixels can be simplified, and the number of bits can be easily increased to achieve higher gradation and higher resolution.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings as appropriate.

(1) Configuration of Example (1-1) Overall Configuration FIG. 2 is a block diagram showing a liquid crystal display device according to this example. In this liquid crystal display device 31, a display unit 32, a vertical drive circuit 33, a horizontal drive circuit 34, a timing generator (TG) 35, an interface (IF) 36, and a DC-DC converter (DDC) 37 are integrated on a glass substrate. The color image is displayed on the display unit 32. For this reason, in this liquid crystal display device 31, red, green, and blue gradation data R [5-1], G [5-1], and B [5] with 5 bits each indicating the gradation of each pixel to be displayed. -1] are input simultaneously in parallel in the raster scanning order.

  In this liquid crystal display device 31, the display unit 32 is formed by a so-called vertical stripe type reflective liquid crystal display panel in which color filters of the same color extend in the vertical direction and sequentially circulate in the horizontal direction. The color filter related to the stripe is formed by three colors corresponding to the image data R [5-1], G [5-1], and B [5-1].

  Further, the display unit 32 is formed by arranging pixels provided with such color filters in a matrix form of N × M pixels in the horizontal direction and the vertical direction, and each pixel is formed by a pixel using a multi-bit memory system. It is made to be done.

  That is, in each pixel 32A, as shown in FIG. 3 in comparison with FIG. 8, the areas of the electrodes 43A, 43B, 43C, 43D, and 43E, which are parts used for display, change approximately by a factor of two. The sub-pixels 32AA to 32AE are provided with pixel circuits 44A to 44E having the same configuration.

  Here, the pixel circuits 44 </ b> A to 44 </ b> E are formed in the same manner as the pixel circuits 4 </ b> A to 4 </ b> E described above with reference to FIGS. 9 and 10 except that the signal line SIG is shared. In the unit 32, as the number of signal lines is reduced, the number of signal lines can be easily increased to increase the number of bits to increase the gradation and resolution.

  Thus, in each pixel 32A, the memory of the inverters 6 and 7 that acquires and holds the signal level of the signal line SIG by the MOS transistor and the memory of the signal line SIG in response to the gate signals GATE1 to GATE5 in each pixel 32A. The switch circuit 8 that supplies the signal level and the in-phase or anti-phase drive signals FRP and XFRP with respect to the common voltage VCOM applied to one electrode of the portion to be displayed are selected according to the memory holding result and displayed. Switch circuits 9 and 10 to be applied to the other electrodes 43A to 43E of the portions to be provided are provided in the sub-pixels 32AA to 32AE, respectively.

  In this way, in the liquid crystal display device 31, the signal lines SIG for the sub-pixels 32AA to 32AE are driven in a time-sharing manner as the signal lines SIG are shared by the sub-pixels 32AA to 32AE.

  That is, the horizontal drive circuit 34 sequentially obtains gradation data R [5-1], G [5-1], and B [5-1] that are sequentially input, thereby sequentially obtaining the gradation data R [5-1]. 5-1], G [5-1], and B [5-1] are grouped in units of lines, and then the gradation data R [5-1] are sequentially arranged in the order corresponding to the arrangement of the sub-pixels 32AA to 32AE. ], G [5-1], and B [5-1] are selected and output, so that the grayscale data R [5-1] corresponding to the signal line SIG common to the sub-pixels 32AA to 32AE by time division. ], G [5-1], and B [5-1]. Thus, in this embodiment, each pixel extending in the vertical direction is driven by time division, and further, sub-pixels in each pixel are driven by time division.

  Corresponding to the serial transfer of each gradation data by the horizontal drive circuit 34, the vertical drive circuit 33 sequentially selects the pixels 32A by the gate lines. In selecting each pixel 32A, the sub pixels 32AA to 32AE are sequentially selected by the gate lines connected to the sub pixels 32AA to 32AE.

  The DC-DC converter 37 operates in accordance with the reference signal DDCV output from the timing generator 35, and generates and outputs a power supply VDD2 for operation from the power supply VDD input from the outside.

  The interface (IF) 36 has gradation data R [5-1] and G [5-1] indicating the gradation of each of the red, green, and blue pixels that are simultaneously input to the liquid crystal display device 31. , B [5-1], the master clock MCK (MCK5) synchronized with the gradation data R [5-1], G [5-1], B [5-1], and the horizontal synchronization signal HSYNC ( HD), vertical synchronization signal VSYNC (VD), and the like are input and output to the timing generator 35. The timing generator 35 generates various reference signals necessary for the operation of each unit based on the input signal from the interface 36. Output.

(1-2) Pixel Layout FIG. 4 is a plan view showing a configuration of one pixel 32A of the liquid crystal display device 31. As shown in FIG. The display section 32 of the liquid crystal display device 31 is formed by arranging the pixels 32A in a matrix. Here, the display unit 32 is configured so that a substantially square area is assigned to three consecutive pixels in the horizontal direction according to the combination of the red, green, and blue pixels 32A. An oblong rectangular area having an aspect ratio of approximately 3: 1 is assigned.

  Each pixel 32A is formed with a signal line extending in the longitudinal direction, and the rectangular region is equally divided by the number of bits in the extending direction of the signal line to form pixel circuits 44A to 44E. An area to be formed (hereinafter referred to as a pixel circuit area) is formed.

  Each pixel 32A has a pixel circuit region formed in this way and extends in the vertical direction so that the lowest side becomes the center side, and the two adjacent regions on the center side have two lower sides 2 respectively. Bit pixel circuits are assigned. Further, in the area outside the area where the lower-order 2-bit pixel circuit is assigned, the upper-order 2-bit pixel circuit is assigned according to the number of remaining bits. Further, pixel circuits of remaining bits are allocated to these outer regions in accordance with the allocation of the upper 2 bits.

  That is, in the example shown in FIG. 4, since the gradation data is 5 bits, the pixel circuit 44A of the least significant bit is assigned to the central area, and the area adjacent to the area to which this pixel circuit 44A is assigned. The succeeding higher-order bit pixel circuit 44B is assigned to (in this example, the upper region). In addition, a pixel circuit 44E corresponding to the most significant bit is assigned to the upper region of the region to which the lowest pixel circuit 44B is assigned. On the contrary, the lower side of the region to which the pixel circuit 44A is assigned. The pixel circuit 44D of the second bit on the upper side is assigned to this area. The remaining upper bit pixel circuit 44C is assigned to the lower region to which the pixel circuit 44D is assigned.

  Thus, in this embodiment, the center of gravity of the display area related to each of the sub-pixels 32AA to 32AE is arranged as close as possible to the center of gravity of the display area related to each pixel 32A in the longitudinal direction. In addition, a smaller area electrode and a smaller area electrode are combined to form a smaller area electrode in a square shape, and a larger area electrode is deformed into a rectangular shape to correspond to this smaller area electrode. As a result, electrodes having greatly different areas are efficiently arranged to ensure gradation with high accuracy.

  Thus, with respect to the allocation of the pixel circuits 44A to 44E related to the sub pixels 32AA to 32AE, the sub pixels 32AA to 32AE driven by the pixel circuits 44A to 44E have corresponding electrodes 43A to 43E as a whole. Are formed so as to be deviated from the raster scanning start side by approximately ¼ side pitch, so that the pixel circuits 44A to 44E can be connected to the corresponding electrodes 43A to 43E with a high degree of freedom in the connection area AR described later. Yes.

  Specifically, these electrodes 43A to 43E are sequentially provided so as to correspond to the pixel circuits 44A to 44E. In addition, the area assigned to the pixel 32A by these electrodes 43A to 43E (the area having the same shape as the vertically long area to which the pixel circuits 44A to 44E are assigned) is the area ratio 16: 8: 4 of each electrode 43A to 43E. : For the area of each electrode 43A to 43E calculated by dividing by 2: 1, when each electrode 43A to 43E is formed in a square shape and the length of one side is shorter than a predetermined value, this electrode has a square shape Is formed along the side opposite to the side where the electrodes 43A to 43E are biased, that is, on the side of the connection region AR described later.

  On the contrary, when the length of the electrode set in the square shape is longer than the predetermined value, in principle, the rectangular shape having the short side of the region assigned to the pixel 32A as one side. A region is assigned to this sub-pixel. Further, at this time, when a rectangular electrode is allocated adjacent to the inside, the electrode is allocated to the rectangular shape so as to extend to the remaining portion, that is, the electrode is formed by an L-shape partially protruding inward. It is formed.

  Thus, in the example of FIG. 4, the electrodes 43A and 43B to which the least significant 2 bits are assigned are formed in a square shape and are formed on the end side in the horizontal scanning direction. Yes. Further, the outermost 2-bit electrodes 43E and 43D on the outer side are formed in an L shape that partially protrudes toward the electrodes 43B and 43A, respectively. Further, the remaining electrode 43C is formed in a rectangular shape in which the short side of the region assigned to the pixel 32A is one side.

  As a result, in this embodiment, even for sub-pixels having a small area for display, variations due to etching or the like can be prevented, and each sub-pixel can be created while ensuring desired accuracy.

  Further, in this way, the shape of the region used for display related to each of the sub-pixels 32AA to 32AE is set, and in this display unit 32, the region used for each display is rounded to a predetermined size, and this is also used for etching. Variations due to processing or the like are prevented, and a desired accuracy can be ensured to create a sub-pixel.

  In practice, in the display section 32, the electrodes 43A to 43E are set and rounded in this way, and further, gaps necessary for insulation are set between the electrodes 43A to 43E, and each of these changes. The shape of each of the electrodes 32AA to 32AE is finely adjusted so that the area of the electrodes 32AA to 32AE finally becomes 16: 8: 4: 2: 1 as described above.

  In this manner, each of the pixel circuits 44A to 44E assigned to the region of the pixel 32A is configured by the transistors Q1 to Q9 described above with reference to FIG. 9, and is laid out as shown in FIG. That is, when the pixel circuits 44A to 44E form the gate electrodes (indicated by reference sign G in FIG. 1) of the MOS transistors Q1 to Q9, the gate line GATE is formed along the upper end of each region together with the gate electrode material. Provided. Further, when the gate line GATE is formed, the wiring patterns L1 and L2 for connecting the inverters 6 and 7 by the transistors Q1 to Q4 to the switch circuits 9 and 10 by the transistors Q6 to Q9 together with the gate electrode material are connected to the gate line GATE. Is formed in parallel with the gate line GATE so that the remaining region is divided into approximately three equal parts.

  In the pixel circuits 44A to 44E, transistors Q1 to Q4 are formed on the left end side of these wiring patterns L1 and L2, inverters 6 and 7 are formed, and transistors Q6 to Q9 are formed on the right end side to form the switch circuit 9. 10 are formed. That is, in the pixel circuits 44A to 44E, of the transistors Q1 and Q2 whose gates are connected to the signal line SIG, the transistor Q2 whose source is connected to the positive power supply VDD is formed on the left end side of the lower wiring pattern L2, and the remaining transistors Q1 is formed inside thereof. Of the remaining transistors Q3 and Q4 of the inverter 7, the transistor Q4 whose source is connected to the positive power supply VDD is formed on the left end side of the central wiring pattern L1, and the remaining transistor Q3 is formed inside thereof. The pixel circuits 44A to 44E include a wiring pattern L3 that connects the transistors Q2 and Q4 to the positive power supply VDD, a wiring pattern L4 that connects the transistors Q1 and Q3 to the negative power supply VSS, and transistors Q3 and Q4 that are connected to the transistor Q5 by the switch circuit 8. A wiring pattern L5 for connecting to the transistors Q1 and Q2 and a wiring pattern L6 for connecting the sources of the transistors Q1 and Q2 to the gates of the transistors Q3 and Q4 are formed following the transistors Q1 to Q4, thereby creating an inverter.

  In the pixel circuits 44A to 44E, the gate line GATE locally extends downward to form the transistor Q5 of the switch circuit 8 that connects the signal line SIG to the inverters 6 and 7. The transistor Q5 is connected to the signal line SIG. The connection wiring pattern L7 is formed.

  Further, transistors Q8 and Q9 of the switch circuit 10 related to the drive signal FRP having the same phase as the common voltage VCOM are formed on the right ends of the wiring patterns L1 and L2, respectively, and an electrode L9 for inputting the drive signal FRP to these transistors Q8 and Q9. , L11 is formed. Further, transistors Q6 and Q7 of the switch circuit 9 related to the drive signal XFRP having a phase opposite to that of the common voltage VCOM are formed inside the transistors Q8 and Q9, and electrodes L10 for inputting the drive signal XFRP to the transistors Q8 and Q9, L8 is formed. In addition, an electrode LX that connects these transistors Q6 to Q9 to the electrodes 43A to 43E of the liquid crystal cell is formed.

  Accordingly, in the pixel circuits 44A to 44E, in this horizontally long region in which the pixel circuits 44A to 44E of the sub-pixels 32AA to 32AE are arranged, a memory circuit (6, 7) for recording a logical value by the signal line SIG, In order to connect the switch circuits 9 and 10 to the electrodes 43A to 43E in the center of this region, the switch circuits 9 and 10 for switching the driving signal to the liquid crystal cell according to the contents of the memory circuit are arranged at both left and right ends of this region. The region AR is formed, and the switch circuits 9 and 10 are connected to the electrodes 43A to 43E in this connection region AR. Thereby, in this embodiment, the layout of the pixel circuits 44A to 44E and the electrodes 43A to 43E constituting the sub-pixels 32A to 32E can be simplified, and the number of bits can be easily increased to increase the gradation and the resolution. Has been made.

  In FIG. 1 and FIG. 5 etc., a circle with a black dot on the inside is a mark indicating a connection point with a wiring pattern formed on the upper layer side, and a circle with an x on the inside is a lower layer side It is a mark which shows a connection location with this wiring pattern.

  That is, as shown in FIG. 5, in such pixel circuits 44A to 44E, a wiring pattern as shown in FIG. 5 is formed on the upper layer side. Here, these wiring patterns are formed so that the signal lines SIG extending from the horizontal drive circuit 34 extend in the vertical direction, and in parallel with the signal lines SIG, wiring patterns of the positive power supply VDD and the negative power supply VSS, Wiring patterns for the drive signals FRP and XFRP are provided.

  Among these wiring patterns, the wiring patterns of the drive signals FRP and XFRP, and the wiring patterns of the positive power supply VDD and the negative power supply VSS are respectively formed in the corresponding wiring pattern portions in the lower layer. The signal line SIG is formed so as to avoid the electrode connection region AR, and the pixel circuits 44A to 44E are arranged in the connection region AR in these wiring pattern layers as shown in FIG. A wiring pattern LX1 for connecting the wiring pattern LX for electrode connection to the subsequent upper layer electrodes 43A to 43E is formed.

  That is, in this manner, the transistors and the like are laid out in the same manner in the pixel circuits 44A to 44E, and in the pixel circuit 44E that is the most significant bit, the switch circuits of the transistors Q6 to Q9 are connected to the electrodes 43A to 43E of the liquid crystal cells. The electrode LX extends to the connection region AR, and in this connection region AR, the electrode LX is connected to the corresponding electrode 43E via the connection wiring pattern LX1 provided in the layer related to the wiring pattern such as the signal line SIG. Is done. On the other hand, in the electrode LX of the pixel circuit 44B that continues, the adjacent pixel circuit 44E that extends to the connection area AR and is bent substantially at a right angle and provided with the corresponding electrode 43B is provided in the connection area AR. Extending to the region AR, and connected to the corresponding electrode 43B via a connection wiring pattern LX1 provided in the region AR of the adjacent pixel circuit 44E.

  Similarly, the subsequent electrode LX of the pixel circuit 44A extends to the connection region AR, and in this connection region AR, is bent substantially at a right angle up to a portion in the region AR where the corresponding electrode 43A is provided. It is extended and connected to the corresponding electrode 43A via the connection wiring pattern LX1 provided in this part. The subsequent electrodes LX of the pixel circuits 44D and 44B extend to the connection region AR and are connected to the corresponding electrodes 43D and 43B via the connection wiring pattern LX1 provided in the connection region AR. The

  Accordingly, in the liquid crystal display device 31, each pixel circuit created with the same layout is used for the electrodes 43A to 43E having a large area by effectively using the connection area AR thus created. 44A to 44E can be connected easily and reliably.

  In this way, when the pixel circuits 44A to 44E corresponding to the electrodes 43A to 43E are connected, in each pixel 32A, the connection portions of the wiring pattern LX1 with respect to the electrodes 43A to 43E are not overlapped when viewed from the vertical direction. These are arranged so as to be irregularly different in the horizontal direction, so that such connection portions are arranged in a row, thereby effectively avoiding the generation of various interference fringes.

(2) Operation of Embodiment In the above configuration, in this liquid crystal display device 31 (FIG. 2), 5-bit gradation data for instructing the gradation of each pixel in red, green, and blue from the drawing controller or the like, respectively. R [5-1], G [5-1], and B [5-1] are sequentially and simultaneously input in the order of raster scanning, and the gradation data R [5-1], G [5-1], B [5-1] is sequentially sampled by the horizontal drive circuit 34 and collected in line units of the display unit 32. Further, the bits of the gradation data R [5-1], G [5-1], and B [5-1], which are collected in units of lines as described above, are sequentially and cyclically selected, and each bit is serially transferred. The signal is output to one signal line SIG in the pixel 32A (FIG. 3).

  In addition, a selection signal for sequentially selecting each line of the display unit 32 is cyclically generated by the vertical drive circuit 33 so as to correspond to the line unit processing by the horizontal drive circuit 34. A selection signal for sequentially selecting the pixels 32AA to 32AE is generated, and this selection signal is output to the gate lines GATE1 to GATE5 of the sub-pixels 32AA to 32AE.

  Thus, in the liquid crystal display device 31, pixels are sequentially selected in line units by the gate signal, and further, subpixels are sequentially selected in the selection of each pixel, and each subpixel is driven in time series by the area gradation method. Images according to the gradation data R [5-1], G [5-1], and B [5-1] are displayed.

  In such a display by the area gradation method, in the liquid crystal display device 31, a region allocated to one pixel is equally divided in a direction along the signal line, and thereby a pixel provided with a drive circuit for each sub-pixel. Regions of circuits 44A-44E are formed (FIG. 4). Further, in the region of each pixel circuit 44A to 44E (FIGS. 1 and 5), it is formed with the same layout except for the connection to the corresponding electrodes 43A to 43E, thereby confirming various operations and changing the number of bits. It is formed so that it is possible to easily cope with a design change related to the above.

  Each of the pixel circuits 44A to 44E is driven by a memory circuit including inverters 6 and 7 that acquires and holds the signal level of the signal line, and electrodes 43A to 43E that are used for display according to the acquired and held signal level. The drive circuit switch circuits 9 and 10 for outputting signals and the signal line switch circuit 8 (FIG. 3) for connecting the memory circuit to the signal line in response to the gate signal are used to form pixel circuits 44A to 44E. A memory circuit and a drive signal switch circuit are respectively provided on both ends of each of the two, and an area AR for connection to the electrodes 43A to 43E is formed between the memory circuit and the drive signal switch circuit (see FIG. 1 and FIG. 5).

  As a result, in the liquid crystal display device 31, a connection area AR having a certain size is provided substantially at the center of the production area of the pixel circuits 44A to 44E, and the pixel circuits 44A to 44E are formed using the area AR. Are connected to the corresponding electrodes 43A to 43, and the wiring patterns of the electrodes 43A to 43E can be created with a high degree of freedom. Therefore, even when the area of the electrodes becomes further different due to the increase in the number of bits, the connection of these identically formed pixel circuits to these electrodes can be easily designed, and the sub-pixels are configured accordingly. The pixel circuit and electrode layout to be performed can be simplified, and the number of bits can be easily increased to achieve higher resolution and higher gradation.

  Further, in the case where the connection area AR is provided in the approximate center of the creation area of the pixel circuits 44A to 44E in this way, the connection of the electrodes 43A to 43E can be achieved even at the connection location to the electrodes 43A to 43E. An edge part can be avoided and various malfunctions can be prevented by providing such a connection location in the edge part of electrode 43A-43E by this. In addition, in such a malfunction, it is the brightness | luminance nonuniformity etc. which are considered to originate in the fine inclination etc. of these electrodes 43A-43E.

  Further, in this embodiment, the connection portions to the electrodes 43A to 43E formed in this way are arranged irregularly in the horizontal direction so as not to overlap when viewed from the vertical direction. Thus, the occurrence of various interference fringes can be effectively avoided by arranging such connection portions in a line.

(3) Advantages of the embodiment According to the above configuration, in the region where the circuit of each subpixel is disposed, the memory circuit and the switch circuit are disposed on both ends, and the region for electrode connection is provided at the center of this region By forming and connecting these circuits and electrodes in this electrode connection region, the layout of pixel circuits and electrodes constituting sub-pixels is simplified in a multi-bit memory display device, and multi-bits can be easily To achieve higher gradation and higher resolution.

  Specifically, these pixels are made of reflective liquid crystal, and in the display device using a multi-bit memory system, the layout of the pixel circuits and electrodes constituting the sub-pixel is simplified, and the number of bits is easily increased to increase the gradation. High resolution can be achieved.

  In addition, the connection points are arranged so as to be irregularly different in the horizontal direction so that the connection points to the electrodes do not overlap each other when viewed from the vertical direction, and thereby the locations where the wiring of the drive signal is connected to the electrodes are at least Since adjacent sub-pixels are provided at different positions in the horizontal direction, image quality deterioration due to various interference fringes can be effectively avoided.

  In the above-described embodiments, the case where the display unit is formed by so-called vertical stripes in which color filters of the same color extend in the vertical direction has been described. However, the present invention is not limited to this, and color filters of the same color are used. When the display unit is formed by so-called horizontal stripes extending in the horizontal direction, when the display unit is formed by arranging color filters in a mosaic pattern, the display unit is further arranged by arranging color filters in a delta pattern. It can be widely applied to the case of forming.

  In the above-described embodiments, the case where one subpixel is driven with two gradations of on / off by selectively applying in-phase and anti-phase drive signals to the common voltage has been described. However, the present invention is not limited to this. In the case where one subpixel is driven with more than two gradations by selectively applying a large number of drive signals having different phases, and further by modulation in the time axis direction. Can also be widely applied.

  In the above-described embodiment, the case where the signal lines are shared by all of the plurality of sub-pixels forming one pixel has been described. However, the present invention is not limited to this, and depending on the layout of the sub-pixels, The present invention can be widely applied to a case where a signal line is shared by only a part of a plurality of sub-pixels forming a pixel, and further to a case where a signal line is individually provided for each sub-pixel.

  In the above-described embodiment, a case has been described in which three types of gradation data of 5 bits each of red, green, and blue are input and processed simultaneously in parallel. However, the present invention is not limited to this, and 5 bits. The present invention can be widely applied to the case of applying gradation data processing with a bit number other than 1 to displaying a color image with four or more kinds of gradation data.

  In the above-described embodiment, the case where the present invention is applied to a reflective liquid crystal display device in which a display unit or the like is formed on a glass substrate has been described. However, the present invention is not limited to this, and the transmissive liquid crystal display device. It can be widely applied to various display devices such as EL (Electro Luminescence) display devices.

  The present invention can be applied to, for example, a liquid crystal display device in which one pixel is constituted by a plurality of sub-pixels, and gradation is expressed by driving the plurality of sub-pixels.

It is a top view which shows the layout of one sub pixel of the liquid crystal display device based on the Example of this invention. It is a block diagram which shows the liquid crystal display device based on the Example of this invention. FIG. 3 is a connection diagram illustrating a configuration of one pixel of the liquid crystal display device of FIG. 2. FIG. 3 is a plan view showing a configuration of one pixel of the liquid crystal display device of FIG. 2. It is a top view which shows the wiring pattern of the upper layer side of FIG. It is a top view with which it uses for description of the connection of a pixel circuit and an electrode. It is a block diagram which shows a liquid crystal display device by a multi-bit memory system. FIG. 8 is a connection diagram illustrating one pixel of the liquid crystal display device of FIG. 7. FIG. 9 is a connection diagram illustrating a pixel circuit provided in one pixel in FIG. 8. FIG. 10 is a connection diagram illustrating an equalization circuit of the pixel circuit of FIG. 9. 10 is a time chart for explaining the operation of the pixel circuit of FIG. 9.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1, 31 ... Liquid crystal display device 2, 32 ... Display part, 2A, 32A ... Pixel, 2AA-2AE, 32AA-32AE ... Sub-pixel, 3A-3E, 43A-43E ... Electrode, 4A-4E 44A to 44E... Pixel circuit, 5A to 5E... Liquid crystal cell, 6, 7, 65... Inverter, 8, 9, 10... Switch circuit 16, 33. Horizontal drive circuit

Claims (3)

A display unit in which pixels are arranged in a matrix, a vertical drive circuit that sequentially selects the pixels by gate lines, and a pixel that is selected by the vertical drive circuit in accordance with gradation data that indicates the gradation of the pixel In a display device having a horizontal drive circuit that outputs a drive signal of
The pixel is
Having a plurality of sub-pixels in which the area of the part for sequential display is increased,
The plurality of sub-pixels are
A memory circuit that acquires and holds the signal level of each signal line;
A drive signal switch circuit that outputs a drive signal to the electrode of the portion used for display according to the acquired and held signal level;
A pixel circuit including a signal line switch circuit for connecting the memory circuit to the signal line in response to a gate signal;
The display unit
A region of a pixel circuit provided with each of the pixel circuits by equally dividing a region allocated to one of the pixels in a direction along the signal line is formed,
The area of each pixel circuit is
The memory circuit, the drive signal switch circuit, and the signal line switch circuit are arranged in the same manner,
The memory circuit and the drive signal switch circuit are provided at both ends, respectively, and a region for connection to the electrode of the portion used for display is formed between the memory circuit and the drive signal switch circuit. ,
In the connection region, a wiring for outputting the drive signal is connected to an electrode of a part used for display. The display device according to claim 1, wherein the pixel is a pixel made of a reflective liquid crystal. 2. The display device according to claim 1, wherein a portion where the wiring for outputting the drive signal is connected to an electrode of a portion used for display is provided at a position that is different in the horizontal direction in at least adjacent sub-pixels.

Images