JP2005142346A - Unipolar transistor and semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To utilize a manufacturing step for LSIs and provide a stable void gate structure, concerning a unipolar transistor and a semiconductor integrated circuit device. <P>SOLUTION: At least an area on the side of a gate insulating film 2 in a gate electrode area of a unipolar transistor is formed as a void region 4 that is closed in four directions along the channel width direction. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a unipolar transistor and a semiconductor integrated circuit device, and more particularly to a unipolar transistor and a semiconductor integrated circuit device that are characterized by the structure of a gate having a cavity structure for sensing or memory action.

  In recent years, electronic devices, information terminals, and game consoles equipped with sensors have appeared. In such devices, various new states can be detected by detecting various states with sensors and performing arithmetic processing with built-in LSIs. It has functions and is expected to develop further in the future.

  On the other hand, in recent years, various robots have appeared, but they are also equipped with many sensors in each part, and by processing this information with LSI, it becomes possible to perform independence and complex movements. ing.

  Conventional sensors are elements different from LSIs, and they are manufactured through a manufacturing process different from LSIs. By combining these sensors with LSI as a component, electronic devices with the desired function can be obtained. It was tailored.

  For example, as a sensor, a sacrificial oxide film made of an LTO (low temperature oxidation) film is provided in the gate electrode region of a MOSFET, and after the gate electrode is formed on the TLO film, the LTO film is removed by etching and directly under the gate electrode. It has been proposed to form an acceleration sensor and to configure an acceleration sensor using the bending due to the acceleration of the cavity (see, for example, Patent Document 1).

  There has also been proposed a gas sensor that senses the gas concentration by providing a gap directly under the gate electrode and flowing a gas to be measured in the gap (see, for example, Patent Document 2).

  However, in the future, it is expected that the sensor and LSI will be developed into an integrated one, which will reduce the cost, enable miniaturization, increase the speed by eliminating the signal delay in the connection wiring, etc. Various benefits are born.

In order to integrate such a sensor and LSI, a transistor structure is formed by forming a source / drain region and an extension region using a normal self-alignment process, and the sensor portion corresponds to a gate insulating film. It has been proposed to form a pressure sensor by finally removing a dummy layer made of a thermal oxide film or the like and providing a cavity directly below the gate electrode (see, for example, Patent Document 3).
Japanese Patent Laid-Open No. 10-303414 JP 09-033467 A JP-A-10-178182

  However, in the case of Patent Document 1 and Patent Document 2, the configuration of the sensor unit is special. Even if the sensor and the LSI are integrally formed, the sensor and the LSI can be formed in the same process. Therefore, there is a problem that cost reduction cannot be realized.

  In the case of the above-mentioned Patent Document 3, although a manufacturing process of LSI is used, a dummy layer made of a thermal oxide film or the like is not affected by another oxide film such as an interlayer insulating film or an Si substrate. There is a problem that it is difficult to selectively remove by etching.

  In addition, since the surface of the active channel region is exposed, it is difficult to prevent the surface state from changing even if the cavity is filled with an inert gas or the like. Therefore, there is a problem that it is difficult to perform highly accurate measurement or stable operation.

  Therefore, an object of the present invention is to provide a stable cavity gate structure suitable for a sensor or a memory while using an LSI manufacturing process.

FIG. 1 is a diagram illustrating the basic configuration of the present invention. Means for solving the problems in the present invention will be described with reference to FIG. Reference numerals 1, 3, and 6 in the figure denote a semiconductor substrate, source / drain regions, and a silicide layer, respectively.
In order to solve the above-described problem, according to the present invention, in the unipolar transistor, at least the region on the gate insulating film 2 side of the self-aligned gate electrode region of the unipolar transistor is closed vertically and horizontally along the channel width direction. It is characterized in that it is a hollow region 4.

  Thus, by making at least the region on the gate insulating film 2 side of the self-aligned gate electrode region of the unipolar transistor into the cavity region 4, that is, by selectively removing the gate electrode, it is compatible with the LSI manufacturing process. Therefore, a unipolar transistor that operates as a sensor or the like can be manufactured at a low cost, and a cavity gate structure that is stable both in the manufacturing process and in the surface state can be realized.

  In this case, the upper part of the cavity region 4 may be formed as a silicide gate electrode by removing only the lower part of the salicide electrode. Alternatively, the floating gate electrode of the EPROM may be removed and the channel width direction may be passed through the insulating layer. Alternatively, the gate electrode may be extended.

  Further, a gate electrode extending in the channel width direction via an insulating layer may be provided on the upper portion of the cavity region 4, thereby detecting the moving speed or the like of the detected medium and applying it to the detected medium. It is possible to measure the strength of external force.

  In this case, at least one end of the cavity region 4 may be an open structure, and thereby, the medium to be detected can be taken into and out of the cavity region 4 or can be easily flowed.

  The cavity region 4 may be a sealed space, and a polarized substance or an ionic substance is used as a detection medium by providing a pair of electrodes via insulating layers at both ends of the cavity region 4 in the channel width direction. In some cases, a memory function can be provided.

  Alternatively, the cross-sectional area perpendicular to the channel width direction at both ends of the cavity region 4 in the channel width direction is made larger than the cross-sectional area perpendicular to the channel width direction of the portion on the channel region 5 to be applied to the detected medium. The strength of external force can be measured with higher sensitivity.

  In each of the above cases, any of the fluid, gas, particles, movable body, ions, or molecules to be detected may be disposed in the cavity region 4, and the sensor functions as a sensor or memory depending on the type of the medium to be detected. Can be made.

  A low-cost and small-sized semiconductor integrated circuit device with a sensor can be realized by monolithically integrating the above-described unipolar transistor and a unipolar transistor having a normal self-aligned gate electrode. In addition, since the interconnect wiring can be formed by a series of multilayer wiring manufacturing steps, the wiring length connecting the sensor portion and the LSI portion can be shortened, thereby enabling high speed operation.

  In the case of manufacturing the unipolar transistor described above, at least the region on the gate insulating film 2 side of the self-aligned gate electrode is selectively removed through the contact hole for the self-aligned gate electrode, and the channel is aligned along the channel width direction. The cavity region 4 may be closed vertically and horizontally, or in the case of an EPROM structure, the floating gate electrode is selectively removed through a contact hole for the floating gate electrode, and the vertical and horizontal directions along the channel width direction are A closed cavity region 4 may be used.

  In this case, it is desirable that the gate electrode to be removed is once replaced with metal, particularly Al, and then selectively removed to form the cavity region 4, thereby facilitating selective removal of the gate electrode.

  When removing the gate electrode, the multilayer wiring connected to the gate electrode to be removed may be removed simultaneously in a series of steps, whereby the cavity region 4 is formed in the uppermost layer of the interlayer insulating film. It can be pulled out to the surface, and the introduction of the detection medium becomes easy.

  According to the present invention, a conventional unipolar transistor can be used as a sensor or a memory without changing the basic structure, and can easily be mixed with normal LSI functions (calculation, storage,...). Therefore, the cost of the entire electronic device can be reduced, the size can be reduced, wiring delay can be suppressed, and the speed can be increased.

  In the present invention, after forming a unipolar transistor to be a sensor or a memory by using a manufacturing process of a normal unipolar transistor constituting a peripheral circuit or a logic circuit, at least a gate of a gate electrode of the unipolar transistor to be a sensor or a memory The area on the insulating film side is selectively removed to form a cavity gate structure, which makes it possible to stabilize the cavity gate structure and to make the sensor and LSI monolithic, lower cost, and smaller And high speed.

Here, the manufacturing process of the sensor according to the first embodiment of the present invention will be described with reference to FIG. 2 to FIG. 9. The upper drawing in each drawing is a cross-sectional view perpendicular to the gate width direction, and the lower drawing. The figure is a cross-sectional view along the gate width direction.
See Figure 2
First, an element isolation oxide film 12 is formed on an n-type silicon substrate 11 and a p-type well region 13 surrounded by the element isolation oxide film 12 is formed using a normal self-aligned MOSFET manufacturing process.

Next, after forming a gate oxide film 14 made of a thermal oxide film on the surface of the p-type well region 13, a polycrystalline silicon film and a SiO ₂ film are deposited, and then patterned to a width of 0.1 μm, for example. A gate electrode 15 and a cap layer 16 are formed.

Next, n ⁻ -type LDD (Lightly Doped Drain) regions 17 are formed by ion implantation of As using the gate electrode 15 and the cap layer 16 as a mask.

See Figure 3
Next, after forming a SiO ₂ film on the entire surface, anisotropic etching is performed to form a sidewall 18, and then As is ion-implanted again using the sidewall 18 as a mask to form n ⁺ -type source / drain regions. 19 is formed.

Next, after depositing a Co film on the entire surface, a silicide layer 20 made of CoSi ₂ is formed on the surface of the n ⁺ -type source / drain region 19 by heat treatment, and then an unreacted Co film is selectively formed. Etch away.

See Figure 4
Next, after providing an interlayer insulating film 21 and planarizing the surface, a contact hole reaching the n ⁺ type source / drain region 19 is provided, and then a thin TiN film 22 is deposited on the entire surface, and then the contact hole is completely formed. A W film is deposited so as to be embedded, and then a W plug 23 is formed by planarizing the surface using a CMP (Chemical Mechanical Polishing) method.

  Next, a contact hole 24 reaching the gate electrode 15 is formed on the gate contact side.

See Figure 5
Next, after an Al layer 25 is deposited on the entire surface, a Ti layer 26 is deposited on the Al layer 25 to increase the efficiency in the next heat treatment step.

See FIG.
Next, for example, heat treatment is performed at 400 ° C. for 30 minutes in an N ₂ atmosphere to replace the gate electrode 15 made of polycrystalline silicon with the Al substitution layer 27. In this heat treatment step, when the width of the gate electrode 15 is 0.1 μm and the height is 0.15 μm, polycrystalline silicon having a thickness of about 8 μm is replaced with Al.

See FIG.
Next, the Al layer 25 is removed by CMP until the W plug 23 is exposed, and the surface is flattened.

See FIG.
Next, as with a normal multilayer wiring structure, an Al wiring forming process, an interlayer insulating film forming process, a W plug manufacturing process, and a planarization process by CMP are repeated for the number of layers required. Then, Al wirings 28, 31, 34, 37, interlayer insulating films 29, 32, 35, and W plugs 30, 33, 36 are formed. In this case, in order to simplify the illustration, the multilayer wiring structure portion is shown as being thinner than the transistor portion.
Although not shown, a TiN film is formed prior to the formation of the W plugs 30, 33, and 36.

See FIG.
Next, a resist pattern 38 having an opening that exposes only the Al wiring 37 connected to the Al substitution layer 27 is provided, and wet etching using H ₂ SO ₄ is performed by using the resist pattern 38 as a mask. 37 → W plug 36 → Al wiring 34 → W plug 33 → Al wiring 31 → W plug 30 → Al wiring 28 → Al layer 25 → Al substitution layer 27 is removed by etching in sequence, and the cavity gate 40 and the leading cavity 39 connected thereto. The basic configuration of the sensor of Example 1 is completed.

  In the MOSFET constituting the peripheral circuit or the logic circuit, the Al electrode 25 is not replaced with the Al electrode 25 itself, or the Al electrode replacement layer 27 is removed even if the gate electrode 15 is replaced. Do not do.

See FIG.
When a detection medium 41 of fluid, gas, particles, ions, or molecules is introduced into the cavity gate 40 via the extraction cavity 39, the resistance varies depending on the detection medium 41 to be introduced. Since a voltage drop occurs from the electrode through the resistor and the voltage applied to the channel region changes, the current flowing between the source and the drain changes, whereby the resistance value or ion concentration of the detected medium 41 can be sensed.

See FIG.
In addition, when the detected medium 41 is a dielectric, since the dielectric constants are different, the capacitance of the capacitor connected in series with the gate insulating film is changed, and as a result, the voltage applied to the gate electrode is changed. The flowing current changes, and the dielectric constant and the like of the detected medium can be sensed.

See FIG.
FIG. 12 is a conceptual configuration diagram of a tilt sensor that uses a change in dielectric constant depending on the presence / absence of a detection medium. If the dielectric constant of the detection medium 41 filled in advance is acquired, the amount of the inclination is increased in the channel region. Since the amount of the medium present in each is different and the dielectric constant is also different, the drain current changes according to the amount of inclination.

  In the first embodiment, the electrode to which the gate voltage is applied is not particularly shown, but may be an electrode to which the gate voltage is applied using a part of the wiring, and the gate electric field is changed from the electrode to the extraction cavity. The voltage is applied to the channel region via the portion 39 → the detected medium 41 → the gate insulating film 14.

  As described above, in the first embodiment, a basic structure is formed using a normal self-aligned MOSFET manufacturing process, the gate electrode 15 is replaced with Al, and the Al replacement layer 27 is selectively formed. Therefore, the cavity gate 40 self-aligned with the channel region can be formed with good reproducibility.

If the gate electrode 15 is to be removed without removing the polycrystalline silicon, an HF + HNO ₃ solution is required as an etchant, and this HF + HNO ₃ solution has an etching action on the SiO ₂ film, so that the etching time is long. Then, the interlayer insulating film and the like are also etched, and the reliability is lowered.

  In addition, if the gate electrode 15 is formed in advance with Al, it can be selectively removed without substituting Al. However, when the source / drain regions are formed by a self-alignment process, the impurities in the source / drain regions are generally activated. Therefore, heat treatment at 900 to 1100 [deg.] C. is required, and aluminum having a melting point of 660 [deg.] C. cannot be applied because it melts, and it is difficult to miniaturize the element.

  In Example 1, since the gate insulating film on the channel region remains stably without being etched in the step of removing the Al substitution layer 27, the channel region is not exposed. Will not change.

Next, a sensor according to a second embodiment of the present invention in which an electrode to which a gate voltage is applied is provided at a position away from the channel region will be described with reference to FIG.
See FIG.
FIG. 13 is a schematic plan view of the sensor according to the second embodiment of the present invention. For example, the side gate electrode 42 is formed using the manufacturing process of the control gate using the manufacturing process of the EPROM. .

See FIG.
FIG. 14 is a conceptual configuration diagram in the case where the sensor of FIG. 13 is used as an inclination sensor. When the resistivity of the detection medium 41 filled in advance is acquired, the side gate electrode 42 to the channel region are obtained depending on the amount of inclination. Therefore, the drain current changes according to the amount of inclination.

Next, the manufacturing process of the sensor according to the third embodiment of the present invention in which a self-aligned gate electrode is provided on the cavity gate will be described with reference to FIGS. 15 to 20. In this case, the above-described first embodiment will be described. A silicide layer is also provided on the gate electrode in the silicide formation step in FIG.
In this case, a cross-sectional view along the channel width direction and a schematic plan view of the final configuration are shown.

See FIG.
An element isolation oxide film 12 is formed on the n-type silicon substrate 11 and a p-type well region 13 surrounded by the element isolation oxide film 12 is formed using a normal self-aligned MOSFET manufacturing process.

  Next, after forming a gate oxide film 14 made of a thermal oxide film on the surface of the p-type well region 13, after depositing a polycrystalline silicon film and a SiN film, the gate is patterned by patterning to a width of 0.1 μm, for example. The electrode 15 and the cap layer 43 are formed.

Next, As is ion-implanted by using the gate electrode 15 and the cap layer 43 as a mask to form an n ⁻ -type LDD region (not shown), an SiO ₂ film is formed on the entire surface, and anisotropic etching is performed. Then, the sidewall 18 is formed, and then As is ion-implanted again using the sidewall 18 as a mask, n ⁺ -type source / drain regions (not shown) are formed.

See FIG.
Next, after selectively removing the cap layer 43 made of the SiN film, a Co film is deposited on the entire surface, and then a heat treatment is performed, whereby a silicide layer made of CoSi ₂ (on the surface of the n ⁺ -type source / drain region ( At the same time as forming a silicide layer 44 made of CoSi ₂ on the gate electrode 15, the unreacted Co film is selectively removed by etching.

See FIG.
Next, after providing the interlayer insulating film 21 and planarizing the surface, a contact hole reaching the n ⁺ type source / drain region and a contact hole reaching the silicide layer 44 are provided, and then a thin TiN film 22 is deposited on the entire surface. After that, a W film is deposited so as to completely fill the contact hole, and then the surface is planarized using a CMP (Chemical Mechanical Polishing) method, whereby the W for the silicide layer provided on the n ⁺ -type source / drain regions is formed. A plug (not shown) is formed, and a W plug 45 for the silicide layer 44 is formed.

  Next, a contact hole 46 reaching the gate electrode 15 is formed on one end side of the gate electrode 15.

See FIG.
Next, after an Al layer 25 is deposited on the entire surface, a Ti layer 26 is deposited on the Al layer 25 to increase the efficiency in the next heat treatment step.

See FIG.
Next, for example, heat treatment is performed at 400 ° C. for 30 minutes in an N ₂ atmosphere to replace the gate electrode 15 made of polycrystalline silicon with the Al substitution layer 27. In this heat treatment step, when the width of the gate electrode 15 is 0.1 μm, the polycrystalline silicon having a thickness of about 8 μm is replaced with Al, but the silicide layer 44 is hardly replaced.

See FIG.
Next, the Al layer 25 is removed by CMP until the W plug 45 is exposed, and the surface is flattened.

See FIG.
Next, as with a normal multilayer wiring structure, an Al wiring forming process, an interlayer insulating film forming process, a W plug manufacturing process, and a planarization process by CMP are repeated for the number of layers required. Then, Al wirings 28, 31, 34, 37, interlayer insulating films 29, 32, 35, and W plugs 30, 33, 36 are formed. In this case, in order to simplify the illustration, the multilayer wiring structure portion is shown as being thinner than the transistor portion.
Although not shown, a TiN film is formed prior to the formation of the W plugs 30, 33, and 36.

See FIG.
Next, a resist pattern 38 having an opening that exposes only the Al wiring 37 connected to the Al substitution layer 27 is provided, and wet etching using H ₂ SO ₄ is performed by using the resist pattern 38 as a mask. 37 → W plug 36 → Al wiring 34 → W plug 33 → Al wiring 31 → W plug 30 → Al wiring 28 → Al layer 25 → Al substitution layer 27 is removed by etching in sequence, and the cavity gate 40 and the leading cavity 39 connected thereto. The basic configuration of the sensor of Example 3 is completed.

See FIG.
FIG. 23 is a schematic plan view showing the final configuration of the third embodiment, and has a structure in which a W plug 45 serving as a gate contact is formed on the other end side of the cavity gate 40 facing the extraction cavity 39.

Next, a chemical substance / DNA analysis method using the sensor of Example 3 will be described with reference to FIG.
See FIG.
FIG. 24 is an explanatory view of a chemical substance / DNA analysis method using the sensor of Example 3, in which a chemical substance or DNA is allowed to flow as a detected medium 41 in the cavity gate 40. Alternatively, if DNA or the like is flowed, the change in the composition of the material can be known because the dielectric constant and resistance change with time.

In particular, for DNA, the DNA base sequence can also be read. In this case, the width of the upper gate electrode made of the silicide layer 44 needs to be about 10 nm.
At present, the operation of a MOSFET having a channel length of 6 nm has been confirmed.

Next, a droplet component analysis method using the sensor of Example 3 will be described with reference to FIG. See FIG.
FIG. 25 is an explanatory diagram of a droplet component analysis method using the sensor of Example 3, in which a chemical substance is caused to flow in the form of droplets in the cavity gate 40, and the dielectric constant and resistance are varied depending on the state of the droplets. Therefore, it is possible to analyze the concentration, component, ionization degree, and the like of the chemical substance that constitutes the droplet.

Next, a sensor according to Example 4 of the present invention will be described with reference to FIG.
See FIG.
FIG. 26 is a schematic cross-sectional view along the channel width direction of the sensor according to the fourth embodiment of the present invention. The basic configuration is the same as that of the third embodiment described above. The open end face is sealed with a sealing member 47 made of glass, plastic, or metal.

Next, a sensor according to Example 5 of the present invention will be described with reference to FIG.
See FIG.
FIG. 27 is a schematic cross-sectional view along the channel width direction of the sensor according to the fifth embodiment of the present invention. The basic configuration is the same as that of the third embodiment described above. The connecting portion side with the hollow gate 40 is sealed with a sealing member 47 made of plastic or metal.

Next, with reference to FIG. 28, a memory using the sensor of Example 4 or 5 of the present invention will be described.
See FIG.
FIG. 28 is an explanatory diagram of a memory using the sensor according to the fourth or fifth embodiment of the present invention. An ion source 49 such as amino acid or butyl alcohol is provided in a working fluid 48 made of, for example, silicone oil in the cavity gate 40. The dispersion or dissolved solution is enclosed, and the ion source 49 is ionized in the working fluid 48.
In this case, in order to operate as a memory, it is necessary to provide a pair of electrodes 50 and 51 at both ends in the longitudinal direction of the cavity gate 40.

  As shown in the upper side of FIG. 28, when the electrode 51 is biased negatively, the ion source 49 that becomes positive ions migrates to the electrode 51 side, and when a voltage is applied to the silicide layer 44 that is the upper gate electrode, Will indicate the condition.

  On the other hand, as shown in the lower side of FIG. 28, when the electrode 50 is negatively biased, the ion source 49 migrates to the electrode 50 side, and when a voltage is applied to the silicide layer 44 that is the upper gate electrode, the first state is different. The second state is shown. When the first state and the second state are made to correspond to “0” and “1”, the memory operation becomes possible.

  In this case, the ion source 49 in the working fluid 48 does not move so much for a certain time, for example, about several minutes to one week even when the voltage applied to the electrodes 50 and 51 is cut off due to the action of viscosity. It is also possible to use a volatile memory.

Next, with reference to FIG. 29, another memory using the sensor of Example 4 or 5 of the present invention will be described.
See FIG.
FIG. 29 is an explanatory diagram of another memory using the sensor according to the fourth or fifth embodiment of the present invention, in which a movable movable object 52 such as a Si fine particle or a polymer is enclosed in a cavity gate 40.
In this case, in order to operate as a memory, it is necessary to provide a pair of electrodes 50 and 51 at both ends in the longitudinal direction of the cavity gate 40, but the electrodes 50 and 51 are exposed in the cavity gate 40. It may be arranged or may be arranged via an insulating film.

  As shown in the upper side of FIG. 29, when the electrodes 50 and 51 are negatively biased, the movable object 52 that is polarized is drawn toward the electrode 51 according to the polarized state, and a voltage is applied to the silicide layer 44 that is the upper gate electrode. When applied, it indicates the first state.

  On the other hand, as shown in the lower side of FIG. 29, when the electrodes 50 and 51 are positively biased, the polarized movable object 52 migrates to the electrode 50 side, and when a voltage is applied to the silicide layer 44 that is the upper gate electrode, This indicates a second state different from the above state. When the first state and the second state are made to correspond to “0” and “1”, the memory operation becomes possible.

  In this case, when the voltage applied to the electrodes 50 and 51 is turned off, the movable object 52 does not move, so that a nonvolatile memory is obtained.

Next, a sensor according to Example 6 of the present invention will be described with reference to FIG.
See FIG.
FIG. 30 is an explanatory diagram of the configuration in the vicinity of the cavity gate of the sensor according to the sixth embodiment of the present invention. Here, the sensor is configured by using the structure of the EPROM. It is the same as that of the sensor.

  As shown in the figure, the floating gate of the EPROM is removed to form the cavity gate 40, and the control gate 54 provided on the second gate insulating film 53 is divided into a plurality of gates. A contact plug (not shown) is connected to 54.

Next, a DNA analysis method using the sensor of Example 6 of the present invention will be described with reference to FIG.
See FIG.
FIG. 31 is an explanatory diagram of a DNA analysis method using the sensor of Example 6 of the present invention. When a voltage is applied to the electrode 50 provided on one end side of the cavity gate 40, the DNA 55 moves by electrophoresis. At that time, since the dielectric constant and resistance change with time, the base sequence of DNA 55 can also be read.

  In this case, since a multi-gate is used, even if the gate length of each control gate 54 is 0.01 μm, the base sequence of DNA 55 can be obtained with a resolution of about 1/10 of the gate length by taking the difference of each control gate 54. Can be read.

Next, with reference to FIG. 32, the multi-gate sensor of Example 7 of this invention is demonstrated.
See FIG.
FIG. 32 is a diagram illustrating the configuration of a multi-gate sensor according to a seventh embodiment of the present invention. The upper diagram is a schematic plan view, and the lower diagram is a conceptual cross-sectional view showing the vicinity of the cavity gate. In this case, the EPROM structure is used as in the sixth embodiment.

  As shown in the figure, a plurality of gate electrodes 56 are formed by patterning a conductor layer such as polycrystalline silicon deposited in the manufacturing process of the control gate so as to extend in the gate length direction of the cavity gate 40, and Large cavities 57 and 58 having a large volume are provided at both ends of the gate 40, and have a symmetrical structure.

Next, an infrared detection method using the multi-gate sensor according to the seventh embodiment of the present invention will be described with reference to FIG.
See Figure 33
FIG. 33 is an explanatory diagram of an infrared detection method using a multi-gate sensor according to a seventh embodiment of the present invention. A light shielding plate 59 is provided on the upper portion of one large cavity portion 57 and a droplet or the like is provided in the cavity gate 40. The movable object 60 is inserted together with a gas such as air.

  Here, when the other large cavity 58 is irradiated with the infrared ray 61, the air in the large cavity 58 expands in accordance with the energy of the infrared ray 61, so that the movable object 60 moves to the large cavity 57 side, and each gate Since the drain current of the FET having the electrode 56 sequentially changes, the moving position of the movable object 60 can be detected, and the incident amount of the infrared rays 61 can be detected from this moving position.

Next, with reference to FIG. 34, the pressure detection method using the multi-gate sensor of Example 7 of this invention is demonstrated.
See FIG.
FIG. 34 is an explanatory diagram of a pressure detection method using the multi-gate sensor according to the seventh embodiment of the present invention, in which a movable object 60 such as a droplet is inserted into a cavity gate 40 together with a gas such as air.

  Here, when pressure is applied to the other large cavity 58, the air in the large cavity 58 is pushed toward the cavity gate 40 according to the pressure, so that the movable object 60 moves toward the large cavity 57, Since the drain current of the FET having the gate electrode 56 changes sequentially, the moving position of the movable object 60 can be detected, and the magnitude of the pressure can be detected from this moving position.

Next, with reference to FIG. 35, the acceleration detection method using the multi-gate sensor of Example 7 of this invention is demonstrated.
See FIG.
FIG. 35 is an explanatory diagram of an acceleration detection method using the multi-gate sensor according to the seventh embodiment of the present invention, in which a movable object 60 such as a droplet is inserted into a cavity gate 40 together with a gas such as air.

  Here, when the acceleration F = aM is applied to the other large cavity 58, the air in the large cavity 58 is pushed toward the cavity gate 40 according to the acceleration, so that the movable object 60 moves toward the large cavity 57. Since the drain current of the FET having each gate electrode 56 changes sequentially, the moving speed of the movable object 60 can be detected, and the magnitude of acceleration can be detected from this moving speed.

Next, with reference to FIG. 36, an impact sensor using the multi-gate sensor according to the seventh embodiment of the present invention will be described.
See FIG.
FIG. 36 is a diagram illustrating the principle of an impact sensor using a multi-gate sensor according to a seventh embodiment of the present invention, in which a movable object 60 such as a droplet is inserted into a cavity gate 40 together with a gas such as air. As shown in the upper diagram, the movable object 60 is positioned at the center of the cavity gate 40 before applying an impact.

  Next, as shown in the interruption diagram, when a weak impact is applied from the right side of the large cavity portion 58, the movable object is blown to the left side, while on the other hand, as shown in the lower diagram, When a strong impact in the right direction is applied to the cavity 58, the movable object 60 is blown to the right, and the drain current of the FET having each gate electrode 56 changes according to the degree of the impact. Therefore, the magnitude and direction of impact can be detected.

In the above description, an integrated structure with a normal LSI is not mentioned, and therefore an example of an integrated structure will be described with reference to FIGS. 37 and 38 using a multi-gate sensor.
See FIG.
FIG. 37 is a diagram for explaining the configuration of an integrated multi-gate sensor. The upper diagram is a schematic plan view, the lower diagram is a conceptual equivalent circuit diagram, and as shown in FIG. 6, six gate electrodes 56 extending in the direction perpendicular to the longitudinal direction of the cavity gate 40 are provided in the longitudinal direction of the cavity gate 40.

  Further, here, both the cavity gates 40 are provided with the extraction cavities 39 and 63, and when the detected medium 41 is introduced from one of the extraction cavities 39, it flows out from the other extraction cavities 63. ing.

See FIG.
FIG. 38 is a conceptual plan view of a semiconductor integrated circuit device in which sensors are integrated. An LSI 65 including a multi-gate sensor 62, an amplifier circuit, an arithmetic circuit, a memory circuit, and the like is monolithically formed on a silicon chip 64. In addition, other components 66 such as a pump, a sensor, or a MEMS are integrated as necessary.

As mentioned above, although each Example of this invention was described, this invention is not restricted to the structure and conditions described in each Example, A various change is possible.
For example, the above numerical values such as the gate length and heat treatment conditions are merely examples, and may be changed as appropriate.

  In the Al replacement step, the Ti layer is used as a cap. However, the Ti layer is not always necessary, and the heat treatment may be performed while the Al layer is deposited.

  In each of the above embodiments, the cavity gate is formed after the multilayer wiring structure is formed. However, the cavity gate may be performed after the planarization process immediately after the Al replacement.

In the third embodiment, the silicided silicide layer is used as the gate electrode. However, a two-layer structure such as a polycrystalline silicon / WSi ₂ structure can be used in the gate electrode deposition process without using the silicidation process. A polycrystalline silicon / TiN structure or a polycrystalline silicon / WN structure may be used.

  Further, in each of the above embodiments, the gate electrode for applying a voltage to the cavity gate is provided on the upper part of the cavity gate. However, the gate electrode is not necessarily required to be provided on the side part of the cavity gate. is there.

  In each of the above embodiments, polycrystalline silicon is replaced with Al. However, it is not always necessary to replace Al, and other metals such as Au, Ag, Cu, and Zn may be substituted. Is.

  In the memory shown in FIG. 28, silicone oil is used as the working fluid and amino acid or butyl alcohol is used as the ion source. However, the present invention is not limited to these combinations, and can be appropriately changed according to the purpose.

  In the above embodiment, the W plug is provided at one end of the cavity gate and the extraction cavity is provided at the other end. However, a W plug is provided at the center of the cavity gate and a pair of extraction cavities are provided at both ends. It may be configured so that a chemical or DNA can flow through the cavity gate as will be described later.

In the multi-gate sensor according to the seventh embodiment, the movable object is inserted in the cavity gate in advance. However, the movable object may be continuously inserted into the cavity gate from the large cavity portion. In this case, the position of the movable object can be detected by using a plurality of transistors, and a means for using the detection signal can be selected.
In this case, alcohols can be used as the movable object.

The detailed features of the present invention will be described again with reference to FIG. 1 again.
Again see Figure 1
(Supplementary note 1) A unipolar transistor characterized in that at least the region on the gate insulating film 2 side of the self-aligned gate electrode region of the unipolar transistor is a hollow region 4 closed vertically and horizontally along the channel width direction. (1)
(Supplementary note 2) The unipolar transistor according to supplementary note 1, wherein an upper portion of the cavity region 4 is formed of a gate electrode. (2)
(Additional remark 3) The said gate electrode is comprised from the silicide layer 6 of the same kind as the silicide layer 6 provided in the surface of the source / drain region 3, The unipolar transistor of Additional remark 3 characterized by the above-mentioned.
(Supplementary note 4) The unipolar transistor according to supplementary note 1, wherein a gate electrode extending in a channel width direction is provided above the hollow region 4 with an insulating layer interposed therebetween.
(Supplementary note 5) The unipolar transistor according to supplementary note 1, wherein a plurality of gate electrodes extending in the channel length direction through an insulating layer are arranged along the channel width direction above the cavity region 4. (3)
(Supplementary note 6) The unipolar transistor according to any one of supplementary notes 1 to 5, wherein both ends of the cavity region 4 in the channel width direction have an open structure.
(Supplementary note 7) The unipolar transistor according to any one of supplementary notes 1 to 5, wherein the hollow region 4 is a sealed space.
(Supplementary note 8) The unipolar transistor according to supplementary note 7, wherein a pair of electrodes are provided at both ends of the hollow region 4 in the channel width direction with an insulating layer interposed therebetween.
(Additional remark 9) The cross-sectional area perpendicular | vertical or horizontal to the channel width direction of the both ends of the channel width direction of the said cavity region 4 is larger than the cross-sectional area perpendicular | vertical or horizontal to the channel width direction of the part on the channel region 5 The unipolar transistor according to appendix 7 or 8.
(Supplementary note 10) The unipolar transistor sensor according to any one of supplementary notes 1 to 9, wherein any one of a fluid, a gas, a granule, a movable body, an ion, or a molecule is disposed in the hollow region 4. . (4)
(Supplementary note 11) A semiconductor integrated circuit device, wherein the unipolar transistor according to any one of supplementary notes 1 to 10 and a unipolar transistor having a self-aligned gate electrode are monolithically integrated. (5)
(Supplementary Note 12) A cavity region in which at least the region on the gate insulating film 2 side of the self-aligned gate electrode is selectively removed through a contact hole for the self-aligned gate electrode, and the upper, lower, left, and right sides along the channel width direction are closed. 4. A method of manufacturing a unipolar transistor, wherein
(Supplementary note 13) The floating gate electrode is selectively removed through a contact hole with respect to the floating gate electrode of the self-aligned gate electrode having a two-layer structure of the floating gate electrode and the control gate electrode, and the vertical direction along the channel width direction is removed. A method for manufacturing a unipolar transistor, characterized in that the cavity region 4 is closed on both sides.
(Supplementary note 14) The method for manufacturing a unipolar transistor according to Supplementary note 12 or 13, wherein the gate electrode to be removed is once replaced with metal, and then selectively removed to form a cavity region 4.
(Additional remark 15) The removal process of the said gate electrode consists of the process of removing the multilayer wiring connected to the said gate electrode used as the said removal object simultaneously in a series of processes, Any one of Additional remark 12 thru | or 14 characterized by the above-mentioned. Unipolar transistor manufacturing method.

  As examples of use of the present invention, various types of sensors are typical, which can be applied to high-function and multi-function electronic devices including sensors such as robots. It can also be used as a memory.

It is explanatory drawing of the fundamental structure of this invention. It is explanatory drawing of the manufacturing process to the middle of the sensor of Example 1 of this invention. It is explanatory drawing of the manufacturing process to the middle after FIG. 2 of the sensor of Example 1 of this invention. It is explanatory drawing of the manufacturing process to the middle after FIG. 3 of the sensor of Example 1 of this invention. It is explanatory drawing of the manufacturing process to the middle after FIG. 4 of the sensor of Example 1 of this invention. It is explanatory drawing of the manufacturing process to the middle after FIG. 5 of the sensor of Example 1 of this invention. It is explanatory drawing of the manufacturing process to the middle after FIG. 6 of the sensor of Example 1 of this invention. It is explanatory drawing of the manufacturing process to the middle after FIG. 7 of the sensor of Example 1 of this invention. It is explanatory drawing of the manufacturing process after FIG. 8 of the sensor of Example 1 of this invention. It is explanatory drawing of the sensing principle in case a to-be-detected medium has electroconductivity. It is explanatory drawing of the sensing principle in case a to-be-detected medium is a dielectric material. It is a notional block diagram of the inclination sensor using the change of a dielectric constant. It is a schematic plan view of the sensor of Example 2 of the present invention. It is a notional block diagram at the time of using the sensor of Example 2 as an inclination sensor. It is explanatory drawing of the manufacturing process to the middle of the sensor of Example 3 of this invention. It is explanatory drawing of the manufacturing process to the middle after FIG. 15 of the sensor of Example 3 of this invention. It is explanatory drawing of the manufacturing process to the middle after FIG. 16 of the sensor of Example 3 of this invention. It is explanatory drawing of the manufacturing process to the middle after FIG. 17 of the sensor of Example 3 of this invention. It is explanatory drawing of the manufacturing process to the middle after FIG. 18 of the sensor of Example 3 of this invention. It is explanatory drawing of the manufacturing process to the middle after FIG. 19 of the sensor of Example 3 of this invention. It is explanatory drawing of the manufacturing process to the middle after FIG. 20 of the sensor of Example 3 of this invention. It is explanatory drawing of the manufacturing process after FIG. 21 of the sensor of Example 3 of this invention. It is a schematic plan view which shows the final structure of the sensor of Example 3 of this invention. 6 is an explanatory diagram of a chemical substance / DNA analysis method using the sensor of Example 3. FIG. 6 is an explanatory diagram of a method for analyzing a droplet component using the sensor of Example 3. FIG. It is a schematic sectional drawing along the channel width direction of the sensor of Example 4 of the present invention. It is a schematic sectional drawing along the channel width direction of the sensor of Example 5 of the present invention. It is explanatory drawing of the memory using the sensor of Example 4 or 5 of this invention. It is explanatory drawing of the other memory using the sensor of Example 4 or 5 of this invention. It is structure explanatory drawing of the cavity gate vicinity of the sensor of Example 6 of this invention. It is explanatory drawing of the analysis method of DNA using the sensor of Example 6 of this invention. It is composition explanatory drawing of the multigate sensor of Example 7 of this invention. It is explanatory drawing of the infrared detection method using the multigate sensor of Example 7 of this invention. It is explanatory drawing of the pressure detection method using the multi-gate sensor of Example 7 of this invention. It is explanatory drawing of the acceleration detection method using the multi-gate sensor of Example 7 of this invention. It is principle explanatory drawing of the impact sensor using the multigate sensor of Example 7 of this invention. It is a structure explanatory drawing of the multigate sensor integrated. It is a conceptual top view of the semiconductor integrated circuit device which integrated the sensor.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Gate insulating film 3 Source / drain region 4 Cavity region 5 Channel region 6 Silicide layer 11 N-type silicon substrate 12 Element isolation oxide film 13 P-type well region 14 Gate oxide film 15 Gate electrode 16 Cap layer 17 n ⁻ type LDD region 18 Side wall 19 n ⁺ type source / drain region 20 Silicide layer 21 Interlayer insulating film 22 TiN film 23 W plug 24 Contact hole 25 Al layer 26 Ti layer 27 Al substitution layer 28 Al wiring 29 Interlayer insulating film 30 W plug 31 Al wiring 32 Interlayer insulating film 33 W plug 34 Al wiring 35 Interlayer insulating film 36 W plug 37 Al wiring 38 Resist pattern 39 Draw cavity 40 Hollow gate 41 Detected medium 42 Side gate electrode 43 Cap layer 44 Silicide layer 45 W plug 46 Contact hole 47 Stop member 48 working fluid 49 ion source 50 electrode 51 electrode 52 movable object 53 a second gate insulating film 54 a control gate 55 DNA
56 Gate electrode 57 Large cavity 58 Large cavity 59 Light shielding plate 60 Movable object 61 Infrared 62 Multi-gate sensor 63 Draw cavity 64 Silicon chip 65 LSI
66 Other components

Claims (5)

A unipolar transistor characterized in that at least a region on a gate insulating film side of a self-aligned gate electrode region of a unipolar transistor is a hollow region closed vertically and horizontally along a channel width direction. 2. The unipolar transistor according to claim 1, wherein an upper portion of the hollow region is constituted by a gate electrode. 2. The unipolar transistor according to claim 1, wherein a plurality of gate electrodes extending in the channel length direction via an insulating layer are arranged along the channel width direction above the hollow region. 4. The unipolar transistor according to claim 1, wherein any one of a fluid, a gas, a particle, a movable body, an ion, and a molecule is disposed in the hollow region. 5. A semiconductor integrated circuit device, wherein the unipolar transistor according to claim 1 and a unipolar transistor having a self-aligned gate electrode are monolithically integrated.

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