CN104609358A - MEMS device and forming method thereof - Google Patents
MEMS device and forming method thereof Download PDFInfo
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- CN104609358A CN104609358A CN201310541693.0A CN201310541693A CN104609358A CN 104609358 A CN104609358 A CN 104609358A CN 201310541693 A CN201310541693 A CN 201310541693A CN 104609358 A CN104609358 A CN 104609358A
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Abstract
The invention relates to an MEMS device and a forming method thereof. The MEMS device comprises: a semiconductor substrate provided with a first region and a second region, wherein a CMOS device is formed on the semiconductor substrate of the first region; a dielectric layer covering the CMOS device, wherein a first interconnection structure connected with the CMOS device is formed in the dielectric layer of the first region, and a second interconnection structure is formed in the dielectric layer of the second region; a first welding disc positioned on the dielectric layer of the first region and connected with the first interconnection structure, and a second welding disc positioned on the dielectric layer of the second region and connected with the second interconnection structure; the MEMS device positioned on the dielectric layer, wherein one end of the MEMS device is connected with the first welding disc, and other end of the MEMS device is connected with the second welding disc; a through hole interconnection structure penetrating through the semiconductor substrate and partial dielectric layer of the second region and connected with the second interconnection structure; and a convex block positioned on the back surface of the semiconductor substrate and connected with the through hole interconnection structure. The MEMS device of the present invention has the small occupation volume.
Description
Technical field
The present invention relates to MEMS and make field, particularly a kind of MEMS and forming method thereof.
Background technology
MEMS (Micro Electro Mechanical System, microelectromechanicdevices devices) technology is a new and high technology of high speed development in this year, is the technology designing micrometer/nanometer (micro/nanotechnology) material, process, manufacture, measure and control.MEMS device is mainly integrated into the microsystem of an integral unit by mechanical component, optical system, driver part, electric-control system.MEMS technology is applied in the making of micro electro mechanical device usually, and described micro electro mechanical device comprises: position sensor, whirligig or inertial sensor etc., and described inertial sensor is acceleration transducer, gyroscope and sound transducer etc. such as.
Prior art utilizes MEMS technology to make micro electro mechanical device (MEMS) in a Semiconductor substrate, then CMOS technology is utilized to make control circuit in second half conductive substrate, then utilize lead frame (Leadframe) to be electrically connected with micro electro mechanical device by control circuit, thus form microelectromechanicdevices devices.Therefore, existing microelectromechanicdevices devices needs to utilize two semiconductor chip fabrication, thus makes the cost of existing microelectromechanicdevices devices higher.Usually, Semiconductor substrate containing control circuit and the Semiconductor substrate being formed with micro electro mechanical device be laid out in parallel in lead frame, therefore, the volume of existing microelectromechanicdevices devices is larger, thus the integrated level of microelectromechanicdevices devices is not high, the requirement of portability in application cannot be met.
Summary of the invention
The problem that the present invention solves how to improve the integrated level of MEMS.
For solving the problem, the invention provides a kind of formation method of MEMS, comprising: provide Semiconductor substrate, described Semiconductor substrate has first area and second area; The front of the Semiconductor substrate of first area forms cmos device; Form the first medium layer covering described Semiconductor substrate and cmos device; In the first medium layer of first area, form the first connector, the first connector is connected with cmos device; Form the through-hole interconnection structure running through the first medium layer of second area and the Semiconductor substrate of segment thickness; Form the second dielectric layer covering described first medium layer, the first connector and through-hole interconnection structure, the first interconnection structure is formed in the second dielectric layer of first area, described first interconnection structure is connected with the first connector, be formed with the second interconnection structure in the second dielectric layer of second area, the second interconnection structure is connected with the top surface of through-hole interconnection structure; The second dielectric layer of first area is formed the first pad, and the first pad is connected with the first interconnection structure, and the second dielectric layer of second area is formed the second pad, and the second pad is connected with the second interconnect architecture; Described second dielectric layer forms MEMS, and one end of MEMS is connected with the first pad, and the other end of MEMS is connected with the second pad; The back side of thinning described Semiconductor substrate, exposes the lower surface of through-hole interconnection structure; The back side of Semiconductor substrate is formed the projection be connected with the lower surface of through-hole interconnection structure.
Optionally, described through-hole interconnection structure comprises diffusion impervious layer and is positioned at the metal level on diffusion impervious layer.
Optionally, the material of described diffusion impervious layer is one or more in Ti, TiN, TaN or Ta, and the material of described metal level is one or more in Al, Cu, Ag, Au, Pt, Ni, Ti or W.
Optionally, the forming process of described first connector and through-hole interconnection structure is: the first medium layer of etching first area, forms the first through hole; The etching first medium layer of second area and the Semiconductor substrate of segment thickness, form the second through hole; Formed and cover described first medium layer and the metal level of filling full first through hole and the second through hole; Planarized described metal level, with first medium layer surface for stop-layer, forms the first connector and through-hole interconnection structure.
Optionally, after formation second through hole, the sidewall being also included in the second through hole forms separation layer.
Optionally, described second dielectric layer is single or multiple lift stacked structure, and described first interconnection structure and the second interconnection structure are single or multiple lift stacked structure.
Optionally, described MEMS is pressure sensor, position sensor, acceleration transducer, gyroscope, sound transducer, optical modulator or crystal oscillator.
Optionally, described projection is soldered ball, or described projection comprises metal column and is positioned at the soldered ball on metal column.
The embodiment of the present invention additionally provides a kind of formation method of MEMS, comprising: provide Semiconductor substrate, and described Semiconductor substrate has first area and second area; The front of the Semiconductor substrate of first area forms cmos device; Form the dielectric layer covering described Semiconductor substrate and cmos device, be formed with the first interconnection structure in the dielectric layer of first area, described first interconnection structure is connected with cmos device, is formed with the second interconnection structure in the dielectric layer of second area; The dielectric layer of first area is formed the first pad, and the first pad is connected with the first interconnection structure, and the dielectric layer of second area is formed the second pad, and the second pad is connected with the second interconnect architecture; Described dielectric layer forms MEMS, and one end of MEMS is connected with the first pad, and the other end of MEMS is connected with the second pad; The back side of the Semiconductor substrate of etching second area and certain media layer, form the through hole of exposure second interconnection structure; In described through hole and on the back side of part semiconductor substrate, form through-hole interconnection structure, through-hole interconnection structure is connected with the second interconnection structure; The through-hole interconnection structure at the Semiconductor substrate back side forms projection.
Optionally, described through-hole interconnection structure comprises diffusion impervious layer and is positioned at the metal level on diffusion impervious layer.
Optionally, the forming process of described through-hole interconnection structure is: on the sidewall of described through hole and the backside surface of bottom and Semiconductor substrate, form diffusion impervious layer; Described diffusion impervious layer forms metal level; Formed and cover described metal level and the 3rd dielectric layer of filling full through hole; Planarized described 3rd dielectric layer, exposes the surface of metal level.
Optionally, before formation through-hole interconnection structure, on the back side of described Semiconductor substrate and on the sidewall of through hole, separation layer is formed.
Optionally, the material of described separation layer is silica, silicon nitride or silicon oxynitride.
Optionally, the technique forming described separation layer is thermal anneal process, and the gas that thermal anneal process adopts is O
2, N
2or O
2and N
2mist, temperature is 400 ~ 1000 degrees Celsius, and the time is 10 seconds ~ 5 minutes.
Optionally, described second interconnection structure is multilayer lamination structure, and described through hole exposes the surface of the bottom metal layer of the second interconnection structure.
Present invention also offers a kind of MEMS, comprising: Semiconductor substrate, described Semiconductor substrate has first area and second area, and the front of the Semiconductor substrate of first area is formed with cmos device; Cover the dielectric layer of described Semiconductor substrate and cmos device, be formed with the first interconnection structure in the dielectric layer of first area, described first interconnection structure is connected with cmos device, is formed with the second interconnection structure in the dielectric layer of second area; Be positioned at the first pad on the dielectric layer of first area, the first pad is connected with the first interconnection structure, and be positioned at the second pad on the dielectric layer of second area, the second pad is connected with the second interconnect architecture; Be positioned at the MEMS on dielectric layer, one end of MEMS is connected with the first pad, and the other end of MEMS is connected with the second pad; Run through the Semiconductor substrate of second area and the through-hole interconnection structure of certain media layer, described through-hole interconnection structure is connected with the second interconnection structure; Be positioned at the projection that the Semiconductor substrate back side is connected with through-hole interconnection structure.
Optionally, described through-hole interconnection structure comprises diffusion impervious layer and is positioned at the metal level on diffusion impervious layer.
Optionally, described through-hole interconnection structure and between dielectric layer and Semiconductor substrate, there is separation layer.
Optionally, the back side of described Semiconductor substrate also has the wiring layer be again connected with through-hole interconnection structure, described projection is positioned on wiring layer again.
Optionally, described second interconnection structure is multilayer lamination structure, and described through-hole interconnection structure is connected with the bottom metal layer of the second interconnection structure.
Compared with prior art, technical scheme of the present invention has the following advantages:
MEMS of the present invention, by the second interconnection structure and through-hole interconnection structure and projection, the port be connected with other circuit outside or other chips of MEMS is caused the back side of Semiconductor substrate, compared to existing lead-in wire Joining Technology, need other spaces occupying MEMS both sides, save the volume that MEMS occupies, improve the integrated level of device.
Further, described through-hole interconnection structure and have separation layer between dielectric layer and Semiconductor substrate, improves the electric isolation effect between through-hole interconnection structure and Semiconductor substrate.
The formation method of MEMS of the present invention, through-hole interconnection structure can be formed when formation the first connector, or the back side of via etch Semiconductor substrate and certain media layer form through hole, then through-hole interconnection structure is formed in through-holes, the manufacture craft of through-hole interconnection structure and existing ic manufacturing process compatibility, formation process is simple, by the through-hole interconnection structure that formed, the link of the port of MEMS is caused the back side of Semiconductor substrate, saves the volume that device occupies.
Accompanying drawing explanation
Fig. 1 ~ Fig. 7 is the cross-sectional view of the forming process of first embodiment of the invention MEMS;
Fig. 8 ~ Figure 13 is the cross-sectional view of the forming process of second embodiment of the invention MEMS.
Detailed description of the invention
Be connected with other circuit by lead-in wire technique during the MEMS of prior art, the volume that MEMS is occupied is comparatively large, is unfavorable for the raising of device integration.
The invention provides a kind of MEMS and forming method thereof, form cmos device and MEMS in the front of Semiconductor substrate; Then by the silicon through hole interconnect structure that runs through Semiconductor substrate and certain media layer, the electric connection point of MEMS is caused the back side of Semiconductor substrate, thus reduce the volume of whole MEMS, improve the integrated level of MEMS.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.When describing the embodiment of the present invention in detail, for ease of illustrating, schematic diagram can be disobeyed general ratio and be made partial enlargement, and described schematic diagram is example, and it should not limit the scope of the invention at this.In addition, the three-dimensional space of length, width and the degree of depth should be comprised in actual fabrication.
First embodiment
Fig. 1 ~ Fig. 7 is the cross-sectional view of the forming process of first embodiment of the invention MEMS.
With reference to figure 1, provide Semiconductor substrate 200, described Semiconductor substrate 200 has first area 21 and second area 22; The front of the Semiconductor substrate 200 of first area 21 forms cmos device 201.
The material of described Semiconductor substrate 200 can be silicon (Si), germanium (Ge) or SiGe (GeSi), carborundum (SiC); Also can be silicon-on-insulator (SOI), germanium on insulator (GOI); Or can also be other material, such as GaAs etc. III-V compounds of group.In the present embodiment, described Semiconductor substrate 200 is silicon substrate.
Described Semiconductor substrate 200 comprises first area 21 and second area 22, first area 21 for the formation of cmos device, in formation through-hole interconnection structure after in second area 22.First area 21 and second area 22 can be adjacent or non-conterminous.
The front of the Semiconductor substrate 200 of first area 21 forms cmos device 201, and described cmos device 201 is as a part for control circuit, and described control circuit is used for the MEMS exhaust control signal to follow-up formation.
In the present embodiment, with transistor be cmos device 201 exemplarily, described transistor comprise in nmos pass transistor or PMOS transistor one or both, in other embodiments of the invention, described cmos device also comprises other semiconductor devices in addition to a transistor.
Described transistor comprises the gate dielectric layer be positioned on the first surface 21 of Semiconductor substrate 200, the gate electrode be positioned on gate dielectric layer, is positioned at the side wall on gate dielectric layer and gate electrode both sides sidewall and is positioned at the source-drain area of Semiconductor substrate of gate electrode and side wall both sides.Described gate dielectric layer material can be silica or high-k dielectric material, and the material of described gate electrode can be polysilicon or metal material.
Fleet plough groove isolation structure (not shown) can also be formed, for isolating adjacent active area in the first area 21 of described Semiconductor substrate 200.Also fleet plough groove isolation structure can be formed, the electric isolation of the through-hole interconnection structure that the cmos device 201 formed for first area 21 and follow-up second area are formed in Semiconductor substrate between first area 21 and second area 22.
With reference to figure 2, form the first medium layer 202 covering described Semiconductor substrate 200 and cmos device 201; The first medium layer 202 of etching first area 21, forms the first through hole 203; The etching first medium layer 202 of second area 22 and the Semiconductor substrate 200 of segment thickness, form the second through hole 204.
Described first medium layer 202 is formed by deposition or spin coating proceeding, and the material of described first medium layer 202 comprises SiO
2, SiON, SiCN, SiC, SiN, in low-K dielectric material one or more.The dielectric constant of described high-k dielectric material is less than 3.9, can be such as dielectric material (as SiOC), organic polymer, the lucite (OSG) of carbon dope, mix fluorine glass (FSG) etc.
Described first through hole 203 and the second through hole 204 are formed by different process step, and the process that the first through hole 203 and the second through hole 204 are formed is: on first medium layer 202, form the first patterned mask layer, such as photoresist mask; With described first patterned mask layer for mask, the first medium layer 202 of etching first area 21, form the first through hole 203 exposing cmos device active area, in the present embodiment, described first through hole 203 comprises the first sub-through hole on the grid structure surface of exposed transistor, and the second sub-through hole on the source region of exposed transistor or surface, drain region; Remove described first patterned mask layer, described first medium layer 202 forms the mask layer of second graphical, such as photoresist mask; With the mask layer of described second graphical for mask, the first medium layer 202 of etching second area and part semiconductor substrate 200, form the second through hole 204; Remove the mask layer of second graphical.In other embodiments of the invention, also first can form the second through hole 204, then form the first through hole 203.
With reference to figure 3, at described first through hole 203(with reference to figure 2) middle formation the first connector 205, first connector 205 is connected with cmos device, in the second through hole 204, (with reference to figure 2) forms through-hole interconnection structure 208, and through-hole interconnection structure 208 runs through the first medium layer 202 of second area 22 and the Semiconductor substrate 200 of segment thickness.
The metal level 206 that described through-hole interconnection structure 208 comprises diffusion impervious layer 207 and is positioned on diffusion impervious layer 207, described diffusion impervious layer 207 spreads in first medium layer 202 or Semiconductor substrate 200 for preventing the metal in metal level 206.The material of described diffusion impervious layer 207 is one or more in Ti, TiN, TaN or Ta, and the material of described metal level 206 is one or more in Al, Cu, Ag, Au, Pt, Ni, Ti or W.
Described first connector 205 and through-hole interconnection structure 208 are that same step is formed, and the forming process of the first connector 205 and through-hole interconnection structure 208 is: on described first medium layer 202 surface, the first through hole 203 and the second through hole 204 sidewall and lower surface, form diffusion impervious layer; Described diffusion impervious layer forms metal level, and described metal level fills full first through hole 203 and the second through hole 204; Planarized described metal level and diffusion impervious layer, with first medium layer 202 surface for stop-layer, form the first connector 205, in the second through hole 204, form through-hole interconnection structure 208 in the first through hole 203.
Before formation through-hole interconnection structure 208, can also form separation layer (not shown) at the sidewall of the second through hole 204, described separation layer is used for electric isolation through-hole interconnection structure 208 and Semiconductor substrate 200.The material of described separation layer can be silica, silicon nitride or silicon oxynitride, and the material of described separation layer also can be the material of other etchings.In the present embodiment, described separation layer can be formed by oxidation or nitriding process, namely in the atmosphere of oxygen, nitrogen or both mists, Semiconductor substrate 200 is annealed, in sidewall and bottom formation separation layer (described separation layer can be silicon oxide layer, silicon nitride layer or silicon oxynitride) of the second through hole 204, separation layer bottom second through hole 204 can be removed when the back side of subsequent planarization Semiconductor substrate 200 exposes the bottom of through-hole interconnection structure, without the need to adopting extra etching technics, formation process is simple, saves cost of manufacture.
In other embodiments of the invention, also separation layer can be formed by deposition with without mask etching technique at the sidewall of the second through hole.
In the present embodiment, after formation first medium layer 202, when forming the first connector 205, form through-hole interconnection structure 208, the degree of depth too technology difficulty come of bathozone during to reduce formation the second through hole 204 simultaneously.Follow-uply on first medium layer 202, form second dielectric layer, the second interconnection structure is formed in second dielectric layer, through-hole interconnection structure 208 is connected with one end of the MEMS in second dielectric layer by the second interconnection structure, thus, by the second interconnection structure and through-hole interconnection structure, the electricity output of MEMS is caused the back side of Semiconductor substrate 200, after forming at the back side of Semiconductor substrate the projection (solder joint) be connected with through-hole interconnection structure 208, the connection with other external circuits or chip can be realized by projection, compared to the mode connected by lead-in wire, save the area that MEMS occupies.
With reference to figure 4, form the second dielectric layer 215 covering described first medium layer 202, first connector 205 and through-hole interconnection structure 208, the first interconnection structure 211 is formed in the second dielectric layer 215 of first area 21, described first interconnection structure 211 is connected with the first connector 205, be formed with the second interconnection structure 214, second interconnection structure 214 in the second dielectric layer 215 of second area 22 to be connected with the top surface of through-hole interconnection structure 208; The second dielectric layer 215 of first area 21 is formed the first pad 217, first pad 217 be connected with the first interconnection structure 211, the second dielectric layer 215 of second area 22 is formed the second pad 218, second pad 218 and is connected with the second interconnect architecture 214; Described second dielectric layer 215 forms MEMS 219, and one end of MEMS 219 is connected with the first pad 217, and the other end of MEMS 219 is connected with the second pad 218.
Described second dielectric layer 215 can be single or multiple lift stacked structure, and the first interconnection structure 211 formed in corresponding second dielectric layer 215 and the second interconnection structure 214 are also single or multiple lift stacked structure.When first interconnection structure 211 and the second interconnection structure 214 are multilayer lamination structure, comprise multiple-level stack metal level and by the connector of the layer metal interconnection of adjacent layer.Described first medium layer 202 and second dielectric layer 215 form dielectric layer.
Described first interconnection structure 211 is for one end interconnection of the MEMS of cmos device or follow-up formation, and described second interconnection structure 214 interconnects for the other end of through-hole interconnection structure 208 with MEMS.
In the present embodiment, with the first interconnection structure 211 of the second dielectric layer 215 of individual layer and individual layer and the second interconnection structure 214 exemplarily.The connector that described first interconnection structure 211 comprises bottom metal layer 209, top layer metallic layer 210 and is connected with top layer metallic layer 210 by bottom metal layer 209, in the present embodiment, the first connector 205 be connected with cmos device is as a part for the first interconnection structure 211.The connector that described second interconnection structure 214 comprises bottom metal layer 212, top layer metallic layer 213 and is connected with top layer metallic layer 213 by bottom metal layer 212.
In one embodiment, described second dielectric layer 215 can also be formed with the passivation layer 216 covering described first pad 217 and the second pad 218, there is in described passivation layer 216 opening exposing described first pad 217 and the second pad 218.Described passivation layer 216 can also be formed the covering layer 220 protecting described MEMS.
Described MEMS 219 is by passivation layer 216 in bonding technology and second dielectric layer 215(or second dielectric layer 215) form as one, one end (such as control signal input) of MEMS 219 is connected with the first pad 217, the other end of MEMS 219 (such as gather or transducing signal output, or with the communication ends of other circuit) is connected with the second pad 218.MEMS 219 please refer to the bonding technology of prior art with the bonding technology of second dielectric layer 215, does not repeat them here.
Described MEMS 219 can be pressure sensor, position sensor, acceleration transducer, gyroscope, sound transducer, optical modulator or crystal oscillator etc.Described MEMS 219 can also be other MEMS.It should be noted that, the kind of MEMS 219 should not limit the scope of the invention.
With reference to figure 5, the back side of thinning described Semiconductor substrate 200, exposes the lower surface of through-hole interconnection structure 208.
The back side of thinning described Semiconductor substrate 200 can adopt chemical mechanical milling tech or return etching technics.
With reference to figure 6 and Fig. 7, the back side of Semiconductor substrate 200 forms the projection 223 be connected with the lower surface of through-hole interconnection structure 208.
Described projection 223 can be formed directly into the top surface of through-hole interconnection structure 208.
In the present embodiment, described projection 223 passes through wiring layer 221 again and is connected with the top surface of through-hole interconnection structure 208.After the back side of Semiconductor substrate 200 forms wiring layer 221 again, the passivation layer 222 on the back side that covers described Semiconductor substrate 200 and wiring layer 221 surface again can be formed, there is in described passivation layer 222 opening on expose portion wiring layer 221 surface again, form projection 223 in the opening.
Described projection 223 is soldered ball, and described projection 223 is formed by screen printing and reflux technique.
In other embodiments of the invention, described projection 223 comprises the metal column be located at again on wiring layer 221 and the soldered ball being positioned at metal column top surface.
The MEMS that said method is formed, please refer to Fig. 7, comprising:
Semiconductor substrate 200, described Semiconductor substrate 200 has first area 21 and second area 22, and the front of the Semiconductor substrate 200 of first area 21 is formed with cmos device 201;
Cover the dielectric layer of described Semiconductor substrate 200 and cmos device 201, the second dielectric layer 215 that described dielectric layer comprises first medium layer 202 and is positioned in second dielectric layer 202, the first interconnection structure 211 is formed in the dielectric layer of first area 21, described first interconnection structure 211 is connected with cmos device 201, is formed with the second interconnection structure 214 in the dielectric layer of second area 22;
The first pad 217, first pad 217 be positioned on the dielectric layer of first area 21 is connected with the first interconnection structure 211, and the second pad 218, second pad 218 be positioned on the dielectric layer of second area 22 is connected with the second interconnect architecture 214;
Be positioned at the MEMS 219 on dielectric layer, one end of MEMS 219 is connected with the first pad 217, and the other end of MEMS 219 is connected with the second pad 218;
Run through the back side of the Semiconductor substrate 200 of second area 22 and the through-hole interconnection structure 208 of certain media layer, described through-hole interconnection structure 208 is connected with the second interconnection structure 214;
Be positioned at the projection 223 that Semiconductor substrate 200 back side is connected with through-hole interconnection structure 208.
Concrete, the metal level 206 that described through-hole interconnection structure 208 comprises diffusion impervious layer 207 and is positioned on diffusion impervious layer 207.
Described through-hole interconnection structure 208 and between dielectric layer and Semiconductor substrate 200, there is separation layer (not shown).
Described second dielectric layer 215 is single or multiple lift stacked structure, and accordingly, described first interconnection structure 211 or the second interconnection structure 214 are single or multiple lift stacked structure.When described second interconnection structure 214 is multilayer lamination structure, described second interconnection structure 214 comprises bottom metal layer 212, and through-hole interconnection structure 208 is connected with bottom metal layer 212.
In the present embodiment, described second dielectric layer 215 is single layer structure, described first interconnection structure 211 and the second interconnection structure 214 are also single layer structure, the connector that described first interconnection structure 211 comprises bottom metal layer 209, top layer metallic layer 210 and is connected with top layer metallic layer 210 by bottom metal layer 209, in the present embodiment, the first connector 205 be connected with cmos device is as a part for the first interconnection structure 211.The connector that described second interconnection structure 214 comprises bottom metal layer 212, top layer metallic layer 213 and is connected with top layer metallic layer 213 by bottom metal layer 212.
The back side of described Semiconductor substrate 200 also has the wiring layer again 221 be connected with through-hole interconnection structure 208, described projection 223 is positioned on wiring layer 221 again.
Described second dielectric layer 215 also has passivation layer 216, and described passivation layer 216 also has covering layer 220.
Described projection 223 can be connected with other circuit or other chips, compared to existing lead-in wire Joining Technology, need other spaces occupying MEMS both sides, the MEMS of the embodiment of the present invention, by the second interconnection structure 214 and through-hole interconnection structure 208 and projection 223, the port be connected with other circuit outside or other chips of MEMS 219 is caused the back side of Semiconductor substrate 200, save the volume that MEMS occupies, improve the integrated level of device.
Second embodiment
Fig. 8 ~ Figure 13 is the cross-sectional view of the forming process of second embodiment of the invention MEMS.
With reference to figure 8, provide Semiconductor substrate 300, described Semiconductor substrate 300 has first area 31 and second area 32; The front of the Semiconductor substrate 300 of first area 31 forms cmos device 301; Form the dielectric layer covering described Semiconductor substrate 300 and cmos device 301, described dielectric layer comprises first medium layer 302 and second dielectric layer 315, the first interconnection structure 311 is formed in the dielectric layer of first area 31, first connector 305 is as a part for the first interconnection structure 311, described first interconnection structure 311 is connected with cmos device 301, is formed with the second interconnection structure 314 in the dielectric layer of second area 32; The dielectric layer of first area 31 is formed the first pad 317, first pad 317 be connected with the first interconnection structure 311, the dielectric layer of second area 32 is formed the second pad 318, second pad 318 and is connected with the second interconnect architecture 314; Described dielectric layer is formed MEMS 319, and one end of MEMS 319 is connected with the first pad 317, and the other end of MEMS 319 is connected with the second pad 318.
Described second dielectric layer 315 can be single or multiple lift stacked structure, and the first interconnection structure 311 formed in corresponding second dielectric layer 315 and the second interconnection structure 314 are also single or multiple lift stacked structure.When first interconnection structure 311 and the second interconnection structure 314 are multilayer lamination structure, comprise multiple-level stack metal level and by the connector of the layer metal interconnection of adjacent layer.Be formed with the first connector 305 that cmos device 301 connects in the first medium layer 202 of first area 31, described first connector 305 is as a part for the first interconnection structure 311.
In the present embodiment, with the first interconnection structure 311 of the second dielectric layer 315 of individual layer and individual layer and the second interconnection structure 314 exemplarily.The connector that described first interconnection structure 311 comprises bottom metal layer 309, top layer metallic layer 310 and is connected with top layer metallic layer 310 by bottom metal layer 309.The connector that described second interconnection structure 314 comprises bottom metal layer 312, top layer metallic layer 313 and is connected with top layer metallic layer 313 by bottom metal layer 312.
In one embodiment, described second dielectric layer 315 can also be formed with the passivation layer 316 covering described first pad 317 and the second pad 318, there is in described passivation layer 316 opening exposing described first pad 317 and the second pad 318.Described passivation layer 316 can also be formed the covering layer 330 protecting described MEMS 319.
Described MEMS 319 is by passivation layer 316 in bonding technology and second dielectric layer 315(or second dielectric layer 315) form as one, one end (such as control signal input) of MEMS 319 is connected with the first pad 317, the other end of MEMS 319 (such as gather or transducing signal output, or with the communication ends of other circuit) is connected with the second pad 318.MEMS 319 please refer to the bonding technology of prior art with the bonding technology of second dielectric layer 315, does not repeat them here.
Described MEMS 319 can be pressure sensor, position sensor, acceleration transducer, gyroscope, sound transducer, optical modulator or crystal oscillator etc.Described MEMS 319 can also be other MEMS.It should be noted that, the kind of MEMS 319 should not limit the scope of the invention.
With reference to figure 9, the back side of the Semiconductor substrate 300 of etching second area 2 and certain media layer, form the through hole 303 of exposure second interconnection structure 314.
The back side of etch semiconductor substrates 300 and certain media layer using plasma etching technics.The through hole 303 that etching is formed can have vertical sidewall or sloped sidewall.
The present embodiment, exposes the bottom metal layer 312 of the second interconnection structure 314, thus reduces the etching depth of through hole 303, reduce the difficulty of etching technics during described through hole 303.
Before the described Semiconductor substrate 300 of etching and certain media layer, also comprise: carry out thinning to the back side of described Semiconductor substrate 300.Described reduction process can be chemical mechanical milling tech.
With reference to Figure 10 and Figure 11, in described through hole 303 and on the back side of part semiconductor substrate 300, form through-hole interconnection structure 307, through-hole interconnection structure 307 is connected with the second interconnection structure 314.
The metal level 306 that described through-hole interconnection structure 307 comprises diffusion impervious layer 305 and is positioned on diffusion impervious layer 305.The material of described diffusion impervious layer 305 is one or more in Ti, TiN, TaN or Ta, and the material of described metal level 306 is one or more in Al, Cu, Ag, Au, Pt, Ni, Ti, W, WN, Wsi.
In other embodiments of the invention, described through-hole interconnection structure can only include metal level, described metal level to be material be in Al, Ag, Au, Pt, Ni, Ti, TiN, TaN, Ta, TaC, TaSiN, W, WN, Wsi one or more.
In the present embodiment, described metal level 306 does not fill full through hole 303, and in other embodiments of the invention, described metal level fills full through hole 303.
The forming process of described through-hole interconnection structure 307 is: on the sidewall of described through hole 303 and the backside surface of bottom and Semiconductor substrate 300, form diffusion impervious layer 305; Described diffusion impervious layer 305 forms metal level 306.
In the present embodiment, before formation through-hole interconnection structure 307, on the back side of described Semiconductor substrate 300 and on the sidewall of through hole 303, form separation layer 304.Described separation layer 304 is for through-hole interconnection structure 307 and the electric isolation between Semiconductor substrate 300 and dielectric layer.
The material of described separation layer 304 can be silica, silicon nitride or silicon oxynitride.Described separation layer 304 can also be other suitable materials.
In this example, the technique forming described separation layer 304 is thermal anneal process, and the gas that thermal anneal process adopts is O
2, N
2or O
2and N
2mist, temperature is 400 ~ 1000 degrees Celsius, time is 10 seconds ~ 5 minutes, bottom due to through hole 303 is bottom metal layer 312, therefore thermal annealing is adopted only can to form separation layer at the sidewall of through hole 303 and the back side of Semiconductor substrate 300, formation process is simple, and in annealing process the temperature lower time very short, less to the damage of bottom metal layer 312.
In other embodiments of the invention, deposition and etching technics also can be adopted to form described separation layer.
Then, please refer to Figure 12, formed and cover described metal level 306 and fill full through hole 303(with reference to Figure 11) the 3rd dielectric layer 308; Planarized described 3rd dielectric layer 308, exposes the surface of metal level 306.
Described 3rd dielectric layer 308 can be silica or silicon nitride etc.
In the present embodiment, during planarized described 3rd dielectric layer, using the metal level 306 at Semiconductor substrate 300 back side as stop-layer, metal level 306 on Semiconductor substrate 300 back side can as wiring layer again, can by the metal level 306 at photoetching and etching technics patterned semiconductor substrate 300 back side, formed need at wiring layer.
In other embodiments of the invention, during planarized described 3rd dielectric layer, can using the separation layer 304 at Semiconductor substrate 300 back side as stop-layer, remove the diffusion impervious layer 305 on Semiconductor substrate 300 back side and metal level 306, follow-uply to be formed and metal level 306 diffusion impervious layer 305 in the through-hole interconnection structure 307(through hole in through hole on the back side of Semiconductor substrate 300) wiring layer again that is connected, described in the part of wiring layer as through-hole interconnection structure.
With reference to Figure 13, the through-hole interconnection structure 307 at Semiconductor substrate 300 back side forms projection 322.
Before formation projection 322, passivation layer 323 can be formed on described metal level 306 and the 3rd dielectric layer 308, there is in described passivation layer 323 opening on expose metal layer 306 surface, and then in opening, form projection 322.
Described projection 322 is soldered ball, and described projection 322 is formed by screen printing and reflux technique.
In other embodiments of the invention, described projection comprises the metal column be located on wiring layer and the soldered ball being positioned at metal column top surface.
In other embodiments of the invention, when the diffusion impervious layer 305 on described Semiconductor substrate 300 back side and metal level 306 are removed at planarized 3rd dielectric layer, first need to form the wiring layer be again connected with diffusion impervious layer 305 with the metal level 306 in through hole at the back side of Semiconductor substrate 300, then on wiring layer, forming projection.
The MEMS that said method is formed, please refer to Figure 13, comprising:
Semiconductor substrate 300, described Semiconductor substrate 300 has first area 31 and second area 32, and the front of the Semiconductor substrate 300 of first area 31 is formed with cmos device 301;
Cover the dielectric layer of described Semiconductor substrate 300 and cmos device 301, described dielectric layer comprises first medium layer 302 and second dielectric layer 315, the first interconnection structure 311 is formed in the dielectric layer of first area 31, described first interconnection structure is connected with cmos device 301, is formed with the second interconnection structure 314 in the dielectric layer of second area 32;
The first pad 317, first pad 317 be positioned on the dielectric layer of first area 31 is connected with the first interconnection structure 311, and the second pad 318, second pad 318 be positioned on the dielectric layer of second area 32 is connected with the second interconnect architecture 314;
Be positioned at the MEMS 319 on dielectric layer, one end of MEMS 319 is connected with the first pad 317, and the other end of MEMS 319 is connected with the second pad 318;
Run through the back side of the Semiconductor substrate of second area and the through hole of certain media layer, described through hole exposes the second interconnection structure 314;
Be positioned at through-hole interconnection structure 307 on the sidewall of described through hole and bottom and part semiconductor substrate 300 back side, described through-hole interconnection structure is connected with the second interconnection structure 314;
The projection 322 that the Semiconductor substrate back side is connected with through-hole interconnection structure 314.
Concrete, the metal level 307 that described through-hole interconnection structure 307 comprises diffusion impervious layer 305 and is positioned on diffusion impervious layer 305.
Have the first connector 305, first connector 305 in the first medium layer 302 of described first area 31 to be connected with cmos device 301, described first connector 305 is as a part for the first interconnection structure 311.
Described through-hole interconnection structure 307 and between dielectric layer and Semiconductor substrate 300, there is separation layer 304.
Described second dielectric layer 315 is single or multiple lift stacked structure, and accordingly, described first interconnection structure 311 or the second interconnection structure 314 are single or multiple lift stacked structure.When described second interconnection structure 314 is multilayer lamination structure, described second interconnection structure 314 comprises bottom metal layer 312, and through-hole interconnection structure 307 is connected with bottom metal layer 312.
In the present embodiment, described second dielectric layer 315 is single layer structure, described first interconnection structure 311 and the second interconnection structure 314 are also single layer structure, the connector that described first interconnection structure 311 comprises bottom metal layer 309, top layer metallic layer 310 and is connected with top layer metallic layer 310 by bottom metal layer 309.The connector that described second interconnection structure 314 comprises bottom metal layer 312, top layer metallic layer 313 and is connected with top layer metallic layer 313 by bottom metal layer 312.
Described second dielectric layer 315 also has passivation layer 316, and described passivation layer 316 also has covering layer 330.
The back side of described Semiconductor substrate 300 also has passivation layer 323.
Described projection 322 can be connected with other circuit or other chips, compared to existing lead-in wire Joining Technology, need other spaces occupying MEMS both sides, the MEMS of the embodiment of the present invention, by the second interconnection structure 314 and through-hole interconnection structure 3078 and projection 322, the port be connected with other circuit outside or other chips of MEMS 319 is caused the back side of Semiconductor substrate 300, save the volume that MEMS occupies, improve the integrated level of device.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (20)
1. a formation method for MEMS, is characterized in that, comprising:
There is provided Semiconductor substrate, described Semiconductor substrate has first area and second area;
The front of the Semiconductor substrate of first area forms cmos device;
Form the first medium layer covering described Semiconductor substrate and cmos device;
In the first medium layer of first area, form the first connector, the first connector is connected with cmos device;
Form the through-hole interconnection structure running through the first medium layer of second area and the Semiconductor substrate of segment thickness;
Form the second dielectric layer covering described first medium layer, the first connector and through-hole interconnection structure, the first interconnection structure is formed in the second dielectric layer of first area, described first interconnection structure is connected with the first connector, be formed with the second interconnection structure in the second dielectric layer of second area, the second interconnection structure is connected with the top surface of through-hole interconnection structure;
The second dielectric layer of first area is formed the first pad, and the first pad is connected with the first interconnection structure, and the second dielectric layer of second area is formed the second pad, and the second pad is connected with the second interconnect architecture;
Described second dielectric layer forms MEMS, and one end of MEMS is connected with the first pad, and the other end of MEMS is connected with the second pad;
The back side of thinning described Semiconductor substrate, exposes the lower surface of through-hole interconnection structure;
The back side of Semiconductor substrate is formed the projection be connected with the lower surface of through-hole interconnection structure.
2. the formation method of MEMS as claimed in claim 1, is characterized in that, described through-hole interconnection structure comprises diffusion impervious layer and is positioned at the metal level on diffusion impervious layer.
3. the formation method of MEMS as claimed in claim 2, it is characterized in that, the material of described diffusion impervious layer is one or more in Ti, TiN, TaN or Ta, and the material of described metal level is one or more in Al, Cu, Ag, Au, Pt, Ni, Ti or W.
4. the formation method of MEMS as claimed in claim 1, it is characterized in that, the forming process of described first connector and through-hole interconnection structure is: the first medium layer of etching first area, forms the first through hole; The etching first medium layer of second area and the Semiconductor substrate of segment thickness, form the second through hole; Formed and cover described first medium layer and the metal level of filling full first through hole and the second through hole; Planarized described metal level, with first medium layer surface for stop-layer, forms the first connector and through-hole interconnection structure.
5. the formation method of MEMS as claimed in claim 4, is characterized in that, after formation second through hole, also comprise: form separation layer at the sidewall of the second through hole.
6. the formation method of MEMS as claimed in claim 1, it is characterized in that, described second dielectric layer is single or multiple lift stacked structure, and described first interconnection structure and the second interconnection structure are single or multiple lift stacked structure.
7. the formation method of MEMS as claimed in claim 1, it is characterized in that, described MEMS is pressure sensor, position sensor, acceleration transducer, gyroscope, sound transducer, optical modulator or crystal oscillator.
8. the formation method of MEMS as claimed in claim 1, it is characterized in that, described projection is soldered ball, or described projection comprises metal column and is positioned at the soldered ball on metal column.
9. a formation method for MEMS, is characterized in that, comprising:
There is provided Semiconductor substrate, described Semiconductor substrate has first area and second area;
The front of the Semiconductor substrate of first area forms cmos device;
Form the dielectric layer covering described Semiconductor substrate and cmos device, be formed with the first interconnection structure in the dielectric layer of first area, described first interconnection structure is connected with cmos device, is formed with the second interconnection structure in the dielectric layer of second area;
The dielectric layer of first area is formed the first pad, and the first pad is connected with the first interconnection structure, and the dielectric layer of second area is formed the second pad, and the second pad is connected with the second interconnect architecture;
Described dielectric layer forms MEMS, and one end of MEMS is connected with the first pad, and the other end of MEMS is connected with the second pad;
The back side of the Semiconductor substrate of etching second area and certain media layer, form the through hole of exposure second interconnection structure;
In described through hole and on the back side of part semiconductor substrate, form through-hole interconnection structure, through-hole interconnection structure is connected with the second interconnection structure;
The through-hole interconnection structure at the Semiconductor substrate back side forms projection.
10. the formation method of MEMS as claimed in claim 9, is characterized in that, described through-hole interconnection structure comprises diffusion impervious layer and is positioned at the metal level on diffusion impervious layer.
The formation method of 11. MEMS as claimed in claim 10, it is characterized in that, the forming process of described through-hole interconnection structure is: on the sidewall of described through hole and the backside surface of bottom and Semiconductor substrate, form diffusion impervious layer; Described diffusion impervious layer forms metal level; Formed and cover described metal level and the 3rd dielectric layer of filling full through hole; Planarized described 3rd dielectric layer, exposes the surface of metal level.
The formation method of 12. MEMS as claimed in claim 9, is characterized in that, before formation through-hole interconnection structure, on the back side of described Semiconductor substrate and on the sidewall of through hole, forms separation layer.
The formation method of 13. MEMS as claimed in claim 12, is characterized in that, the material of described separation layer is silica, silicon nitride or silicon oxynitride.
The formation method of 14. MEMS as claimed in claim 13, is characterized in that, the technique forming described separation layer is thermal anneal process, and the gas that thermal anneal process adopts is O
2, N
2or O
2and N
2mist, temperature is 400 ~ 1000 degrees Celsius, and the time is 10 seconds ~ 5 minutes.
The formation method of 15. MEMS as claimed in claim 9, it is characterized in that, described second interconnection structure is multilayer lamination structure, and described through hole exposes the surface of the bottom metal layer of the second interconnection structure.
16. 1 kinds of MEMS, is characterized in that, comprising:
Semiconductor substrate, described Semiconductor substrate has first area and second area, and the front of the Semiconductor substrate of first area is formed with cmos device;
Cover the dielectric layer of described Semiconductor substrate and cmos device, be formed with the first interconnection structure in the dielectric layer of first area, described first interconnection structure is connected with cmos device, is formed with the second interconnection structure in the dielectric layer of second area;
Be positioned at the first pad on the dielectric layer of first area, the first pad is connected with the first interconnection structure, and be positioned at the second pad on the dielectric layer of second area, the second pad is connected with the second interconnect architecture;
Be positioned at the MEMS on dielectric layer, one end of MEMS is connected with the first pad, and the other end of MEMS is connected with the second pad;
Run through the Semiconductor substrate of second area and the through-hole interconnection structure of certain media layer, described through-hole interconnection structure is connected with the second interconnection structure;
Be positioned at the projection that the Semiconductor substrate back side is connected with through-hole interconnection structure.
17. MEMS as claimed in claim 16, is characterized in that, described through-hole interconnection structure comprises diffusion impervious layer and is positioned at the metal level on diffusion impervious layer.
18. MEMS as claimed in claim 16, is characterized in that, described through-hole interconnection structure and have separation layer between dielectric layer and Semiconductor substrate.
19. MEMS as claimed in claim 16, it is characterized in that, the back side of described Semiconductor substrate also has the wiring layer be again connected with through-hole interconnection structure, described projection is positioned on wiring layer again.
20. MEMS as claimed in claim 16, it is characterized in that, described second interconnection structure is multilayer lamination structure, and described through-hole interconnection structure is connected with the bottom metal layer of the second interconnection structure.
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