JP2005142182A - Optical semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an optical semiconductor integrated element structure for avoiding problems in the structure such as overhanging growth over a mask due to a dielectric mask area and surface orientation dependency of growth speed of a buried regrowing layer and an increase in the growth speed at a mask end, and to provide its manufacturing method. <P>SOLUTION: The dielectric mask (dummy mask) is formed on the side of a region where a large buried layer thickness is required to concentrate a stock material to a specific region, thereby increasing the thickness of the required region. Thus, the thickness at the mask end parallel to [1-10] or a region with a large mask area where abnormal growth is likely to occur can be minimized, and only the thickness of the required region such as a current constriction can be arbitrarily increased. In the case of a DC-PBH structure, the mask may be formed on an appropriate location on a terrace of a carrier recombination layer. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an optical semiconductor element and a method for manufacturing the same.

In the optical semiconductor integrated device, various elements having functions such as light emission, modulation, amplification, wave guide, and light reception are formed on one substrate, so that the optical function element can be reduced in size, cost and function. It is advantageous. Among these optical semiconductor integrated devices, so-called “monolithic integrated devices” that integrate all devices using only process technologies such as crystal growth, lithography, etching, and film formation can be mass-produced if manufacturing technology is established. It is easy, and significant cost reduction and miniaturization can be expected. A typical example of an integrated device that has already been put to practical use is a modulator integrated light source in which a light modulator is integrated in a semiconductor laser. In this modulation integrated light source, for example, as shown in Non-Patent Document 1 (page 74, FIG. 5.8), a semiconductor laser and an optical modulator are formed by butt coupling (butt joint). The semiconductor laser portion and the optical modulator portion can be separately manufactured with an optimum structure. That is, in FIG. 1, first, an optical waveguide layer including a multiple quantum well (MQW) active layer for a semiconductor laser is formed on a flat substrate, and then a mask is formed only on a portion where a laser is to be formed. Other portions are removed by selective etching to form grooves. Next, an optical waveguide layer including an MQW active layer for a modulator is formed in the groove portion, mask formation and selective etching for forming a groove for a current confinement layer are performed, and finally a current confinement layer is formed, Finish crystal growth. An example of the element structure of the modulator integrated light source manufactured in this way is shown in FIG. 2 (from Non-Patent Document 1, page 78, FIG. 5.10).
Isao Kobayashi, “Optical Integrated Device”, Kyoritsu Shuppan, July 25, 1999

  The modulator integrated light source is the simplest integrated structure in which two waveguides having the same width are arranged in a straight line, and it is relatively easy to produce a desired structure. In the case of integrating a structure having a curved structure or a structure having a slanted waveguide, the growth rate changes due to the difference in mask area and the growth rate of the buried regrowth crystal is dependent on the plane orientation. Problems such as overgrowth growth and abnormal growth at the edge of the mask occur. As an example, an integrated structure composed of three waveguides WG1, WG2, and WG3 having different widths will be described.

  First, a step of crystal growth of a semiconductor thin film having a double heterostructure, a step of forming a dielectric film on the semiconductor thin film, and a step of forming a desired mask pattern on the semiconductor thin film by photolithography and etching, As shown in FIG. 3, a pattern in which three dielectric masks having widths w (1), w (2), and w (3) (w (1) <w (2) <w (3)) are combined is flashed. It is formed in a direction parallel to the [110] direction on a semiconductor wafer having a double hetero structure of zinc ore type crystal.

  Next, after forming a mesa as shown in FIG. 4 by dry etching, a first buried layer RG1 as shown in FIG. 5 is grown using a metal organic vapor phase epitaxy (MOVPE) method. At this time, cross-sectional views after growth of RG1 along the lines AA, BB, CC, and DD in FIG. 5 are shown in FIGS. 6-1, 6-2, and 6-3, respectively. As shown in FIG. At this time, the maximum buried layer thickness in the cross section where the maximum buried layer thickness in the cross section perpendicular to the waveguide direction of each of the waveguides WG1, WG2, and WG3 is d (1) <d (2) <d (3 ).

Thereafter, the dielectric masks M1, M2, and M3 are removed by wet etching or the like, and a second buried layer RG2 as shown in FIG. 7 is grown. Cross-sectional views after growth of RG2 along the lines AA, BB, CC, and DD in FIG. 7 are shown in FIGS. 8-1, 8-2, 8-3, and FIG. 8-4. As can be seen from FIG. 6-1, FIG. 6-2, FIG. 6-3, and FIG. 6-4, the buried growth layer thickness and shape near the mesa side change due to the difference in the dielectric mask area and mesa direction, The thickness of the regrowth layer increases toward the side of a mesa having a large mask area (for example, a multi-mode interferometer (MMI)), and the mask edge parallel to the direction equivalent to [1-10] The overhanging growth becomes remarkable. That is, of the first buried regrowth layer, the largest buried layer in the cross section where the maximum buried layer thickness in the cross section (in this case, (110) cross section) perpendicular to the waveguide direction of each of the waveguides WG1, WG2, WG3 is the thinnest. The thickness is d (1) <d (2) <d (3). This is because the raw material not consumed on the dielectric mask such as SiO ₂ is transported to the mask edge by vapor phase diffusion or surface diffusion and increases the growth rate in the vicinity of the mask edge. An increase in the growth rate in the vicinity causes overgrowth growth on the mask or a protrusion due to an increase in the growth rate depending on the orientation of the mask edge as shown in FIG. 6-4. When overhang growth occurs, for example, when the mask is removed and the cladding layer is stacked and grown, the growth raw material cannot reach that portion and remains as a cavity V1 as shown in FIG. Such as a crystal defect is proliferated during the operation of the device and causes device deterioration. Further, when the growth rate increases at the edge of the mask and an extreme protrusion is generated, the flatness of the element surface after the regrowth is deteriorated, and the subsequent waveguide formation or electrode formation process becomes difficult.

  The above problem becomes more serious as the degree of integration increases. For example, in a wavelength selective light source as shown in FIG. 18 in which four DFB lasers LD1, LD2, LD3, LD4, an MMI multiplexer MMI1, and a semiconductor amplifier (SOA) SOA1 are integrated, the current block layer of the DFB laser When the block is formed, a block layer is projected on the mask at the S-shaped waveguides S1, S2, S3, and S4, and the coupling portion between the S-shaped waveguides S1, S2, S3, and S4 and the MMI multiplexer MMI1 After overhang growth occurs on the mask at the coupling portion of the MMI multiplexer MMI1 and the semiconductor amplifier SOA1 or the boundary portion between the semiconductor amplifier SOA1 and the window region WD1 provided at the tip thereof, and the cladding layer is stacked and grown, As shown in FIG. 8-4, a cavity remains and becomes a light reflection point. To cause sexual degradation, as overhanging growth does not occur at these sites, it was necessary to reduce the blocking layer thickness of the LD section.

  As described above, the example of the optical integrated device has been described. However, in the optical semiconductor device, in order to suppress overgrowth growth, abnormal growth, and formation of cavities, the growth layer thickness of the entire wafer is restricted, and depending on the device configuration. However, there is a problem that a sufficient buried layer thickness cannot be obtained when forming a current blocking structure or an optical confinement structure.

  SUMMARY OF THE INVENTION An object of the present invention is to provide an optical semiconductor element that has little overgrowth on a mask and abnormal growth at the edge of the mask and has excellent surface flatness, and a method for manufacturing the same.

  According to the present invention, an optical semiconductor device having a buried waveguide structure, a waveguide including a relatively narrow narrow portion and a relatively wide wide portion, and adjacent to the narrow portion. An optical semiconductor, comprising: a selective growth layer formed in a predetermined region including the first region to be formed and formed with a predetermined width at least in the first region; and a buried layer covering the selective growth layer An element is provided.

  According to the invention, the first mask covering the waveguide including the narrow portion and the wide portion provided on the semiconductor substrate, and the predetermined width from the narrow portion in the direction perpendicular to the substrate plane with respect to the optical waveguide direction. Forming a mask pattern including a second mask disposed at a distance; and selectively growing a semiconductor layer in an opening of the mask pattern to form a selective growth layer in contact with a side surface of the waveguide And a step of forming a buried layer so as to cover the selective growth layer.

  According to the present invention, the selective growth layer is formed in a region sandwiched between the waveguide and the buried layer in the narrow width portion. For this reason, the growth delay of the semiconductor growth layer in the narrow width portion is alleviated, and the variation in the thickness of the buried layer between the narrow width portion and the thick width portion is reduced. As a result, the growth time of the semiconductor layer around the waveguide can be minimized, and there is little overgrowth growth on the mask and abnormal growth at the edge of the mask, with excellent surface flatness and reliability. A high element structure is realized.

In the above invention, the buried layer may be configured to be in contact with at least a part of a side surface of the selective growth layer opposite to a side in contact with the narrow width portion and an upper surface of the selective growth layer. it can. By doing so, the growth of the semiconductor growth layer in the narrow width portion is promoted, and the variation in the thickness of the buried layer between the narrow width portion and the thick width portion is further reduced.
In the present invention, the predetermined region includes a second region adjacent to the wide portion, and the maximum layer thickness of the selective growth layer in the first region is substantially equal to the maximum layer thickness of the selective growth layer in the second region. Or a small configuration. The term “substantially equal” means substantially equal within a measurement error range. For example, the ratio of the thickness of a selective growth layer having a small thickness to a selective growth layer having a large thickness is 90% or more. By doing so, a highly reliable element structure with excellent surface flatness is realized.

  Further, in the present invention, a buried layer may be formed in a region adjacent to the second region on the opposite side of the wide portion. In this case, the width of the second region may be wider than the width of the first region. In this way, the width of the second region can be controlled in addition to the width of the first region, and the growth rate of the semiconductor growth layer not only near the narrow portion but also near the wide portion can be controlled. As a result, a highly reliable element structure with even more excellent surface flatness is realized.

The narrow-width portion is a fundamental mode waveguide, and the wide-width portion is a multimode waveguide that has a wider width than the fundamental mode waveguide and provides a mode including multiple modes for guided light. Also good.
The optical semiconductor element of the present invention can be suitably applied to various elements having an optical waveguide, and can be particularly suitably applied to an optical integrated element or the like.

  Although the configuration of the present invention has been described above, any combination of these configurations, or a conversion of the expression of the present invention between methods, apparatuses, systems, etc. is also effective as an aspect of the present invention.

For example, the present invention includes the following inventions.
(i) In an optical semiconductor integrated device having an embedded waveguide structure having at least two different widths, the waveguide width is w (n) (n is a positive integer, w (n + 1)> w (n)), and the width In the layer thickness of the semiconductor buried layer beside the waveguide of w (n), the maximum buried layer thickness in the cross section where the maximum buried layer thickness in the cross section perpendicular to the waveguide direction of the same waveguide is the thinnest is d (n). Then, at least one optical semiconductor element having n satisfying d (n + 1) ≦ d (n).
(ii) a step of laminating a semiconductor layer for forming at least two types of semiconductor buried waveguides having different widths on a substrate, and then a width for striping the semiconductor layer for forming the optical waveguide; The thickness of the first mask of w (n) (n is a positive integer, w (n + 1)> w (n)) and the semiconductor buried layer beside the waveguide of width w (n) is defined as d (n). Then, a step of forming a second mask for realizing n satisfying at least one of d (n + 1) ≦ d (n) at an interval beside the n-th first mask, and then the first mask And a step of forming a groove by etching a part of the semiconductor layer while leaving the second mask, and a step of forming a semiconductor buried layer in the groove by crystal growth. Manufacturing method of optical semiconductor integrated device.
(iii) On the substrate, at least one waveguide side surface and a plane parallel to the substrate intersect with a waveguide in a direction parallel to [110], and at least one intersection line not parallel to [110]. A step of laminating semiconductor layers for forming waveguides, a first mask for striping the semiconductor layers for forming the optical waveguides, and at least one of the intersection lines is [110]. Forming a second mask at an interval beside the waveguide in the parallel direction, and then etching a part of the semiconductor layer while leaving the first mask and the second mask to form a groove And a step of forming a semiconductor buried layer in the groove portion by performing crystal growth, and a method for manufacturing an optical semiconductor integrated device.

  Since the buried layer thickness can be locally controlled, the degree of freedom in designing an optical semiconductor element can be increased, and the performance and yield can be improved. Further, since only the layer thickness of a necessary portion can be increased, the time required for the burying growth can be greatly shortened, and the manufacturing cost can be greatly saved.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.

  The growth of the semiconductor layer in each embodiment uses the MOVPE method, but other film forming methods can also be used.

  In the semiconductor optical device according to the embodiment shown below, a dielectric mask (dummy mask) is formed beside a region (for example, LD stripe) whose layer thickness is to be increased, and the growth rate of the specific region is increased, Increase the layer thickness of the required area. This dummy mask does not necessarily match the planar shape of all or part of the semiconductor layer constituting the optical integrated device. For example, in the case of a double channel planar buried-hetero (DC-PBH) structure A mask may be formed at an appropriate position on the terrace of the carrier recombination layer.

  In the semiconductor optical device according to the following embodiments, since a necessary amount of raw material is supplied to a necessary portion by a dummy mask, a necessary portion such as a current constriction portion is sufficiently thick and abnormal growth is likely to occur. The layer thickness of the butt joint part in the (110) direction ((111) A direction) is minimized, and there are few protrusions on the mask and protrusions at the mask edge, and optically smooth connection and flatness. Are compatible.

First Embodiment This embodiment relates to a semiconductor optical amplifier having a structure in which a fundamental mode waveguide is connected to a multimode interferometer (MMI). The periphery of the waveguide composed of the MMI region and the fundamental mode waveguide is covered with a buried semiconductor layer. In this embodiment, this buried layer is formed in two stages. That is, first, a first buried layer is formed by selective growth in the regions on both sides of the waveguide, and then a second buried layer that covers the first buried layer is formed. Thereby, the overgrowth growth and abnormal growth of the semiconductor layer and the formation of cavities can be suppressed.

  Hereinafter, a method for manufacturing the semiconductor optical amplifier according to the present embodiment will be described.

First, a first cladding layer L1, a core layer L2, and a second cladding layer L3 are stacked in this order on a semiconductor substrate. Various materials can be used as these constituent materials. In this embodiment, an InGaAsP semiconductor is used. That is, an InP substrate is used as the semiconductor substrate, and n-InP and p-InP are used for the first cladding layer L1 and the second cladding layer L3, respectively. As a material constituting the core layer, for example, In _x Ga _1-x As _y P _1-y (x and y are 0 or more and 1 or less).
Is used.

  Next, a mask pattern shown in FIG. 9 is formed. As shown in the drawing, dummy masks DM1, DM2, and DM3 are arranged on both sides of the masks M1 to M3 at a predetermined distance in the direction perpendicular to the substrate surface with respect to the optical waveguide direction. Each mask is formed of, for example, silicon oxide.

  The widths wdm (1), wdm (2), and wdm (3) of the dummy masks DM1, DM2, and DM3 have the smallest buried layer thickness in the cross section perpendicular to the waveguide direction of each of the waveguides WG1, WG2, and WG3. The maximum buried layer thicknesses d (1), d (2), and d (3) in the cross section are designed to satisfy d (1) = d (2) = d (3).

When the dummy mask is not provided, the growth of the semiconductor layer is faster on the side surface of the wide waveguide portion than on the side surface of the narrow width portion. Therefore, in this embodiment, wdm (1)> wdm (2)> wdm (3). Further, the distance between M1-DM1 between the distance of the distance between _d 1, M2-DM2 (opening width) _d 2, M3-DM3 as _{d 3,} is set to _{d 3> d 2> d 1} . Thereby, the growth rate of the buried layer is adjusted so that d (1) = d (2) = d (3).

  Using this mask, a first selective buried layer RG1 is grown on the wafer, and both sides of the multimode interferometer (MMI) and the mesa of the fundamental mode waveguide are buried. Cross-sectional views after growth of RG1 along the lines AA, BB, CC, and DD in FIG. 9 are shown in FIGS. 10-1, 10-2, 10-3, and FIG. It becomes like 10-4. At this time, the maximum buried layer thicknesses d (1), d (2), d (3) in the cross section where the maximum buried layer thickness in the cross section perpendicular to the waveguide direction of each waveguide WG1, WG2, WG3 is the thinnest. ) Is d (1) = d (2)> d (3). As can be seen from FIG. 10-4, no overgrowth growth on the mask as seen in FIG. 6-4 is observed even at the mask edge parallel to [1-10].

  Next, after removing the mask using a predetermined chemical solution, the second buried growth layer RG2 is grown. The mask removing liquid is appropriately selected according to the mask material. In the case of a silicon oxide mask, buffered hydrofluoric acid is preferably used. The material of the growth layer RG2 may be the same material as RG1 or a different material. Due to this growth, the cross sections shown in FIGS. 10-1, 10-2, 10-3, and 10-4 are as shown in FIGS. 11-1, 11-2, 11-3, and 11-4. become. As shown in the drawing, RG2 is formed so as to cover the side surface and the upper surface of the selective growth layer RG1 formed in the region near the side surface of the waveguide.

As can be seen from FIG. 11-4, even at the mask edge parallel to [1-10], the cavity as seen in FIG. 8-4 is not seen. Therefore, this integrated device structure has no overgrowth growth or cavities on the mask, and is excellent in flatness after embedded growth compared to the conventional integrated device structure. Therefore, an optically smooth connection can be obtained, and an integrated device with few crystal defects and excellent device life can be manufactured.
Also, in this integrated device structure, increase in the growth rate at the mask edge is suppressed and no extreme protrusion is generated, so that the flatness of the device surface after regrowth is good, and the subsequent waveguide formation and electrode formation processes Is easy. These effects are due to the effect of adjusting the growth rate difference depending on the mask area during the burying growth by using a dummy mask to suppress the overgrowth growth on the mask and the formation of cavities and protrusions due to abnormal growth. That is, the optical semiconductor device according to the present embodiment includes a waveguide structure including a narrow portion and a wide portion, and includes a selective growth layer formed in a stripe shape having a predetermined width in a region adjacent to the narrow portion. Therefore, the growth of the semiconductor growth layer in the narrow width portion is promoted and the variation in the growth layer thickness is reduced, so that the reliability of the device can be greatly improved.

  Second embodiment

  Next, a second embodiment of the present invention will be described using an integrated element structure having a DC-PBH structure in which a recombination layer is disposed outside a waveguide and current blocking performance is improved.

  Hereinafter, a method for manufacturing the element according to the present embodiment will be described. First, a step of crystal growth of a semiconductor thin film having a double hetero structure, a step of forming a dielectric film on the semiconductor thin film, and a step of forming a desired mask pattern on the semiconductor thin film by photolithography and etching Perform to obtain the structure shown in FIG. In the illustrated structure, the first dielectric is formed by combining three dielectric masks having widths w (1), w (2), w (3) (w (1) <w (2) <w (3)). A mask and a second dielectric mask disposed at positions separated from the dielectric mask by widths wc (1), wc (2), and wc (3) are provided. The second dielectric mask is formed in a direction parallel to the [110] direction on the semiconductor wafer having a double hetero structure of zinc ore crystal.

  Using this mask, dry etching is performed to form a waveguide mesa. Next, a part of the second dielectric mask is removed by wet etching or the like to obtain the structure shown in FIG. In the illustrated structure, the widths wc (1), wc (1), w (2), w (3) (w (1) <w (2) <w (3)) are outside the waveguide. 2) The carrier recombination layer is disposed through the groove of wc (3). A dummy mask having widths wdm (1), wdm (2), and wdm (3) is formed on the carrier recombination layer.

  Next, when the first buried layer RG1 is grown by using a metal organic vapor phase epitaxy (MOVPE) method, AA line, BB line, CC line, D in FIG. The cross-sectional views after RG1 growth along the line -D are as shown in FIGS. 14-1, 14-2, 14-3, and 14-4. At this time, the widths wc (1), wc (2), and wc (3) of the grooves and the widths wdm (1), wdm (2), and wdm (3) of the dummy masks DM1, DM2, and DM3 correspond to the respective waveguides. The maximum buried layer thicknesses d (1), d (2), and d (3) in the cross section where the maximum buried layer thickness in the cross section perpendicular to the waveguide direction of WG1, WG2, and WG3 is d (1 ) = D (2) = d (3).

  When the dummy mask is not provided, the growth of the semiconductor layer is faster on the side surface of the wide waveguide portion than on the side surface of the narrow width portion. Therefore, in this embodiment, wdm (1)> wdm (2)> wdm (3). Thereby, the growth rate of the buried layer is adjusted so that d (1) = d (2) = d (3).

  Next, when the first and second dielectric masks are removed by wet etching or the like to grow the second buried growth layer RG2, as shown in FIGS. 14-1, 14-2, 14-3, and 14-4. The same cross sections as shown are as shown in FIGS. 15-1, 15-2, 15-3, and 15-4, respectively. As shown in the drawing, RG2 is formed so as to cover the side surface and the upper surface of the selective growth layer RG1 formed in the region near the side surface of the waveguide.

  In the present embodiment, dummy masks DM1 and DM2 are provided on both sides of the narrow waveguides (w (1) and w (2)) with a predetermined distance in the direction perpendicular to the optical waveguide direction in the substrate plane, A semiconductor buried layer is selectively grown in the opening between these and the masks M1 and M2. For this reason, compared with the case where no dummy mask is provided, the buried growth around the narrow waveguide is promoted. As a result, the growth rate of the buried layer can be made substantially equal around the narrow portion and the wide portion of the waveguide, and the flatness of the buried layer can be improved. Further, the time required for the burying growth can be kept to the minimum necessary, the overgrowth growth to the mask end in the cross-sectional structure shown in FIG. 14-4 can be suppressed, and the generation of the cavity shown in FIG. 8-4 can be avoided. .

  As described above, the integrated device structure according to the present embodiment has no overgrowth growth and cavities on the mask, and is excellent in flatness after embedded growth compared to the conventional integrated device structure. Therefore, an optically smooth connection can be obtained, and an integrated device with few crystal defects and excellent device life can be manufactured. Also, in this integrated device structure, increase in the growth rate at the mask edge is suppressed and no extreme protrusion is generated, so that the flatness of the device surface after regrowth is good, and the subsequent waveguide formation and electrode formation processes Is easy. These effects are achieved by adjusting the growth rate difference depending on the mask area during buried growth by adjusting the width and length of the groove and dummy mask provided between the waveguide and the recombination layer, This is due to the effect of suppressing the formation of protrusions due to abnormal growth. That is, the optical semiconductor device according to the present embodiment includes a waveguide structure including a narrow portion and a wide portion, and includes a selective growth layer formed in a stripe shape having a predetermined width in a region adjacent to the narrow portion. Therefore, the growth of the semiconductor growth layer in the narrow width portion is promoted and the variation in the growth layer thickness is reduced, so that the reliability of the device can be greatly improved.

  In the present embodiment, a part of the second dielectric mask is removed by wet etching or the like to obtain a pattern as shown in FIG. 13, but the second dielectric mask is completely removed and a new dielectric is formed. After forming the body film, a pattern as shown in FIG. 13 may be obtained by photolithography and etching.

  Third embodiment

  FIG. 20A is a layout diagram of a mask that can be used to form the optical semiconductor element of the present invention. FIG. 20A is the same as that described in the above embodiment. The illustrated mask includes a mask 203 formed on the upper portion of the waveguide, and a dummy mask 201a and a dummy mask 201b for controlling the layer thickness of the buried layers (current blocking layers) on both sides of the waveguide. A dummy mask 201a is formed on the side of the narrow portion of the waveguide, and a dummy mask 201b is formed on the side of the thick portion of the waveguide. The width of the dummy mask 201a is D1, the width of the dummy mask 201b is D2, the distance between the dummy mask 201a and the mask 203 is d1, and the distance between the dummy mask 201b and the mask 203 is d2. By appropriately designing the sizes of these parameters, the thickness of the buried layer beside the waveguide can be made uniform. Since the growth of the semiconductor layer is promoted on the side surface of the waveguide wide portion, it is preferable that the dummy mask 201b has a smaller area than the dummy mask 201a and d2 has a value larger than d1.

  In the mask pattern shown in FIG. 20A, the dummy mask 201a and the dummy mask 201b are formed separately, and the mask does not exist in the vicinity of the junction between the waveguide wide portion and the narrow portion. . For this reason, the effect that the abnormal growth of the semiconductor layer on the surface a is suppressed is obtained, and the reliability of the device is also improved in this respect.

  FIG. 20-2 shows another mask pattern. In this mask pattern, dummy masks 201 are formed in stripes on both sides of the mask 203 at a predetermined distance in the direction perpendicular to the substrate surface with respect to the optical waveguide direction. Unlike the mask pattern shown in FIG. 20A, a dummy mask beside the wide width portion and a dummy mask beside the narrow width portion are continuously formed integrally. Even with this mask pattern, it is possible to suppress variations in the thickness of the waveguide side buried layer between the wide width portion and the narrow width portion.

  FIG. 21 shows another mask pattern. In this mask pattern, a dummy mask is formed only on the side of the narrow portion of the waveguide. Thereby, the growth of the semiconductor layer on the side surface of the narrow width portion is promoted, and as a result, variations in the buried layer thickness between the narrow width portion and the thick width portion are reduced.

  Fourth embodiment

  The present embodiment relates to a semiconductor optical amplifier. The element of this embodiment is substantially the same as that of the first embodiment, except that the end face of the MMI region is formed at 45 ° with respect to the waveguide direction. The periphery of the waveguide composed of the MMI region and the fundamental mode waveguide is covered with a buried semiconductor layer. In this embodiment, this buried layer is formed in two stages. That is, first, a first buried layer is formed by selective growth in the regions on both sides of the waveguide, and then a second buried layer that covers the first buried layer is formed. Thereby, the overgrowth growth and abnormal growth of the semiconductor layer and the formation of cavities are suppressed.

  FIG. 22 is a schematic diagram showing a waveguide structure of the semiconductor optical amplifier according to this embodiment. FIG. 23 is a top view of the device shown in FIG. As shown in FIG. 22, the semiconductor optical amplifier according to this embodiment includes an input port 103 formed of a fundamental mode waveguide at one end of a multimode waveguide 104. In addition, an output port 105 formed of a fundamental mode waveguide is provided at the other end of the multimode waveguide 104. The multimode waveguide 104 has a wider width than the input port 103 and the output port 105, and provides a mode including multimodes to the waveguide.

The end faces of the multimode waveguide 104 indicated by a1 to a4 in FIG. 23 are all equivalent planes of the (100) plane (hereinafter referred to as {100} planes as appropriate) or planes inclined from these planes. In the case of the inclined surface, the surface is inclined in the direction in which the waveguide region expands in the stacking direction of the semiconductor layers. In the present embodiment, the following aspects are adopted.
a1: (0-10) plane a2: (100) plane a3: (010) plane a4: (-100) plane

  In FIG. 23, b1 and b2 are light emitting surfaces, and the (110) plane and the (-1-10) plane of the semiconductor layer constituting the waveguide are exposed. No mirror is formed on these surfaces.

  In FIG. 22, the periphery of the waveguide is covered with a buried layer 200. The buried layer 200 has a structure similar to that shown in FIGS. 11A and 11B, and is composed of RG1 beside the waveguide and RG2 covering the side and upper part thereof.

  FIG. 24 shows an example of a mask pattern for forming the waveguide shown in FIGS.

  The mask pattern of FIG. 24-1 includes a mask 203 formed on the upper portion of the waveguide, and a dummy mask 201a and a dummy mask 201b for controlling the layer thickness of the buried layers (current blocking layers) on both sides of the waveguide. ing. A dummy mask 201a is formed on the side of the narrow portion of the waveguide, and a dummy mask 201b is formed on the side of the thick portion of the waveguide. The width of the dummy mask 201a is D1, the width of the dummy mask 201b is D2, the distance between the dummy mask 201a and the mask 203 is d1, and the distance between the dummy mask 201b and the mask 203 is d2. By appropriately designing the sizes of these parameters, the thickness of the buried layer beside the waveguide can be made uniform. Since the growth of the semiconductor layer is promoted on the side surface of the waveguide wide portion, it is preferable that the dummy mask 201b has a smaller area than the dummy mask 201a and d2 has a value larger than d1.

  In the mask pattern shown in FIG. 24-1, the dummy mask 201a and the dummy mask 201b are formed separately, and the mask does not exist in the vicinity of the junction between the waveguide wide portion and the narrow portion. . For this reason, the effect that the abnormal growth of the semiconductor layer on the surface a is suppressed is obtained, and the reliability of the device is also improved in this respect.

  FIG. 24-2 shows another mask pattern. In this mask pattern, dummy masks 201 are formed in stripes on both sides of the mask 203 at a predetermined distance in the direction perpendicular to the substrate surface with respect to the optical waveguide direction. Unlike the mask pattern of FIG. 24A, the mask on the side of the wide width portion and the mask on the side of the narrow width portion are formed continuously and integrally. Even with this mask pattern, it is possible to suppress variations in the thickness of the waveguide side buried layer between the wide width portion and the narrow width portion.

  In addition, a dummy mask may be formed only on the side of the narrow portion of the waveguide. Thereby, the growth of the semiconductor layer on the side surface of the narrow width portion is promoted, and as a result, variations in the buried layer thickness between the narrow width portion and the thick width portion are reduced.

  Using the mask pattern as described above, the buried layer (RG1) is selectively grown on both sides of the waveguide, and then RG2 that covers the side and top of RG1 is formed, thereby obtaining the element according to the present embodiment. be able to.

  In the structure of the present embodiment, the following advantages are obtained in addition to the operational effects described in the first and second embodiments.

  In the present embodiment, the end surface of the multimode waveguide 104 is set as an equivalent surface of the (100) plane. By doing so, the growth of the buried layer around the waveguide is suppressed, and the abnormal growth of the semiconductor layer on the MMI end face, which has been a problem in the past, is suppressed. Thereby, generation | occurrence | production of an electric current leak can be suppressed and an optical loss can be reduced effectively.

  Further, in the present embodiment, as a result of the side surface of the multimode waveguide 104 being a specific surface as described above, the corner portion is removed from the conventional rectangular multimode waveguide 104. Yes. These corners are regions that do not contribute to the light emission intensity, and eliminating this part eliminates the need for passing an extra current, and also provides an advantage that power saving of the element can be achieved.

Example 1
An example in which the second embodiment is applied to an InGaAsP-based active MMI laser will be described. In this example, in the second embodiment, the waveguides WG1 and WG2 are single mode waveguides having the same width, and the waveguide WG3 is a multimode interference waveguide, which is the same as in the second embodiment. An element is formed by the manufacturing procedure. First, a step of crystal growth of a semiconductor thin film having a double heterostructure having an InGaAsP strained multiple quantum well as an active layer on an n-type InP substrate, a step of forming a dielectric film on the semiconductor thin film, photolithography, By a process of forming a desired mask pattern on the semiconductor thin film by etching or the like, widths w (1), w (2), w (3) (w (1) = <w (2) as shown in FIG. a first dielectric mask in which three dielectric masks of <w (3)) are combined, and a place away from the dielectric mask by a certain width (wc (1) = wc (2) = wc (3)) Is formed in a direction parallel to the [110] direction on the semiconductor thin film.

  Next, a mesa is formed by dry etching, and then a part of the second dielectric mask is removed by wet etching or the like, and the widths w (1), w (2), w (3) (w) as shown in FIG. (1) = w (2) <w (3)) A carrier recombination layer is disposed outside the waveguide via a groove having a constant width (wc (1) = wc (2) = wc (3)). Further, a pattern in which a dummy mask having widths wdm (1), wdm (2), and wdm (3) is formed on the carrier recombination layer is obtained.

  Next, when a current blocking layer composed of a p-type InP block layer CB1, an n-type InP block layer CB2, and a p-type InP cap layer CB3 is grown using the MOVPE method, the AA line, the CC line in FIG. Sectional views after growth of the current blocking layer along the line D-D are as shown in FIGS. 16-1, 16-2, and 16-3, respectively. At this time, the widths wc (1), wc (2), and wc (3) of the grooves and the widths wdm (1), wdm (2), and wdm (3) of the dummy masks DM1, DM2, and DM3 correspond to the respective waveguides. The maximum buried layer thicknesses d (1), d (2), and d (3) in the cross section where the maximum buried layer thickness in the cross section perpendicular to the waveguide direction of WG1, WG2, and WG3 is d (1 ) = D (2) = d (3).

  When the dummy mask is not provided, the growth of the semiconductor layer is faster on the side surface of the wide waveguide portion than on the side surface of the narrow width portion. Therefore, in this embodiment, wdm (1)> wdm (2)> wdm (3). As a result, the growth rate of the current blocking layer is adjusted so that d (1) = d (2) = d (3).

  Next, the first dielectric masks M1, M2, and M3 and the dummy masks DM1, DM2, and DM3 are removed by wet etching or the like, and the p-type InP layer cladding layer CL1 and the p-type contact layer CNT1 are grown. 1, FIG. 16-2 and FIG. 16-3 have the same cross sections as shown in FIG. 17-1, FIG. 17-2 and FIG. 17-3, respectively. As can be seen from FIG. 17-3, even at the mask edge parallel to [1-10], no overgrowth growth on the mask as seen in FIG. 6-4 is observed, and the p-type cladding layer CL1. Even after the growth of the p-type contact layer CNT1, there is no cavity as seen in FIG. 8-4, as shown in FIG. 17-3. Therefore, the present active MMI laser has no overgrowth growth or cavities on the mask, and is excellent in flatness after buried growth compared to the conventional active MMI laser. Therefore, an optically smooth connection can be obtained, and an integrated device with few crystal defects and excellent device life can be manufactured. Further, in the present active MMI laser, an increase in the growth rate at the mask edge is suppressed and no extreme protrusion is generated, so that the flatness of the element surface after regrowth is good, and the subsequent waveguide formation and electrode formation processes Is easy. These effects are achieved by adjusting the growth rate difference depending on the mask area during buried growth by adjusting the width and length of the groove and dummy mask provided between the waveguide and the recombination layer, This is due to the effect of suppressing the formation of protrusions due to abnormal growth.

  In this embodiment, the 1 × 1 MMI structure has been described. However, the MMI structure including Nx1 and NxN (N is a positive integer) is also effective, and is also effective for the structure having a curved waveguide or a window structure. . In this embodiment, the case where the current blocking layer has a three-layer structure has been described. However, the present invention is not limited to this, and the present invention is also applicable to a structure including a plurality of current blocking layers other than three layers or a single current blocking layer. It is valid. Further, neither the first cladding layer CL1 layer nor the first contact layer CNT1 needs to be a layer having a uniform composition or electrical conductivity, but a layer having a plurality of compositions or a plurality of electrical conductivities. It may be composed of a combination of different layers.

  Example 2

  Next, the case where the present invention is applied to an InGaAsP-based wavelength selective light source will be specifically described.

  The wavelength selection light source according to the present embodiment is manufactured as follows. First, four DFB lasers LD1, LD2, LD3, LD4, an MMI multiplexer MMI1, a semiconductor amplifier (Semiconductor Optical) are formed on a semiconductor wafer having a double heterostructure having an InGaAsP active layer fabricated on an InP substrate by MOVPE. Amplifier: SOA) A mesa is formed using the mask pattern of the wavelength selective light source of FIG. Next, as shown in FIG. 19, a first dummy mask DM1 for increasing the block layer thickness of the LD1, LD2, LD3, and LD4 portions, and a second dummy mask DM2 for increasing the block layer thickness of the SOA portion. Place. That is, a dummy mask is provided in a portion where the waveguide width is narrow with a predetermined distance in the direction perpendicular to the substrate plane with respect to the optical waveguide direction.

  Thereafter, a current blocking layer made of n-type and p-type InP is formed by MOVPE, and then DFB laser parts LD1, LD2, LD3, LD4, S-shaped waveguide parts S1, S2, S3, S4, MMI multiplexer parts. All the partial masks of the MMI 1 and the semiconductor amplifier part SOA1, the first dummy mask DM1, and the second dummy mask DM2 are removed by etching or the like. Subsequently, a clad layer and a contact layer are formed by the MOVPE method.

  Due to the effect of the dummy mask, the S-shaped waveguides S1, S2, S3, S4, the overhanging growth at the input / output ends of the MMI, and the overhanging on the mask also at the boundary between the semiconductor amplifier SOA1 and the window region WD1 at the tip thereof. It is possible to obtain a sufficiently thin growth layer thickness in which no growth occurs and void formation does not occur, and it is possible to sufficiently increase the current blocking layer thickness in the LD1, LD2, LD3, LD4 and SOA1 portions. As a result, the maximum optical output of each of the DFB lasers LD1, LD2, LD3, LD4 and the semiconductor optical amplifier SOA1 is improved, and a reflection point such as a cavity is suppressed from being generated in the waveguide, thereby optically smooth coupling. Is realized.

  The fiber coupled maximum light output of this wavelength selection light source is 50 mW or more, which is 5 times or more higher than the conventional device.

The present invention has been described based on the embodiments. This embodiment is an exemplification, and it will be understood by those skilled in the art that various modifications are possible and that such modifications are also within the scope of the present invention.

  For example, in the above embodiment, an integrated device structure having an InGaAsP-based waveguide structure on an InP substrate has been described. However, other material systems and substrates can be used. For example, an integrated device structure having an AlGaInAs-based waveguide structure on an InP substrate, an integrated device structure having an AlGaAs-based waveguide structure on a GaAs substrate, an integrated device structure having a GaInAs-based waveguide structure on a GaAs substrate, or on a GaAs substrate An integrated device structure having a GaInNAsSb-based waveguide structure, an integrated device structure having an AlGaInP-based waveguide structure on a GaAs substrate, an sapphire or SiC substrate, an integrated device structure having an AlGaInN-based waveguide structure on a GaN substrate, etc. The present invention can be applied.

  In the element according to the embodiment, the lower clad layer is formed on the substrate and the core layer is provided thereon. However, the core layer may be provided directly on the substrate.

  As mentioned above, although embodiment of this invention was described with reference to drawings, these are the illustrations of this invention, Various structures other than the above are also employable.

  In the above embodiment, an integrated element having a semiconductor waveguide structure including a substrate and a first cladding layer, a core layer, and a second cladding layer has been described. However, an integrated element having a waveguide having a structure other than this is described. It is also effective for devices. In this embodiment, the case where three waveguides having different widths are combined is described. However, the present invention is not limited to this combination, and a combination of a plurality of waveguides having different widths, a plurality of linear waveguides, and a curved line are used. It is also effective for an integrated structure composed of a combination of waveguides. Further, in this embodiment, the integrated device structure manufactured by two times of buried growth is described, but the number of times of buried growth is not limited to this, and it is also effective for an integrated device manufactured by other number of times of buried growth. It is.

  In the present embodiment, the structure is symmetrical on both sides of the center line in the axial direction of the waveguide. For example, the groove width, the dummy mask width and length, the shape, and the shape of the recombination layer are different. An asymmetric structure may be used.

Manufacturing process of conventional modulator integrated light source described in Non-Patent Document 1 Conventional modulator integrated light source described in Non-Patent Document 1 Wafer overview after waveguide pattern mask formation in conventional integrated device manufacturing process Overview of wafer after waveguide mesa formation by dry etching in conventional integrated device manufacturing process Overview of wafer after growth of first buried layer in conventional integrated device manufacturing process Wafer sectional view along line AA in FIG. Wafer sectional view along line BB in FIG. Wafer cross-sectional view along line CC in FIG. Wafer sectional view along line DD in FIG. Overview of wafer after growing second buried layer in conventional integrated device manufacturing process Wafer cross section along line AA in FIG. Wafer cross section along line BB in FIG. Wafer sectional view along line CC in FIG. Wafer sectional view taken along line DD in FIG. Overview of wafer after forming dummy mask after waveguide mesa formation by dry etching in the manufacturing process of the first embodiment of the integrated device of the present invention FIG. 9 is a cross-sectional view of the wafer taken along line AA in FIG. 9 after the first buried layer is grown in the manufacturing process of the integrated device according to the first embodiment. FIG. 9 is a cross-sectional view of the wafer taken along line BB in FIG. 9 after the first buried layer is grown in the manufacturing process of the integrated device according to the first embodiment. FIG. 9 is a cross-sectional view of the wafer taken along line CC in FIG. 9 after the growth of the first buried layer in the manufacturing process of the integrated device according to the first embodiment. FIG. 9 is a cross-sectional view of a wafer taken along line DD in FIG. 9 after the first buried layer is grown in the manufacturing process of the integrated device according to the first embodiment. FIG. 9 is a cross-sectional view of the wafer taken along line AA of FIG. 9 after the second buried layer is grown in the manufacturing process of the integrated device according to the first embodiment. FIG. 9 is a cross-sectional view of the wafer taken along line BB in FIG. 9 after the second buried layer is grown in the manufacturing process of the integrated device according to the first embodiment. FIG. 9 is a cross-sectional view of the wafer taken along line CC in FIG. 9 after the second buried layer is grown in the manufacturing process of the integrated device according to the first embodiment. FIG. 9 is a cross-sectional view of the wafer taken along line DD in FIG. 9 after the second buried layer is grown in the manufacturing process of the integrated device according to the first embodiment. Overview of wafer after mask formation of waveguide pattern in manufacturing process of second embodiment of integrated device according to embodiment Overview of wafer after formation of dummy mask after formation of waveguide mesa by dry etching in manufacturing process of second embodiment of integrated device according to embodiment Sectional view of wafer taken along line AA in FIG. 13 after the growth of the first buried layer in the manufacturing process of the second embodiment of the integrated device according to the embodiment Sectional view of wafer taken along line BB in FIG. 13 after the growth of the first buried layer in the manufacturing process of the second embodiment of the integrated device according to the embodiment Sectional view of wafer taken along line CC in FIG. 13 after the growth of the first buried layer in the manufacturing process of the second embodiment of the integrated device according to the embodiment Sectional view of wafer taken along line DD in FIG. 13 after the growth of the first buried layer in the manufacturing process of the second embodiment of the integrated device according to the embodiment Sectional view of wafer taken along line AA in FIG. 13 after the second buried layer growth in the manufacturing process of the second embodiment of the integrated device according to the embodiment Sectional view of wafer taken along line BB in FIG. 13 after growth of the second buried layer in the manufacturing process of the second embodiment of the integrated device according to the embodiment Sectional view of wafer taken along line CC in FIG. 13 after the growth of the second buried layer in the manufacturing process of the second embodiment of the integrated device according to the embodiment FIG. 13 is a cross-sectional view of the wafer taken along line DD in FIG. 13 after the second buried layer is grown in the manufacturing process of the second embodiment of the integrated device according to the embodiment. Sectional view of wafer taken along line AA in FIG. 13 after the growth of the first buried layer in the manufacturing process of the first example of the integrated device according to the embodiment. Sectional view of wafer taken along line BB in FIG. 13 after the growth of the first buried layer in the manufacturing process of the first example of the integrated device according to the embodiment. Sectional view of wafer taken along line DD in FIG. 13 after the growth of the first buried layer in the manufacturing process of the first example of the integrated device according to the embodiment. Sectional view of wafer taken along line AA in FIG. 13 after the growth of the second buried layer in the manufacturing process of the first example of the integrated device according to the embodiment Sectional view of wafer taken along line BB in FIG. 13 after growth of the second buried layer in the manufacturing process of the first example of the integrated device according to the embodiment Sectional view of wafer taken along line DD in FIG. 13 after the growth of the second buried layer in the manufacturing process of the first example of the integrated device according to the embodiment Dielectric mask pattern before current blocking layer growth of conventional wavelength selective light source Dielectric mask pattern before current block layer growth of wavelength selective light source according to embodiment It is a figure which shows an example of the mask pattern for forming the element which concerns on embodiment. It is a figure which shows an example of the mask pattern for forming the element which concerns on embodiment. It is a figure which shows an example of the mask pattern for forming the element which concerns on embodiment. It is a figure which shows the structure of the element which concerns on embodiment. It is a figure which shows the structure of the element which concerns on embodiment. It is a figure which shows an example of the mask pattern for forming the element which concerns on embodiment. It is a figure which shows an example of the mask pattern for forming the element which concerns on embodiment.

Explanation of symbols

L1: Semiconductor substrate and first clad layer L2 deposited thereon: Core layer L3 ... Second clad layer M1 ... Dielectric mask M2 for forming the first waveguide ... Dielectric mask M3 for forming the second waveguide ... Dielectric mask WG1 for forming the third waveguide ... First waveguide WG2 ... Second guide Waveguide WG3 ... third waveguide w (1) ... first waveguide width w (2) ... second waveguide width w (3) ... third waveguide width RG1 ... First semiconductor buried layer AA ... Line AA parallel to the substrate
BB: Straight line BB parallel to the substrate
CC ... Straight line CC parallel to the substrate
DD: Straight line DD parallel to substrate
d (1) ... The maximum buried layer thickness d (2) in the cross section where the maximum buried layer thickness in the cross section perpendicular to the waveguide direction of the first waveguide in the first buried regrowth layer is the thinnest. ..Maximum buried layer thickness d (3) in the cross section where the maximum buried layer thickness in the cross section perpendicular to the waveguide direction of the second waveguide in the first buried regrown layer is the thinnest. Among buried regrowth layers, the largest buried layer thickness RG2 in the cross section where the maximum buried layer thickness in the cross section perpendicular to the waveguide direction of the third waveguide is the smallest RG2... Second semiconductor buried layer V1. 1
DM1 ・ ・ ・ first dummy mask DM2 ・ ・ ・ second dummy mask DM3 ・ ・ ・ third dummy mask wc (1) ・ ・ ・ first groove width wc (2) ・ ・ ・ second groove Width wc (3) ... third groove width wdm (1) ... first dummy mask width wdm (2) ... second dummy mask width wdm (3) ... third dummy Mask width CB1 ... first current block layer CB2 ... second current block layer CB3 ... third current block layer CL1 ... first cladding layer CNT1 ... first contact layer LD1 ... first semiconductor laser LD2 ... second semiconductor laser LD3 ... third semiconductor laser LD4 ... fourth semiconductor laser S1 ... first S-shaped waveguide S2 ... Second S-shaped waveguide S3 ... Third S-shaped waveguide S4 ... Fourth S-shaped waveguide MMI1 ... first multimode interference multiplexer SOA1 ... first semiconductor amplifier WD1 ... first window region 103 ... input port 104 ... multimode waveguide 105 ... output Port 200 ... Embedded layer 201 ... Dummy mask 201a ... Dummy mask 201b ... Dummy mask 203 ... Mask

Claims (9)

An optical semiconductor element having a buried waveguide structure,
A waveguide including a relatively narrow narrow portion and a relatively wide wide portion;
A selective growth layer formed in a predetermined region including a first region adjacent to the narrow-width portion, and having a predetermined width at least in the first region;
A buried layer covering the selective growth layer;
An optical semiconductor element comprising: The optical semiconductor device according to claim 1,
The optical semiconductor element, wherein the buried layer is formed in contact with at least a part of a side surface of the selective growth layer opposite to a side in contact with the narrow width portion and an upper surface of the selective growth layer.   3. The optical semiconductor device according to claim 1, wherein the predetermined region includes a second region adjacent to the wide portion, and a maximum layer thickness of the selective growth layer in the first region is selected in the second region. An optical semiconductor element characterized by being substantially equal to the maximum thickness of the growth layer or smaller than the maximum thickness of the selective growth layer in the second region.   4. The optical semiconductor element according to claim 3, wherein the width of the second region is wider than the width of the first region. The optical semiconductor element according to claim 1,
The narrow width portion is a fundamental mode waveguide, and the wide width portion is a multimode waveguide that has a wider width than the fundamental mode waveguide and provides a mode including a multimode with respect to guided light. A featured optical semiconductor element. A first mask covering a waveguide including a narrow portion and a wide portion provided on a semiconductor substrate, and a predetermined distance from the narrow portion in the direction perpendicular to the optical waveguide direction in the substrate plane Forming a mask pattern including a second mask;
Selectively growing a semiconductor layer in the opening of the mask pattern to form a selective growth layer in contact with a side surface of the waveguide;
Forming a buried layer so as to cover the selective growth layer;
The manufacturing method of the optical semiconductor element characterized by the above-mentioned. In the manufacturing method of the optical semiconductor element according to claim 6,
The opening of the mask pattern includes a first region adjacent to the narrow portion,
The method of manufacturing an optical semiconductor element, wherein the buried layer is formed also in a region adjacent to the first region on the opposite side of the narrow portion.   8. The method for manufacturing an optical semiconductor device according to claim 6, wherein the opening of the mask pattern includes a second region adjacent to the wide portion, and the maximum thickness of the selective growth layer in the first region is the first. Manufacturing the optical semiconductor element, wherein the selective growth layer is formed so as to be substantially equal to or smaller than the maximum thickness of the selective growth layer in the second region. Method.   9. The method of manufacturing an optical semiconductor element according to claim 8, wherein the width of the second region is wider than the width of the first region.

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