JP2005136667A - Digital signal delay unit, acoustic signal processor equipped with the same, digital signal delay method and its program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a digital signal delay unit for executing delay processing to an inputted digital signal, and an acoustic signal processor equipped with the unit, and a digital signal delay method and its program, wherein the setting precision of a delay time is improved while a necessary memory capacity is suppressed. <P>SOLUTION: This digital signal delay unit is provided with up-sample parts 21 and 22 which successively execute up-sample processing 11 to increase the sampling rate of an inputted digital signal several times, delay parts 11 to 13 which execute the delay processing of a delay time which is several times as large as a signal sampling cycle to each of a plurality of signals before and after the up-sampling processing and a delay switching part which executes switching of the delay time and the switching of whether to execute delay processing for each of delay processing by the delay parts. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a digital signal delay device that performs delay processing on an input digital signal, an acoustic signal processing device including the delay device, a digital signal delay method, and a program thereof.

A multiway speaker system used for high-end audio requires a realistic sound reproduction with high sound quality.
For example, in Patent Document 1, in a multi-way speaker system, a channel divider (corresponding to a crossover portion) for dividing a signal for each speaker is provided, and a delay correction is provided for the output signal. It is shown.
FIG. 8 is a schematic configuration diagram illustrating an example of a multi-way speaker system.
In the multi-way speaker system, each channel signal (L channel, R channel) of a digital audio signal (sound signal) is branched for each of a plurality of speakers suitable for reproduction of different sound ranges, and a sound range suitable for each speaker. A crossover unit 90 is provided for filtering and outputting to each speaker. Crossover is a function of dividing (branching and filtering) a single acoustic signal (one-channel signal) into bands suitable for the characteristics of each speaker in order to output to a plurality of speakers. .
The acoustic signal divided (filtered) into a plurality of sound ranges (frequency bands) by the crossover unit 90 is output to the speaker 93 via the time alignment unit 91 and the D / A converter 92 (including an amplifier). The time alignment is a function that can set a time for delaying each acoustic signal after the filter processing according to a difference in distance between each speaker 93 and the user who listens to the reproduced sound. Each channel signal (each signal to a plurality of D / A converters 92) is output in synchronism with each sample.
Even if the phase of each channel signal output from the crossover unit 90 is synchronized, if the delay difference of the sound due to the distance difference (difference in the delay time of each sound reaching the user) is not compensated, a plurality of Therefore, there is a problem that the sound from the speaker 93 feels a difference in timing or the sound image is not correctly localized. Therefore, the time delay is used to compensate for the sound delay difference.
In general, the time alignment unit 91 includes a buffer memory that temporarily stores each sample (digital signal) sequentially input at a predetermined sampling period, and stores past samples by the number of samples corresponding to a set delay time. Output sequentially. Therefore, the delay time can be set in the unit of the sampling period of the input digital signal (integer multiple (multiple) of the sampling period).
Here, in the case of an audio digital signal of a music CD, the sampling rate (sampling frequency) is 44.1 kHz, and the sound speed is 340 m / s. Therefore, when the delay time for the sampling period is converted into distance, 340000 (mm ) / 44100 (Hz) = 7.7mm. Therefore, the delay can be adjusted in units of 7.7 mm.
On the other hand, high-quality audio systems may require time alignment with an accuracy of 5 mm or less in terms of distance to the speaker.
In order to meet such demands, before performing delay processing with time alignment, an up-sampling process (also referred to as over-sampling process or over-sampling) that increases the sampling rate is performed on the digital signal, and the sampling period is set. It is conceivable to perform the delay processing described above after shortening.
On the other hand, in recent digital audio systems, upsampling processing is performed on digital audio signals before being analogized by a D / A converter in order to improve sound quality.
For example, Patent Document 2 discloses an analog signal reproduction device that outputs a digital signal to a D / A converter after oversampling (upsampling processing).
Japanese Patent Laid-Open No. 3-143195 JP-A-11-340788

However, when delaying a digital signal that has been upsampled to a sampling rate corresponding to the desired setting accuracy in order to increase the accuracy of setting the delay time in time alignment (narrow the step size), it is almost proportional to the conversion rate of the upsample. As a result, the necessary buffer memory increases.
For example, when delay processing with a maximum delay time of 1 second is performed on a digital signal having a sampling rate of 44.1 kHz, a buffer memory for storing (44100-1) samples is required. When this is up-sampled to 88.2 kHz or 176.4 kHz at a sampling rate of 2 or 4 times, a buffer memory for storing (88200-1) or (176400-1) samples is required.
Accordingly, the present invention has been made in view of the above circumstances, and an object of the present invention is to provide a digital signal delay device and a digital signal delay device capable of improving delay time setting accuracy while suppressing required memory capacity. An audio signal processing apparatus, a digital signal delay method, and a program thereof are provided.

To achieve the above object, according to the present invention, in a digital signal delay device for performing delay processing on an input digital signal, up-sampling processing for increasing the sampling rate of the input signal is sequentially superimposed on the digital signal one or more times. And up-sampling means, and delay means for subjecting each of a plurality of signals before and after each of the up-sampling processes to a delay process having a delay time that is an integral multiple of the sampling period of the signal. It is comprised as a digital signal delay apparatus characterized by these.
Thereby, the setting accuracy of the delay time can be improved while suppressing the required memory capacity. Details will be described later.
Further, for each of the delay processes by the delay means, the delay time according to the situation is provided if it comprises delay switching means for switching the delay time and / or switching whether or not to perform the delay processing. It becomes easy to adjust.

Further, the present invention may be understood as an acoustic signal processing device including the digital signal delay device.
That is, filter means for performing filter processing with different filter characteristics on the input digital acoustic signal in parallel and outputting each signal after the filter processing, and a plurality of digital signals for performing delay processing on each output signal of the filter means An acoustic signal processing device comprising a delay device, wherein the digital signal delay device is the digital signal delay device according to claim 1.
Thus, it is preferable to provide a plurality of the digital signal delay devices because the memory suppression effect becomes more remarkable.
Furthermore, the present invention may be understood as a digital signal delay method or a digital signal delay program corresponding to the processing performed by the digital signal delay device.

  According to the present invention, it is possible to improve the delay time setting accuracy (narrow the setting step width) while reducing the required memory capacity.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings so that the present invention can be understood. The following embodiment is an example embodying the present invention, and does not limit the technical scope of the present invention.
FIG. 1 is a processing block diagram showing an outline of signal processing executed by the acoustic signal processing apparatus A according to the embodiment of the present invention, and FIG. 2 shows an example of an execution program of the acoustic signal processing apparatus A. FIG. 3 is a processing block diagram of an FIR filter unit that is an example of an execution program of the acoustic signal processing apparatus A, and FIG. 4 is a processing block diagram of a channel delay unit X that is an example of an execution program of the acoustic signal processing apparatus A. FIG. 5 is a diagram for explaining the processing of the upsampling unit which is an example of the execution program of the acoustic signal processing apparatus A, and FIG. 6 is the configuration of the buffer memory used by the upsampling unit which is an example of the execution program of the acoustic signal processing apparatus A FIG. 7 is a diagram showing a setting pattern of the delay time of the channel delay unit X, and FIG. 8 is a multi-way spin as an example of a conventional acoustic signal processing device. It is a block diagram illustrating a schematic configuration of a mosquito system.

The acoustic signal processing apparatus A according to the embodiment of the present invention is incorporated in the crossover unit and the time alignment unit of the multiway speaker system as shown in FIG. Filter processing for passing a signal in a frequency band corresponding to the speaker), and delay processing for the signal after the filter processing.
The acoustic signal processing apparatus A includes a DSP (Digital Signal Processor). The DSP inputs an acoustic digital signal sampled at a constant period via an input interface, and stores in advance in storage means such as a ROM provided in the DSP. By executing the filtered processing program, filtering processing and delay processing are performed on the input acoustic digital signal, and the processed acoustic signal is output via the output interface. Hereinafter, each processing shown in the processing block diagrams of FIGS. 1 to 5 is implemented by the DSP executing a filter processing program or a delay processing program.
FIG. 1 is a processing block diagram showing an outline of signal processing executed by the acoustic signal processing apparatus A according to the embodiment of the present invention.
As shown in FIG. 1, the acoustic signal processing apparatus A includes a plurality of filter units 80 that execute in parallel filter processes having different filter characteristics on an input digital acoustic signal (digital audio signal), and the filter units. Each program with a plurality of channel delay units X (hereinafter referred to as CH delay units X) that performs delay processing on each of the filtered channel signals output from each of 80 is executed. Here, the CH delay section X corresponds to an embodiment of the digital signal delay device according to the present invention. The plurality of filter sections 80 constitute a crossover section 90, and the plurality of CH delay sections X constitute a time alignment section 91.
That is, the crossover unit 90 (an example of the filter unit) including a plurality of filter units 80 performs filter processing with different filter characteristics on the input digital acoustic signal in parallel, and each signal after the filter processing is performed. Is output. Further, each of the output signals of the crossover unit 90 is subjected to delay processing by a plurality of CH delay units X (corresponding to an example of the digital signal delay device).

FIG. 2 shows an example of the processing configuration of the filter unit 80.
The filter unit 80 includes a first FIR filter unit 81 that performs low-pass filter processing (LPF processing) on the input signal by well-known FIR filter processing, and outputs an output signal of the FIR filter unit 81 further than the FIR filter unit 81. A second FIR filter unit 82 that performs LPF processing by FIR filter processing at a low cutoff frequency, a delay unit 83 that delays the output signal of the first FIR filter unit 81 for the same time as the delay time generated in the second FIR filter unit 82, And a subtracting unit 84 for subtracting the output signal of the second FIR filter unit 82 from the output signal of the delay unit 83.
The second FIR filter unit 82, the delay unit 83, and the subtracting unit 84 realize a high pass filter (HPF). The HPF process and the LPF process by the first FIR filter unit 81 are superimposed on the input signal. By executing, a band pass filter (BPF) is realized.
Of course, depending on the frequency band to be used, only the LPF processing part at the front stage or only the HPF processing part at the rear stage may be considered, and other filter processing may be performed.

FIG. 3 is a block diagram showing known FIR filter processing.
As shown in FIG. 3, in the FIR filter processing, a delay processing unit 94 generates a signal of (n + 1) samples from a certain time t to n samples before, and the multiplication processing unit 95 performs filter coefficient a (k ) (K = 0, 1, 2,..., N) is added by the addition processing unit 96 (that is, product-sum operation is performed) to perform filter processing. Linear phase characteristics (constant delay characteristics) can be obtained by making the filter coefficient a (k) symmetrical (a (N−i + 1) = a (i)) with respect to the order (i = 1 to n).
Although known IIR filter processing can be considered as filter processing, since an IIR filter causes nonlinear filter phase delay with respect to frequency components, an FIR filter is used for high-end audio that requires higher sound quality in recent years. It is desirable to use it.

FIG. 4 is a processing block diagram of the CH delay unit X.
The CH delay unit X includes a first upsampling unit 21 and a second upsampling unit 22 that perform an upsampling process for increasing the sampling rate of the input signal, and thereby the digital signal input from the filter unit 80 is converted into a digital signal. On the other hand, the up-sampling process is performed two times (several times) successively.
In addition, the CH delay unit X has a delay time that is an integral multiple of the sampling period of each of a total of three (plural) signals before and after each processing of the first and second upsampling units 21 and 22. First to third delay units 11, 12, and 13 (an example of the delay unit) that perform delay processing are included.
FIG. 5 shows an upsampling state at a double conversion rate as an example of the upsampling process (oversampling) performed in the first and second upsampling units 21 and 22.
As shown in FIG. 5A, zero value samples are inserted between the samples of the original signal (the signal before upsampling) so that the number of samples per unit time becomes the desired number of samples. Low-pass filter processing is performed to remove high-frequency components (imaging components) generated by the insertion. The example of FIG. 5 (a) is an example in which the number of samples is doubled by inserting a zero value, and low-pass filter processing for removing a high band with a band 1/2 is performed.
FIG. 5B shows each signal corresponding to FIG. 5A as a frequency spectrum.
Assuming that the sampling rate of the signal before upsampling is Fs (for example, 44.1 kHz for an audio signal of a music CD), it is well known that the signal contains only a signal having a frequency component of Fs / 2 or less. is there. On the other hand, when the sampling rate is doubled by inserting a zero value, a spectrum is generated in which the spectrum of the lower frequency band is folded back to a frequency band higher than Fs / 2 that was not in the original signal.
Therefore, by performing a low-pass filter process for removing frequencies higher than Fs / 2, data is interpolated between the original samples, and only the signal having a frequency of Fs / 2 or less originally included can be left.
By the way, it is desirable that the low-pass filter processing performed here is FIR filter processing in order to ensure linearity of delay with respect to the frequency component after the filter processing. In this case, in order to upsample at once at a high conversion rate (for example, 4 times), filter performance that attenuates sharply in a relatively narrow band is required. Therefore, an FIR filter has a very large order filter. Therefore, a very large calculation load and a storage capacity for filter coefficients are required.
On the other hand, when the upsampling at a relatively small change rate (for example, 2 times) is performed in a plurality of stages (for example, two stages) (multiple times are repeated) like the CH delay unit X, As a result, the filter order can be reduced, and the necessary calculation load and filter coefficient storage capacity can be reduced. As a result, the necessary calculation load and filter coefficient storage capacity can be suppressed even for the entire plurality of stages. Thus, the processing configuration of the CH delay unit X that performs upsampling in a plurality of stages also has the effect of reducing the computation load and the filter coefficient capacity.

Further, the CH delay unit X performs a process of switching the delay time from a plurality of candidates in units of integer multiples of the sampling period of the target signal for each of the delay processes by the first to third delay units 11, 12, and 13, and A delay switching unit 30 (an example of the delay switching unit) that performs a process of switching whether or not to perform a delay process is included. This delay time is designated by designating a multiple (C1, C2, C3) of the sampling period for each of the delay units 11 to 13 from the delay switching unit 30.
For example, the first delay unit 11 has three times that is 0 times (= no delay processing), 1 time or 2 times the sampling period Δt 0 of the signal before processing by the first upsampling unit 21. Among the candidates, delay processing is performed according to the delay time designated by the delay switching unit 30.
Similarly, the second and third delay units 12 and 13 apply the respective sampling periods Δt1 and Δt2 to the signals after processing by the first upsampling unit 21 and after processing by the second upsampling unit 22. Delay processing is performed according to the delay time designated by the delay switching unit 30 among 0 times (= when no delay processing is performed) or 1 time.
In this case, the capacity of the buffer memory necessary for the delay process in the first delay unit 11 is sufficient if it has a capacity for two samples of the input signal (sample), and the delays in the second and third delay units 12 and 13 are sufficient. The capacity of the buffer memory necessary for processing is sufficient if it has a capacity for one sample. In other words, when 0 times are specified (no delay), the input sample is output as it is without being stored in the buffer memory. When 1 times is specified, the previous (one time before) stored temporarily in the buffer memory is output. If the sample is output and specified twice, it is sufficient to output the previous sample temporarily stored in the buffer memory.

FIG. 6 shows a configuration example of the buffer memory used by the first delay unit 11. Here, a case is considered in which the delay is performed with a delay time M times the sampling period of the input signal.
FIG. 6A shows a shift register type buffer memory. This reserves sample storage areas (buffer memory) from No. 1 to M, stores M samples, outputs the M-th sample each time a new sample is input, and M- Sample 1 is shifted to position M, sample M-2 is shifted to position M-1, position 1 is shifted to position 2, and a new sample is shifted to position 1. It will be memorized.
FIG. 6B shows a ring buffer type buffer memory. This secures M or more sample storage areas (buffer memory), and sets an input pointer indicating a position (memory address) for storing a new input sample and an output pointer indicating a position for reading a sample to be output. These are set separately, and each time a new sample is input, each pointer is shifted by one. If the pointer points to the end of the sample storage area, the next shift destination is returned to the beginning.
The buffer memory shown in FIGS. 6A and 6B may be secured in a part of the main memory of the DSP provided in the acoustic signal device A, or a separate dedicated buffer memory may be provided.

Next, a delay time setting pattern by the CH delay unit X shown in FIG. 4 will be described with reference to FIG. Here, it is assumed that the conversion rates in the first and second upsampling units 21 and 22 in the CH delay unit X are doubled, and a total of four times upsampling is performed.
In this case, if the sampling period of the original input signal is Δt 0, the input signal to the first delay unit 11 (ie, the original input signal), the input signal to the second delay unit 12, and the third delay unit 13 Each sampling period of the input signal to Δt is Δt0, Δt0 / 2, and Δt0 / 4. Therefore, when the combination of the set multiples C1 (= 0, 1, 2), C2, C3 (= 0, 1 respectively) for switching the delay time to the delay units 11 to 13 is switched, the CH delay unit X The overall delay time is as shown in the table of FIG.
As can be seen from FIG. 7, the delay time of the entire CH delay unit X (here, the delay time caused by the upsampling process is excluded, the same applies hereinafter) has a high accuracy of Δt0 / 4 unit (step size). Thus, a delay time in the range of 0 to 11 · Δt0 / 4 can be set. Further, the capacity of the buffer memory necessary for the realization is 4 samples (= 2 + 1 + 1).
On the other hand, the delay time in the range of 0 to 11 · Δt0 / 4 can be set in the unit (step size) of Δt0 / 4 for the signal after the upsampling process of 4 times. , Δt0 / 4, it is necessary to store samples input up to 2.75 · Δt0 before, so the buffer memory capacity for 11 samples (= (11 · Δt0 / 4) / (Δt0 / 4)) Necessary.

In addition, in the CH delay unit X, when the set multiple C1 for switching the delay time to the first delay unit 11 can be switched from 0, 1, 2,. Memory is required. In this case, the delay time of the entire CH delay unit X can be set to a delay time in the range of 0 to (4M + 3) · Δt0 / 4 in a unit (step size) of Δt0 / 4.
On the other hand, if the delay time can be set in the same unit and range for the signal after the upsampling process of 4 times, a buffer memory for 4M + 3 samples is required.
Therefore, in the case of the above example, by using the CH delay unit X, the buffer memory capacity is at least 3/7 or less and M is large compared to the case where the delay processing is performed after up-sampling the desired conversion rate. Can be suppressed to about 1/4 or less. In addition, since the CH delay unit X is provided for each of a plurality of channel signals in the acoustic signal processing apparatus A, the capacity saving effect of the buffer memory becomes more remarkable as the entire acoustic signal processing apparatus A.

In the above-described embodiment, an example is shown in which each upsampling unit 21 performs upsampling at a double conversion rate. However, upsampling is performed at other conversion rates such as triple, quadruple, and eight times. Even if the upsampling unit performs upsampling at different conversion rates in each upsampling unit, or upsampling in three or more stages, the same effects can be obtained. Furthermore, it is conceivable that each delay unit can select only whether or not to perform delay processing (C1, C2, and C3 are each 0 times or 1 time).
Even if the upsampling unit has one stage (upsampling process is performed once), if delay processing is performed on each of the signals before and after the upsampling unit, the delay processing is performed only on the signal after upsampling. The buffer memory capacity can be suppressed.
In addition, if there are two or more upsampling units (two or more upsampling processes), there are three or more signals with different sampling periods as the signals before and after that, but a delay time is required. Depending on the setting contents (options), it is not always necessary to perform delay processing on all of them, and a configuration in which delay processing is performed on any of two or more (plural) signals is also conceivable.
Also, when the delay switching unit 30 is not provided, and the delay time in each of the delay units 11 to 13 is set at the stage of production of the acoustic signal processing apparatus A, etc., and then fixed (the user cannot change the setting) However, there is no substitute for being able to set the delay time with high accuracy (in the stage of production, etc.) while suppressing the required buffer memory capacity.

  The present invention can be applied to a delay processing apparatus for digital signals such as acoustic digital signals.

The processing block diagram showing the outline of the signal processing which the acoustic signal processing apparatus A which concerns on embodiment of this invention performs. The processing block diagram of the filter part which is an example of the execution program of the acoustic signal processing apparatus A. The processing block diagram of the FIR filter part which is an example of the execution program of the acoustic signal processing apparatus A. The processing block diagram of the channel delay part X which is an example of the execution program of the acoustic signal processing apparatus A. The figure explaining the process of the up-sampling part which is an example of the execution program of the acoustic signal processing apparatus A. FIG. The figure showing the structural example of the buffer memory which the upsampling part which is an example of the execution program of the acoustic signal processing apparatus A uses. The figure showing the setting pattern of the delay time of the channel delay part X. FIG. The block diagram showing the schematic structure of the multiway speaker system which is an example of the conventional acoustic signal processing apparatus.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11, 12, 13 ... Delay part 21,22 ... Upsampling part 30 ... Delay switching part 80 ... Filter part 90 ... Crossover part 91 ... Time alignment part A ... Acoustic signal processing apparatus X ... Channel delay part

Claims (5)

In a digital signal delay device that applies delay processing to an input digital signal,
Up-sampling means for performing up-sampling processing for increasing the sampling rate of the input signal on the digital signal one or more times in succession;
Delay means for performing a delay process for a plurality of signals among the signals before and after each of the upsampling processes, with a delay time that is an integral multiple of the sampling period of the signals;
A digital signal delay device comprising: Delay switching means for switching the delay time and / or switching whether or not to perform delay processing for each of the delay processing by the delay means;
The digital signal delay device according to claim 1, comprising: Filter means for performing filter processing with different filter characteristics on the input digital acoustic signal in parallel and outputting each signal after the filter processing, and a plurality of digital signal delay devices for delaying each output signal of the filter means In an acoustic signal processing apparatus comprising:
An acoustic signal processing apparatus, wherein the digital signal delay apparatus is the digital signal delay apparatus according to claim 1. In a digital signal delay method for delaying an input digital signal,
An up-sampling process in which up-sampling processing for increasing the sampling rate of the input signal is sequentially performed on the digital signal one or more times;
A delay step of performing a delay process of a delay time that is an integral multiple of a sampling period of the signal for each of a plurality of signals before and after each of the upsampling processes;
A digital signal delay method characterized by comprising: In a digital signal delay program for causing a computer to execute a process of performing a delay process on an input digital signal,
An up-sampling process in which up-sampling processing for increasing the sampling rate of the input signal is sequentially performed on the digital signal one or more times;
A delay step of performing a delay process of a delay time that is an integral multiple of the sampling period of the signal for each of a plurality of signals before and after each of the upsampling processes;
A digital signal delay program for causing a computer to execute.

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